1 //===--- SIProgramInfo.h ----------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// Defines struct to track resource usage and hardware flags for kernels and 11 /// entry functions. 12 /// 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H 17 #define LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H 18 19 #include "llvm/IR/CallingConv.h" 20 #include <cstdint> 21 22 namespace llvm { 23 24 /// Track resource usage for kernels / entry functions. 25 struct SIProgramInfo { 26 // Fields set in PGM_RSRC1 pm4 packet. 27 uint32_t VGPRBlocks = 0; 28 uint32_t SGPRBlocks = 0; 29 uint32_t Priority = 0; 30 uint32_t FloatMode = 0; 31 uint32_t Priv = 0; 32 uint32_t DX10Clamp = 0; 33 uint32_t DebugMode = 0; 34 uint32_t IEEEMode = 0; 35 uint32_t WgpMode = 0; // GFX10+ 36 uint32_t MemOrdered = 0; // GFX10+ 37 uint64_t ScratchSize = 0; 38 39 // State used to calculate fields set in PGM_RSRC2 pm4 packet. 40 uint32_t LDSBlocks = 0; 41 uint32_t ScratchBlocks = 0; 42 43 // Fields set in PGM_RSRC2 pm4 packet 44 uint32_t ScratchEnable = 0; 45 uint32_t UserSGPR = 0; 46 uint32_t TrapHandlerEnable = 0; 47 uint32_t TGIdXEnable = 0; 48 uint32_t TGIdYEnable = 0; 49 uint32_t TGIdZEnable = 0; 50 uint32_t TGSizeEnable = 0; 51 uint32_t TIdIGCompCount = 0; 52 uint32_t EXCPEnMSB = 0; 53 uint32_t LdsSize = 0; 54 uint32_t EXCPEnable = 0; 55 56 uint64_t ComputePGMRSrc3GFX90A = 0; 57 58 uint32_t NumVGPR = 0; 59 uint32_t NumArchVGPR = 0; 60 uint32_t NumAccVGPR = 0; 61 uint32_t AccumOffset = 0; 62 uint32_t TgSplit = 0; 63 uint32_t NumSGPR = 0; 64 unsigned SGPRSpill = 0; 65 unsigned VGPRSpill = 0; 66 uint32_t LDSSize = 0; 67 bool FlatUsed = false; 68 69 // Number of SGPRs that meets number of waves per execution unit request. 70 uint32_t NumSGPRsForWavesPerEU = 0; 71 72 // Number of VGPRs that meets number of waves per execution unit request. 73 uint32_t NumVGPRsForWavesPerEU = 0; 74 75 // Final occupancy. 76 uint32_t Occupancy = 0; 77 78 // Whether there is recursion, dynamic allocas, indirect calls or some other 79 // reason there may be statically unknown stack usage. 80 bool DynamicCallStack = false; 81 82 // Bonus information for debugging. 83 bool VCCUsed = false; 84 85 SIProgramInfo() = default; 86 87 /// Compute the value of the ComputePGMRsrc1 register. 88 uint64_t getComputePGMRSrc1() const; 89 uint64_t getPGMRSrc1(CallingConv::ID CC) const; 90 91 /// Compute the value of the ComputePGMRsrc2 register. 92 uint64_t getComputePGMRSrc2() const; 93 uint64_t getPGMRSrc2(CallingConv::ID CC) const; 94 }; 95 96 } // namespace llvm 97 98 #endif // LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H 99