xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h (revision fcaf7f8644a9988098ac6be2165bce3ea4786e91) 
1 //==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15 
16 #include "AMDGPUArgumentUsageInfo.h"
17 #include "AMDGPUMachineFunction.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20 #include "SIInstrInfo.h"
21 #include "llvm/ADT/SetVector.h"
22 #include "llvm/CodeGen/MIRYamlMapping.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/Support/raw_ostream.h"
25 
26 namespace llvm {
27 
28 class MachineFrameInfo;
29 class MachineFunction;
30 class SIMachineFunctionInfo;
31 class SIRegisterInfo;
32 class TargetRegisterClass;
33 
34 class AMDGPUPseudoSourceValue : public PseudoSourceValue {
35 public:
36   enum AMDGPUPSVKind : unsigned {
37     PSVBuffer = PseudoSourceValue::TargetCustom,
38     PSVImage,
39     GWSResource
40   };
41 
42 protected:
43   AMDGPUPseudoSourceValue(unsigned Kind, const AMDGPUTargetMachine &TM)
44       : PseudoSourceValue(Kind, TM) {}
45 
46 public:
47   bool isConstant(const MachineFrameInfo *) const override {
48     // This should probably be true for most images, but we will start by being
49     // conservative.
50     return false;
51   }
52 
53   bool isAliased(const MachineFrameInfo *) const override {
54     return true;
55   }
56 
57   bool mayAlias(const MachineFrameInfo *) const override {
58     return true;
59   }
60 };
61 
62 class AMDGPUBufferPseudoSourceValue final : public AMDGPUPseudoSourceValue {
63 public:
64   explicit AMDGPUBufferPseudoSourceValue(const AMDGPUTargetMachine &TM)
65       : AMDGPUPseudoSourceValue(PSVBuffer, TM) {}
66 
67   static bool classof(const PseudoSourceValue *V) {
68     return V->kind() == PSVBuffer;
69   }
70 
71   void printCustom(raw_ostream &OS) const override { OS << "BufferResource"; }
72 };
73 
74 class AMDGPUImagePseudoSourceValue final : public AMDGPUPseudoSourceValue {
75 public:
76   // TODO: Is the img rsrc useful?
77   explicit AMDGPUImagePseudoSourceValue(const AMDGPUTargetMachine &TM)
78       : AMDGPUPseudoSourceValue(PSVImage, TM) {}
79 
80   static bool classof(const PseudoSourceValue *V) {
81     return V->kind() == PSVImage;
82   }
83 
84   void printCustom(raw_ostream &OS) const override { OS << "ImageResource"; }
85 };
86 
87 class AMDGPUGWSResourcePseudoSourceValue final : public AMDGPUPseudoSourceValue {
88 public:
89   explicit AMDGPUGWSResourcePseudoSourceValue(const AMDGPUTargetMachine &TM)
90       : AMDGPUPseudoSourceValue(GWSResource, TM) {}
91 
92   static bool classof(const PseudoSourceValue *V) {
93     return V->kind() == GWSResource;
94   }
95 
96   // These are inaccessible memory from IR.
97   bool isAliased(const MachineFrameInfo *) const override {
98     return false;
99   }
100 
101   // These are inaccessible memory from IR.
102   bool mayAlias(const MachineFrameInfo *) const override {
103     return false;
104   }
105 
106   void printCustom(raw_ostream &OS) const override {
107     OS << "GWSResource";
108   }
109 };
110 
111 namespace yaml {
112 
113 struct SIArgument {
114   bool IsRegister;
115   union {
116     StringValue RegisterName;
117     unsigned StackOffset;
118   };
119   Optional<unsigned> Mask;
120 
121   // Default constructor, which creates a stack argument.
122   SIArgument() : IsRegister(false), StackOffset(0) {}
123   SIArgument(const SIArgument &Other) {
124     IsRegister = Other.IsRegister;
125     if (IsRegister) {
126       ::new ((void *)std::addressof(RegisterName))
127           StringValue(Other.RegisterName);
128     } else
129       StackOffset = Other.StackOffset;
130     Mask = Other.Mask;
131   }
132   SIArgument &operator=(const SIArgument &Other) {
133     IsRegister = Other.IsRegister;
134     if (IsRegister) {
135       ::new ((void *)std::addressof(RegisterName))
136           StringValue(Other.RegisterName);
137     } else
138       StackOffset = Other.StackOffset;
139     Mask = Other.Mask;
140     return *this;
141   }
142   ~SIArgument() {
143     if (IsRegister)
144       RegisterName.~StringValue();
145   }
146 
147   // Helper to create a register or stack argument.
148   static inline SIArgument createArgument(bool IsReg) {
149     if (IsReg)
150       return SIArgument(IsReg);
151     return SIArgument();
152   }
153 
154 private:
155   // Construct a register argument.
156   SIArgument(bool) : IsRegister(true), RegisterName() {}
157 };
158 
159 template <> struct MappingTraits<SIArgument> {
160   static void mapping(IO &YamlIO, SIArgument &A) {
161     if (YamlIO.outputting()) {
162       if (A.IsRegister)
163         YamlIO.mapRequired("reg", A.RegisterName);
164       else
165         YamlIO.mapRequired("offset", A.StackOffset);
166     } else {
167       auto Keys = YamlIO.keys();
168       if (is_contained(Keys, "reg")) {
169         A = SIArgument::createArgument(true);
170         YamlIO.mapRequired("reg", A.RegisterName);
171       } else if (is_contained(Keys, "offset"))
172         YamlIO.mapRequired("offset", A.StackOffset);
173       else
174         YamlIO.setError("missing required key 'reg' or 'offset'");
175     }
176     YamlIO.mapOptional("mask", A.Mask);
177   }
178   static const bool flow = true;
179 };
180 
181 struct SIArgumentInfo {
182   Optional<SIArgument> PrivateSegmentBuffer;
183   Optional<SIArgument> DispatchPtr;
184   Optional<SIArgument> QueuePtr;
185   Optional<SIArgument> KernargSegmentPtr;
186   Optional<SIArgument> DispatchID;
187   Optional<SIArgument> FlatScratchInit;
188   Optional<SIArgument> PrivateSegmentSize;
189 
190   Optional<SIArgument> WorkGroupIDX;
191   Optional<SIArgument> WorkGroupIDY;
192   Optional<SIArgument> WorkGroupIDZ;
193   Optional<SIArgument> WorkGroupInfo;
194   Optional<SIArgument> LDSKernelId;
195   Optional<SIArgument> PrivateSegmentWaveByteOffset;
196 
197   Optional<SIArgument> ImplicitArgPtr;
198   Optional<SIArgument> ImplicitBufferPtr;
199 
200   Optional<SIArgument> WorkItemIDX;
201   Optional<SIArgument> WorkItemIDY;
202   Optional<SIArgument> WorkItemIDZ;
203 };
204 
205 template <> struct MappingTraits<SIArgumentInfo> {
206   static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
207     YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
208     YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
209     YamlIO.mapOptional("queuePtr", AI.QueuePtr);
210     YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
211     YamlIO.mapOptional("dispatchID", AI.DispatchID);
212     YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
213     YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
214 
215     YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
216     YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
217     YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
218     YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
219     YamlIO.mapOptional("LDSKernelId", AI.LDSKernelId);
220     YamlIO.mapOptional("privateSegmentWaveByteOffset",
221                        AI.PrivateSegmentWaveByteOffset);
222 
223     YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
224     YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
225 
226     YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
227     YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
228     YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
229   }
230 };
231 
232 // Default to default mode for default calling convention.
233 struct SIMode {
234   bool IEEE = true;
235   bool DX10Clamp = true;
236   bool FP32InputDenormals = true;
237   bool FP32OutputDenormals = true;
238   bool FP64FP16InputDenormals = true;
239   bool FP64FP16OutputDenormals = true;
240 
241   SIMode() = default;
242 
243   SIMode(const AMDGPU::SIModeRegisterDefaults &Mode) {
244     IEEE = Mode.IEEE;
245     DX10Clamp = Mode.DX10Clamp;
246     FP32InputDenormals = Mode.FP32InputDenormals;
247     FP32OutputDenormals = Mode.FP32OutputDenormals;
248     FP64FP16InputDenormals = Mode.FP64FP16InputDenormals;
249     FP64FP16OutputDenormals = Mode.FP64FP16OutputDenormals;
250   }
251 
252   bool operator ==(const SIMode Other) const {
253     return IEEE == Other.IEEE &&
254            DX10Clamp == Other.DX10Clamp &&
255            FP32InputDenormals == Other.FP32InputDenormals &&
256            FP32OutputDenormals == Other.FP32OutputDenormals &&
257            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
258            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
259   }
260 };
261 
262 template <> struct MappingTraits<SIMode> {
263   static void mapping(IO &YamlIO, SIMode &Mode) {
264     YamlIO.mapOptional("ieee", Mode.IEEE, true);
265     YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
266     YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);
267     YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);
268     YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);
269     YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);
270   }
271 };
272 
273 struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
274   uint64_t ExplicitKernArgSize = 0;
275   Align MaxKernArgAlign;
276   uint32_t LDSSize = 0;
277   uint32_t GDSSize = 0;
278   Align DynLDSAlign;
279   bool IsEntryFunction = false;
280   bool NoSignedZerosFPMath = false;
281   bool MemoryBound = false;
282   bool WaveLimiter = false;
283   bool HasSpilledSGPRs = false;
284   bool HasSpilledVGPRs = false;
285   uint32_t HighBitsOf32BitAddress = 0;
286 
287   // TODO: 10 may be a better default since it's the maximum.
288   unsigned Occupancy = 0;
289 
290   SmallVector<StringValue> WWMReservedRegs;
291 
292   StringValue ScratchRSrcReg = "$private_rsrc_reg";
293   StringValue FrameOffsetReg = "$fp_reg";
294   StringValue StackPtrOffsetReg = "$sp_reg";
295 
296   unsigned BytesInStackArgArea = 0;
297   bool ReturnsVoid = true;
298 
299   Optional<SIArgumentInfo> ArgInfo;
300   SIMode Mode;
301   Optional<FrameIndex> ScavengeFI;
302   StringValue VGPRForAGPRCopy;
303 
304   SIMachineFunctionInfo() = default;
305   SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
306                         const TargetRegisterInfo &TRI,
307                         const llvm::MachineFunction &MF);
308 
309   void mappingImpl(yaml::IO &YamlIO) override;
310   ~SIMachineFunctionInfo() = default;
311 };
312 
313 template <> struct MappingTraits<SIMachineFunctionInfo> {
314   static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
315     YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
316                        UINT64_C(0));
317     YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign);
318     YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
319     YamlIO.mapOptional("gdsSize", MFI.GDSSize, 0u);
320     YamlIO.mapOptional("dynLDSAlign", MFI.DynLDSAlign, Align());
321     YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
322     YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
323     YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
324     YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
325     YamlIO.mapOptional("hasSpilledSGPRs", MFI.HasSpilledSGPRs, false);
326     YamlIO.mapOptional("hasSpilledVGPRs", MFI.HasSpilledVGPRs, false);
327     YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
328                        StringValue("$private_rsrc_reg"));
329     YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
330                        StringValue("$fp_reg"));
331     YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
332                        StringValue("$sp_reg"));
333     YamlIO.mapOptional("bytesInStackArgArea", MFI.BytesInStackArgArea, 0u);
334     YamlIO.mapOptional("returnsVoid", MFI.ReturnsVoid, true);
335     YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
336     YamlIO.mapOptional("mode", MFI.Mode, SIMode());
337     YamlIO.mapOptional("highBitsOf32BitAddress",
338                        MFI.HighBitsOf32BitAddress, 0u);
339     YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
340     YamlIO.mapOptional("wwmReservedRegs", MFI.WWMReservedRegs);
341     YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
342     YamlIO.mapOptional("vgprForAGPRCopy", MFI.VGPRForAGPRCopy,
343                        StringValue()); // Don't print out when it's empty.
344   }
345 };
346 
347 } // end namespace yaml
348 
349 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
350 /// tells the hardware which interpolation parameters to load.
351 class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
352   friend class GCNTargetMachine;
353 
354   // Registers that may be reserved for spilling purposes. These may be the same
355   // as the input registers.
356   Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
357 
358   // This is the the unswizzled offset from the current dispatch's scratch wave
359   // base to the beginning of the current function's frame.
360   Register FrameOffsetReg = AMDGPU::FP_REG;
361 
362   // This is an ABI register used in the non-entry calling convention to
363   // communicate the unswizzled offset from the current dispatch's scratch wave
364   // base to the beginning of the new function's frame.
365   Register StackPtrOffsetReg = AMDGPU::SP_REG;
366 
367   AMDGPUFunctionArgInfo ArgInfo;
368 
369   // Graphics info.
370   unsigned PSInputAddr = 0;
371   unsigned PSInputEnable = 0;
372 
373   /// Number of bytes of arguments this function has on the stack. If the callee
374   /// is expected to restore the argument stack this should be a multiple of 16,
375   /// all usable during a tail call.
376   ///
377   /// The alternative would forbid tail call optimisation in some cases: if we
378   /// want to transfer control from a function with 8-bytes of stack-argument
379   /// space to a function with 16-bytes then misalignment of this value would
380   /// make a stack adjustment necessary, which could not be undone by the
381   /// callee.
382   unsigned BytesInStackArgArea = 0;
383 
384   bool ReturnsVoid = true;
385 
386   // A pair of default/requested minimum/maximum flat work group sizes.
387   // Minimum - first, maximum - second.
388   std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
389 
390   // A pair of default/requested minimum/maximum number of waves per execution
391   // unit. Minimum - first, maximum - second.
392   std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
393 
394   const AMDGPUBufferPseudoSourceValue BufferPSV;
395   const AMDGPUImagePseudoSourceValue ImagePSV;
396   const AMDGPUGWSResourcePseudoSourceValue GWSResourcePSV;
397 
398 private:
399   unsigned NumUserSGPRs = 0;
400   unsigned NumSystemSGPRs = 0;
401 
402   bool HasSpilledSGPRs = false;
403   bool HasSpilledVGPRs = false;
404   bool HasNonSpillStackObjects = false;
405   bool IsStackRealigned = false;
406 
407   unsigned NumSpilledSGPRs = 0;
408   unsigned NumSpilledVGPRs = 0;
409 
410   // Feature bits required for inputs passed in user SGPRs.
411   bool PrivateSegmentBuffer : 1;
412   bool DispatchPtr : 1;
413   bool QueuePtr : 1;
414   bool KernargSegmentPtr : 1;
415   bool DispatchID : 1;
416   bool FlatScratchInit : 1;
417 
418   // Feature bits required for inputs passed in system SGPRs.
419   bool WorkGroupIDX : 1; // Always initialized.
420   bool WorkGroupIDY : 1;
421   bool WorkGroupIDZ : 1;
422   bool WorkGroupInfo : 1;
423   bool LDSKernelId : 1;
424   bool PrivateSegmentWaveByteOffset : 1;
425 
426   bool WorkItemIDX : 1; // Always initialized.
427   bool WorkItemIDY : 1;
428   bool WorkItemIDZ : 1;
429 
430   // Private memory buffer
431   // Compute directly in sgpr[0:1]
432   // Other shaders indirect 64-bits at sgpr[0:1]
433   bool ImplicitBufferPtr : 1;
434 
435   // Pointer to where the ABI inserts special kernel arguments separate from the
436   // user arguments. This is an offset from the KernargSegmentPtr.
437   bool ImplicitArgPtr : 1;
438 
439   bool MayNeedAGPRs : 1;
440 
441   // The hard-wired high half of the address of the global information table
442   // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
443   // current hardware only allows a 16 bit value.
444   unsigned GITPtrHigh;
445 
446   unsigned HighBitsOf32BitAddress;
447 
448   // Current recorded maximum possible occupancy.
449   unsigned Occupancy;
450 
451   mutable Optional<bool> UsesAGPRs;
452 
453   MCPhysReg getNextUserSGPR() const;
454 
455   MCPhysReg getNextSystemSGPR() const;
456 
457 public:
458   struct SGPRSpillVGPR {
459     // VGPR used for SGPR spills
460     Register VGPR;
461 
462     // If the VGPR is is used for SGPR spills in a non-entrypoint function, the
463     // stack slot used to save/restore it in the prolog/epilog.
464     Optional<int> FI;
465 
466     SGPRSpillVGPR(Register V, Optional<int> F) : VGPR(V), FI(F) {}
467   };
468 
469   struct VGPRSpillToAGPR {
470     SmallVector<MCPhysReg, 32> Lanes;
471     bool FullyAllocated = false;
472     bool IsDead = false;
473   };
474 
475   // Track VGPRs reserved for WWM.
476   SmallSetVector<Register, 8> WWMReservedRegs;
477 
478   /// Track stack slots used for save/restore of reserved WWM VGPRs in the
479   /// prolog/epilog.
480 
481   /// FIXME: This is temporary state only needed in PrologEpilogInserter, and
482   /// doesn't really belong here. It does not require serialization
483   SmallVector<int, 8> WWMReservedFrameIndexes;
484 
485   void allocateWWMReservedSpillSlots(MachineFrameInfo &MFI,
486                                      const SIRegisterInfo &TRI);
487 
488   auto wwmAllocation() const {
489     assert(WWMReservedRegs.size() == WWMReservedFrameIndexes.size());
490     return zip(WWMReservedRegs, WWMReservedFrameIndexes);
491   }
492 
493 private:
494   // Track VGPR + wave index for each subregister of the SGPR spilled to
495   // frameindex key.
496   DenseMap<int, std::vector<SIRegisterInfo::SpilledReg>> SGPRToVGPRSpills;
497   unsigned NumVGPRSpillLanes = 0;
498   SmallVector<SGPRSpillVGPR, 2> SpillVGPRs;
499 
500   DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
501 
502   // AGPRs used for VGPR spills.
503   SmallVector<MCPhysReg, 32> SpillAGPR;
504 
505   // VGPRs used for AGPR spills.
506   SmallVector<MCPhysReg, 32> SpillVGPR;
507 
508   // Emergency stack slot. Sometimes, we create this before finalizing the stack
509   // frame, so save it here and add it to the RegScavenger later.
510   Optional<int> ScavengeFI;
511 
512 private:
513   Register VGPRForAGPRCopy;
514 
515 public:
516   Register getVGPRForAGPRCopy() const {
517     return VGPRForAGPRCopy;
518   }
519 
520   void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy) {
521     VGPRForAGPRCopy = NewVGPRForAGPRCopy;
522   }
523 
524 public: // FIXME
525   /// If this is set, an SGPR used for save/restore of the register used for the
526   /// frame pointer.
527   Register SGPRForFPSaveRestoreCopy;
528   Optional<int> FramePointerSaveIndex;
529 
530   /// If this is set, an SGPR used for save/restore of the register used for the
531   /// base pointer.
532   Register SGPRForBPSaveRestoreCopy;
533   Optional<int> BasePointerSaveIndex;
534 
535   bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg);
536 
537 public:
538   SIMachineFunctionInfo(const MachineFunction &MF);
539   SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI) = default;
540 
541   MachineFunctionInfo *
542   clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
543         const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
544       const override;
545 
546   bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI,
547                                 const MachineFunction &MF,
548                                 PerFunctionMIParsingState &PFS,
549                                 SMDiagnostic &Error, SMRange &SourceRange);
550 
551   void reserveWWMRegister(Register Reg) {
552     WWMReservedRegs.insert(Reg);
553   }
554 
555   ArrayRef<SIRegisterInfo::SpilledReg>
556   getSGPRToVGPRSpills(int FrameIndex) const {
557     auto I = SGPRToVGPRSpills.find(FrameIndex);
558     return (I == SGPRToVGPRSpills.end())
559                ? ArrayRef<SIRegisterInfo::SpilledReg>()
560                : makeArrayRef(I->second);
561   }
562 
563   ArrayRef<SGPRSpillVGPR> getSGPRSpillVGPRs() const { return SpillVGPRs; }
564 
565   ArrayRef<MCPhysReg> getAGPRSpillVGPRs() const {
566     return SpillAGPR;
567   }
568 
569   ArrayRef<MCPhysReg> getVGPRSpillAGPRs() const {
570     return SpillVGPR;
571   }
572 
573   MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
574     auto I = VGPRToAGPRSpills.find(FrameIndex);
575     return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
576                                          : I->second.Lanes[Lane];
577   }
578 
579   void setVGPRToAGPRSpillDead(int FrameIndex) {
580     auto I = VGPRToAGPRSpills.find(FrameIndex);
581     if (I != VGPRToAGPRSpills.end())
582       I->second.IsDead = true;
583   }
584 
585   bool haveFreeLanesForSGPRSpill(const MachineFunction &MF,
586                                  unsigned NumLane) const;
587   bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
588   bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
589 
590   /// If \p ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill
591   /// to the default stack.
592   bool removeDeadFrameIndices(MachineFrameInfo &MFI,
593                               bool ResetSGPRSpillStackIDs);
594 
595   int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI);
596   Optional<int> getOptionalScavengeFI() const { return ScavengeFI; }
597 
598   unsigned getBytesInStackArgArea() const {
599     return BytesInStackArgArea;
600   }
601 
602   void setBytesInStackArgArea(unsigned Bytes) {
603     BytesInStackArgArea = Bytes;
604   }
605 
606   // Add user SGPRs.
607   Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
608   Register addDispatchPtr(const SIRegisterInfo &TRI);
609   Register addQueuePtr(const SIRegisterInfo &TRI);
610   Register addKernargSegmentPtr(const SIRegisterInfo &TRI);
611   Register addDispatchID(const SIRegisterInfo &TRI);
612   Register addFlatScratchInit(const SIRegisterInfo &TRI);
613   Register addImplicitBufferPtr(const SIRegisterInfo &TRI);
614   Register addLDSKernelId();
615 
616   /// Increment user SGPRs used for padding the argument list only.
617   Register addReservedUserSGPR() {
618     Register Next = getNextUserSGPR();
619     ++NumUserSGPRs;
620     return Next;
621   }
622 
623   // Add system SGPRs.
624   Register addWorkGroupIDX() {
625     ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
626     NumSystemSGPRs += 1;
627     return ArgInfo.WorkGroupIDX.getRegister();
628   }
629 
630   Register addWorkGroupIDY() {
631     ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
632     NumSystemSGPRs += 1;
633     return ArgInfo.WorkGroupIDY.getRegister();
634   }
635 
636   Register addWorkGroupIDZ() {
637     ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
638     NumSystemSGPRs += 1;
639     return ArgInfo.WorkGroupIDZ.getRegister();
640   }
641 
642   Register addWorkGroupInfo() {
643     ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
644     NumSystemSGPRs += 1;
645     return ArgInfo.WorkGroupInfo.getRegister();
646   }
647 
648   // Add special VGPR inputs
649   void setWorkItemIDX(ArgDescriptor Arg) {
650     ArgInfo.WorkItemIDX = Arg;
651   }
652 
653   void setWorkItemIDY(ArgDescriptor Arg) {
654     ArgInfo.WorkItemIDY = Arg;
655   }
656 
657   void setWorkItemIDZ(ArgDescriptor Arg) {
658     ArgInfo.WorkItemIDZ = Arg;
659   }
660 
661   Register addPrivateSegmentWaveByteOffset() {
662     ArgInfo.PrivateSegmentWaveByteOffset
663       = ArgDescriptor::createRegister(getNextSystemSGPR());
664     NumSystemSGPRs += 1;
665     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
666   }
667 
668   void setPrivateSegmentWaveByteOffset(Register Reg) {
669     ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
670   }
671 
672   bool hasPrivateSegmentBuffer() const {
673     return PrivateSegmentBuffer;
674   }
675 
676   bool hasDispatchPtr() const {
677     return DispatchPtr;
678   }
679 
680   bool hasQueuePtr() const {
681     return QueuePtr;
682   }
683 
684   bool hasKernargSegmentPtr() const {
685     return KernargSegmentPtr;
686   }
687 
688   bool hasDispatchID() const {
689     return DispatchID;
690   }
691 
692   bool hasFlatScratchInit() const {
693     return FlatScratchInit;
694   }
695 
696   bool hasWorkGroupIDX() const {
697     return WorkGroupIDX;
698   }
699 
700   bool hasWorkGroupIDY() const {
701     return WorkGroupIDY;
702   }
703 
704   bool hasWorkGroupIDZ() const {
705     return WorkGroupIDZ;
706   }
707 
708   bool hasWorkGroupInfo() const {
709     return WorkGroupInfo;
710   }
711 
712   bool hasLDSKernelId() const { return LDSKernelId; }
713 
714   bool hasPrivateSegmentWaveByteOffset() const {
715     return PrivateSegmentWaveByteOffset;
716   }
717 
718   bool hasWorkItemIDX() const {
719     return WorkItemIDX;
720   }
721 
722   bool hasWorkItemIDY() const {
723     return WorkItemIDY;
724   }
725 
726   bool hasWorkItemIDZ() const {
727     return WorkItemIDZ;
728   }
729 
730   bool hasImplicitArgPtr() const {
731     return ImplicitArgPtr;
732   }
733 
734   bool hasImplicitBufferPtr() const {
735     return ImplicitBufferPtr;
736   }
737 
738   AMDGPUFunctionArgInfo &getArgInfo() {
739     return ArgInfo;
740   }
741 
742   const AMDGPUFunctionArgInfo &getArgInfo() const {
743     return ArgInfo;
744   }
745 
746   std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
747   getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
748     return ArgInfo.getPreloadedValue(Value);
749   }
750 
751   MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
752     auto Arg = std::get<0>(ArgInfo.getPreloadedValue(Value));
753     return Arg ? Arg->getRegister() : MCRegister();
754   }
755 
756   unsigned getGITPtrHigh() const {
757     return GITPtrHigh;
758   }
759 
760   Register getGITPtrLoReg(const MachineFunction &MF) const;
761 
762   uint32_t get32BitAddressHighBits() const {
763     return HighBitsOf32BitAddress;
764   }
765 
766   unsigned getNumUserSGPRs() const {
767     return NumUserSGPRs;
768   }
769 
770   unsigned getNumPreloadedSGPRs() const {
771     return NumUserSGPRs + NumSystemSGPRs;
772   }
773 
774   Register getPrivateSegmentWaveByteOffsetSystemSGPR() const {
775     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
776   }
777 
778   /// Returns the physical register reserved for use as the resource
779   /// descriptor for scratch accesses.
780   Register getScratchRSrcReg() const {
781     return ScratchRSrcReg;
782   }
783 
784   void setScratchRSrcReg(Register Reg) {
785     assert(Reg != 0 && "Should never be unset");
786     ScratchRSrcReg = Reg;
787   }
788 
789   Register getFrameOffsetReg() const {
790     return FrameOffsetReg;
791   }
792 
793   void setFrameOffsetReg(Register Reg) {
794     assert(Reg != 0 && "Should never be unset");
795     FrameOffsetReg = Reg;
796   }
797 
798   void setStackPtrOffsetReg(Register Reg) {
799     assert(Reg != 0 && "Should never be unset");
800     StackPtrOffsetReg = Reg;
801   }
802 
803   // Note the unset value for this is AMDGPU::SP_REG rather than
804   // NoRegister. This is mostly a workaround for MIR tests where state that
805   // can't be directly computed from the function is not preserved in serialized
806   // MIR.
807   Register getStackPtrOffsetReg() const {
808     return StackPtrOffsetReg;
809   }
810 
811   Register getQueuePtrUserSGPR() const {
812     return ArgInfo.QueuePtr.getRegister();
813   }
814 
815   Register getImplicitBufferPtrUserSGPR() const {
816     return ArgInfo.ImplicitBufferPtr.getRegister();
817   }
818 
819   bool hasSpilledSGPRs() const {
820     return HasSpilledSGPRs;
821   }
822 
823   void setHasSpilledSGPRs(bool Spill = true) {
824     HasSpilledSGPRs = Spill;
825   }
826 
827   bool hasSpilledVGPRs() const {
828     return HasSpilledVGPRs;
829   }
830 
831   void setHasSpilledVGPRs(bool Spill = true) {
832     HasSpilledVGPRs = Spill;
833   }
834 
835   bool hasNonSpillStackObjects() const {
836     return HasNonSpillStackObjects;
837   }
838 
839   void setHasNonSpillStackObjects(bool StackObject = true) {
840     HasNonSpillStackObjects = StackObject;
841   }
842 
843   bool isStackRealigned() const {
844     return IsStackRealigned;
845   }
846 
847   void setIsStackRealigned(bool Realigned = true) {
848     IsStackRealigned = Realigned;
849   }
850 
851   unsigned getNumSpilledSGPRs() const {
852     return NumSpilledSGPRs;
853   }
854 
855   unsigned getNumSpilledVGPRs() const {
856     return NumSpilledVGPRs;
857   }
858 
859   void addToSpilledSGPRs(unsigned num) {
860     NumSpilledSGPRs += num;
861   }
862 
863   void addToSpilledVGPRs(unsigned num) {
864     NumSpilledVGPRs += num;
865   }
866 
867   unsigned getPSInputAddr() const {
868     return PSInputAddr;
869   }
870 
871   unsigned getPSInputEnable() const {
872     return PSInputEnable;
873   }
874 
875   bool isPSInputAllocated(unsigned Index) const {
876     return PSInputAddr & (1 << Index);
877   }
878 
879   void markPSInputAllocated(unsigned Index) {
880     PSInputAddr |= 1 << Index;
881   }
882 
883   void markPSInputEnabled(unsigned Index) {
884     PSInputEnable |= 1 << Index;
885   }
886 
887   bool returnsVoid() const {
888     return ReturnsVoid;
889   }
890 
891   void setIfReturnsVoid(bool Value) {
892     ReturnsVoid = Value;
893   }
894 
895   /// \returns A pair of default/requested minimum/maximum flat work group sizes
896   /// for this function.
897   std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
898     return FlatWorkGroupSizes;
899   }
900 
901   /// \returns Default/requested minimum flat work group size for this function.
902   unsigned getMinFlatWorkGroupSize() const {
903     return FlatWorkGroupSizes.first;
904   }
905 
906   /// \returns Default/requested maximum flat work group size for this function.
907   unsigned getMaxFlatWorkGroupSize() const {
908     return FlatWorkGroupSizes.second;
909   }
910 
911   /// \returns A pair of default/requested minimum/maximum number of waves per
912   /// execution unit.
913   std::pair<unsigned, unsigned> getWavesPerEU() const {
914     return WavesPerEU;
915   }
916 
917   /// \returns Default/requested minimum number of waves per execution unit.
918   unsigned getMinWavesPerEU() const {
919     return WavesPerEU.first;
920   }
921 
922   /// \returns Default/requested maximum number of waves per execution unit.
923   unsigned getMaxWavesPerEU() const {
924     return WavesPerEU.second;
925   }
926 
927   /// \returns SGPR used for \p Dim's work group ID.
928   Register getWorkGroupIDSGPR(unsigned Dim) const {
929     switch (Dim) {
930     case 0:
931       assert(hasWorkGroupIDX());
932       return ArgInfo.WorkGroupIDX.getRegister();
933     case 1:
934       assert(hasWorkGroupIDY());
935       return ArgInfo.WorkGroupIDY.getRegister();
936     case 2:
937       assert(hasWorkGroupIDZ());
938       return ArgInfo.WorkGroupIDZ.getRegister();
939     }
940     llvm_unreachable("unexpected dimension");
941   }
942 
943   const AMDGPUBufferPseudoSourceValue *
944   getBufferPSV(const AMDGPUTargetMachine &TM) {
945     return &BufferPSV;
946   }
947 
948   const AMDGPUImagePseudoSourceValue *
949   getImagePSV(const AMDGPUTargetMachine &TM) {
950     return &ImagePSV;
951   }
952 
953   const AMDGPUGWSResourcePseudoSourceValue *
954   getGWSPSV(const AMDGPUTargetMachine &TM) {
955     return &GWSResourcePSV;
956   }
957 
958   unsigned getOccupancy() const {
959     return Occupancy;
960   }
961 
962   unsigned getMinAllowedOccupancy() const {
963     if (!isMemoryBound() && !needsWaveLimiter())
964       return Occupancy;
965     return (Occupancy < 4) ? Occupancy : 4;
966   }
967 
968   void limitOccupancy(const MachineFunction &MF);
969 
970   void limitOccupancy(unsigned Limit) {
971     if (Occupancy > Limit)
972       Occupancy = Limit;
973   }
974 
975   void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
976     if (Occupancy < Limit)
977       Occupancy = Limit;
978     limitOccupancy(MF);
979   }
980 
981   bool mayNeedAGPRs() const {
982     return MayNeedAGPRs;
983   }
984 
985   // \returns true if a function has a use of AGPRs via inline asm or
986   // has a call which may use it.
987   bool mayUseAGPRs(const MachineFunction &MF) const;
988 
989   // \returns true if a function needs or may need AGPRs.
990   bool usesAGPRs(const MachineFunction &MF) const;
991 };
992 
993 } // end namespace llvm
994 
995 #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
996