1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// SI Instruction format definitions. 10// 11//===----------------------------------------------------------------------===// 12 13class InstSI <dag outs, dag ins, string asm = "", 14 list<dag> pattern = []> : 15 AMDGPUInst<outs, ins, asm, pattern>, GCNPredicateControl { 16 // Low bits - basic encoding information. 17 field bit SALU = 0; 18 field bit VALU = 0; 19 20 // SALU instruction formats. 21 field bit SOP1 = 0; 22 field bit SOP2 = 0; 23 field bit SOPC = 0; 24 field bit SOPK = 0; 25 field bit SOPP = 0; 26 27 // VALU instruction formats. 28 field bit VOP1 = 0; 29 field bit VOP2 = 0; 30 field bit VOPC = 0; 31 field bit VOP3 = 0; 32 field bit VOP3P = 0; 33 field bit VINTRP = 0; 34 field bit SDWA = 0; 35 field bit DPP = 0; 36 field bit TRANS = 0; 37 38 // Memory instruction formats. 39 field bit MUBUF = 0; 40 field bit MTBUF = 0; 41 field bit SMRD = 0; 42 field bit MIMG = 0; 43 field bit VIMAGE = 0; 44 field bit VSAMPLE = 0; 45 field bit EXP = 0; 46 field bit FLAT = 0; 47 field bit DS = 0; 48 49 // Pseudo instruction formats. 50 field bit VGPRSpill = 0; 51 field bit SGPRSpill = 0; 52 53 // LDSDIR instruction format. 54 field bit LDSDIR = 0; 55 56 // VINTERP instruction format. 57 field bit VINTERP = 0; 58 59 // High bits - other information. 60 field bit VM_CNT = 0; 61 field bit EXP_CNT = 0; 62 field bit LGKM_CNT = 0; 63 64 // Whether WQM _must_ be enabled for this instruction. 65 field bit WQM = 0; 66 67 // Whether WQM _must_ be disabled for this instruction. 68 field bit DisableWQM = 0; 69 70 field bit Gather4 = 0; 71 72 // Most sopk treat the immediate as a signed 16-bit, however some 73 // use it as unsigned. 74 field bit SOPKZext = 0; 75 76 // This is an s_store_dword* instruction that requires a cache flush 77 // on wave termination. It is necessary to distinguish from mayStore 78 // SMEM instructions like the cache flush ones. 79 field bit ScalarStore = 0; 80 81 // Whether the operands can be ignored when computing the 82 // instruction size. 83 field bit FixedSize = 0; 84 85 // This bit tells the assembler to use the 32-bit encoding in case it 86 // is unable to infer the encoding from the operands. 87 field bit VOPAsmPrefer32Bit = 0; 88 89 // This bit indicates that this is a VOP3 opcode which supports op_sel 90 // modifier. 91 field bit VOP3_OPSEL = 0; 92 93 // Is it possible for this instruction to be atomic? 94 field bit maybeAtomic = 1; 95 96 // This bit indicates that this is a VI instruction which is renamed 97 // in GFX9. Required for correct mapping from pseudo to MC. 98 field bit renamedInGFX9 = 0; 99 100 // This bit indicates that this has a floating point result type, so 101 // the clamp modifier has floating point semantics. 102 field bit FPClamp = 0; 103 104 // This bit indicates that instruction may support integer clamping 105 // which depends on GPU features. 106 field bit IntClamp = 0; 107 108 // This field indicates that the clamp applies to the low component 109 // of a packed output register. 110 field bit ClampLo = 0; 111 112 // This field indicates that the clamp applies to the high component 113 // of a packed output register. 114 field bit ClampHi = 0; 115 116 // This bit indicates that this is a packed VOP3P instruction 117 field bit IsPacked = 0; 118 119 // This bit indicates that this is a D16 buffer instruction. 120 field bit D16Buf = 0; 121 122 // This field indicates that FLAT instruction accesses FLAT_GLBL segment. 123 // Must be 0 for non-FLAT instructions. 124 field bit FlatGlobal = 0; 125 126 // Reads the mode register, usually for FP environment. 127 field bit ReadsModeReg = 0; 128 129 // This bit indicates that this uses the floating point double precision 130 // rounding mode flags 131 field bit FPDPRounding = 0; 132 133 // Instruction is FP atomic. 134 field bit FPAtomic = 0; 135 136 // This bit indicates that this is one of MFMA instructions. 137 field bit IsMAI = 0; 138 139 // This bit indicates that this is one of DOT instructions. 140 field bit IsDOT = 0; 141 142 // This field indicates that FLAT instruction accesses FLAT_SCRATCH segment. 143 // Must be 0 for non-FLAT instructions. 144 field bit FlatScratch = 0; 145 146 // Atomic without a return. 147 field bit IsAtomicNoRet = 0; 148 149 // Atomic with return. 150 field bit IsAtomicRet = 0; 151 152 // This bit indicates that this is one of WMMA instructions. 153 field bit IsWMMA = 0; 154 155 // This bit indicates that tied source will not be read. 156 field bit TiedSourceNotRead = 0; 157 158 // This bit indicates that the instruction is never-uniform/divergent 159 field bit IsNeverUniform = 0; 160 161 // ds_gws_* instructions. 162 field bit GWS = 0; 163 164 // This bit indicates that this is one of SWMMAC instructions. 165 field bit IsSWMMAC = 0; 166 167 // These need to be kept in sync with the enum in SIInstrFlags. 168 let TSFlags{0} = SALU; 169 let TSFlags{1} = VALU; 170 171 let TSFlags{2} = SOP1; 172 let TSFlags{3} = SOP2; 173 let TSFlags{4} = SOPC; 174 let TSFlags{5} = SOPK; 175 let TSFlags{6} = SOPP; 176 177 let TSFlags{7} = VOP1; 178 let TSFlags{8} = VOP2; 179 let TSFlags{9} = VOPC; 180 let TSFlags{10} = VOP3; 181 let TSFlags{12} = VOP3P; 182 183 let TSFlags{13} = VINTRP; 184 let TSFlags{14} = SDWA; 185 let TSFlags{15} = DPP; 186 let TSFlags{16} = TRANS; 187 188 let TSFlags{17} = MUBUF; 189 let TSFlags{18} = MTBUF; 190 let TSFlags{19} = SMRD; 191 let TSFlags{20} = MIMG; 192 let TSFlags{21} = VIMAGE; 193 let TSFlags{22} = VSAMPLE; 194 let TSFlags{23} = EXP; 195 let TSFlags{24} = FLAT; 196 let TSFlags{25} = DS; 197 198 let TSFlags{26} = VGPRSpill; 199 let TSFlags{27} = SGPRSpill; 200 201 let TSFlags{28} = LDSDIR; 202 let TSFlags{29} = VINTERP; 203 204 let TSFlags{32} = VM_CNT; 205 let TSFlags{33} = EXP_CNT; 206 let TSFlags{34} = LGKM_CNT; 207 208 let TSFlags{35} = WQM; 209 let TSFlags{36} = DisableWQM; 210 let TSFlags{37} = Gather4; 211 212 let TSFlags{38} = SOPKZext; 213 let TSFlags{39} = ScalarStore; 214 let TSFlags{40} = FixedSize; 215 let TSFlags{41} = VOPAsmPrefer32Bit; 216 let TSFlags{42} = VOP3_OPSEL; 217 218 let TSFlags{43} = maybeAtomic; 219 let TSFlags{44} = renamedInGFX9; 220 221 let TSFlags{45} = FPClamp; 222 let TSFlags{46} = IntClamp; 223 let TSFlags{47} = ClampLo; 224 let TSFlags{48} = ClampHi; 225 226 let TSFlags{49} = IsPacked; 227 228 let TSFlags{50} = D16Buf; 229 230 let TSFlags{51} = FlatGlobal; 231 232 let TSFlags{52} = FPDPRounding; 233 234 let TSFlags{53} = FPAtomic; 235 236 let TSFlags{54} = IsMAI; 237 238 let TSFlags{55} = IsDOT; 239 240 let TSFlags{56} = FlatScratch; 241 242 let TSFlags{57} = IsAtomicNoRet; 243 244 let TSFlags{58} = IsAtomicRet; 245 246 let TSFlags{59} = IsWMMA; 247 248 let TSFlags{60} = TiedSourceNotRead; 249 250 let TSFlags{61} = IsNeverUniform; 251 252 let TSFlags{62} = GWS; 253 254 let TSFlags{63} = IsSWMMAC; 255 256 let SchedRW = [Write32Bit]; 257 258 let AsmVariantName = AMDGPUAsmVariants.Default; 259 260 // Avoid changing source registers in a way that violates constant bus read limitations. 261 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU); 262} 263 264class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = ""> 265 : InstSI<outs, ins, asm, pattern> { 266 let isPseudo = 1; 267 let isCodeGenOnly = 1; 268} 269 270class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = ""> 271 : PseudoInstSI<outs, ins, pattern, asm> { 272 let SALU = 1; 273} 274 275class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = ""> 276 : PseudoInstSI<outs, ins, pattern, asm> { 277 let VALU = 1; 278 let Uses = [EXEC]; 279} 280 281class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], 282 bit UseExec = 0, bit DefExec = 0> : 283 SPseudoInstSI<outs, ins, pattern> { 284 285 let Uses = !if(UseExec, [EXEC], []); 286 let Defs = !if(DefExec, [EXEC, SCC], [SCC]); 287 let mayLoad = 0; 288 let mayStore = 0; 289 let hasSideEffects = 0; 290} 291 292class Enc32 { 293 field bits<32> Inst; 294 int Size = 4; 295} 296 297class Enc64 { 298 field bits<64> Inst; 299 int Size = 8; 300} 301 302class Enc96 { 303 field bits<96> Inst; 304 int Size = 12; 305} 306 307def CPolBit { 308 int GLC = 0; 309 int SLC = 1; 310 int DLC = 2; 311 int SCC = 4; 312} 313 314class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">; 315 316def VOPDstOperand_t16 : VOPDstOperand <VGPR_16> { 317 let EncoderMethod = "getMachineOpValueT16"; 318 let DecoderMethod = "DecodeVGPR_16RegisterClass"; 319} 320 321def VOPDstOperand_t16Lo128 : VOPDstOperand <VGPR_16_Lo128> { 322 let EncoderMethod = "getMachineOpValueT16Lo128"; 323 let DecoderMethod = "DecodeVGPR_16_Lo128RegisterClass"; 324} 325 326class VINTRPe <bits<2> op> : Enc32 { 327 bits<8> vdst; 328 bits<8> vsrc; 329 bits<2> attrchan; 330 bits<6> attr; 331 332 let Inst{7-0} = vsrc; 333 let Inst{9-8} = attrchan; 334 let Inst{15-10} = attr; 335 let Inst{17-16} = op; 336 let Inst{25-18} = vdst; 337 let Inst{31-26} = 0x32; // encoding 338} 339 340class MIMGe_gfxpre11 : Enc64 { 341 bits<10> vdata; 342 bits<4> dmask; 343 bits<1> unorm; 344 bits<5> cpol; 345 bits<1> r128; 346 bits<1> tfe; 347 bits<1> lwe; 348 bit d16; 349 bits<7> srsrc; 350 bits<7> ssamp; 351 352 let Inst{11-8} = dmask; 353 let Inst{12} = unorm; 354 let Inst{13} = cpol{CPolBit.GLC}; 355 let Inst{15} = r128; 356 let Inst{17} = lwe; 357 let Inst{25} = cpol{CPolBit.SLC}; 358 let Inst{31-26} = 0x3c; 359 let Inst{47-40} = vdata{7-0}; 360 let Inst{52-48} = srsrc{6-2}; 361 let Inst{57-53} = ssamp{6-2}; 362 let Inst{63} = d16; 363} 364 365class MIMGe_gfx6789 <bits<8> op> : MIMGe_gfxpre11 { 366 bits<8> vaddr; 367 bits<1> da; 368 369 let Inst{0} = op{7}; 370 let Inst{7} = cpol{CPolBit.SCC}; 371 let Inst{14} = da; 372 let Inst{16} = tfe; 373 let Inst{24-18} = op{6-0}; 374 let Inst{39-32} = vaddr; 375} 376 377class MIMGe_gfx90a <bits<8> op> : MIMGe_gfxpre11 { 378 bits<8> vaddr; 379 bits<1> da; 380 381 let Inst{0} = op{7}; 382 let Inst{7} = cpol{CPolBit.SCC}; 383 let Inst{14} = da; 384 let Inst{16} = vdata{9}; // ACC bit 385 let Inst{24-18} = op{6-0}; 386 let Inst{39-32} = vaddr; 387} 388 389class MIMGe_gfx10 <bits<8> op> : MIMGe_gfxpre11 { 390 bits<8> vaddr0; 391 bits<3> dim; 392 bits<2> nsa; 393 bits<1> a16; 394 395 let Inst{0} = op{7}; 396 let Inst{2-1} = nsa; 397 let Inst{5-3} = dim; 398 let Inst{7} = cpol{CPolBit.DLC}; 399 let Inst{16} = tfe; 400 let Inst{24-18} = op{6-0}; 401 let Inst{39-32} = vaddr0; 402 let Inst{62} = a16; 403} 404 405class MIMGe_gfx11 <bits<8> op> : Enc64 { 406 bits<8> vdata; 407 bits<4> dmask; 408 bits<1> unorm; 409 bits<5> cpol; 410 bits<1> r128; 411 bits<1> tfe; 412 bits<1> lwe; 413 bits<7> srsrc; 414 bits<7> ssamp; 415 bit d16; 416 bits<1> a16; 417 bits<8> vaddr0; 418 bits<3> dim; 419 bits<1> nsa; 420 421 let Inst{0} = nsa; 422 let Inst{4-2} = dim; 423 let Inst{7} = unorm; 424 let Inst{11-8} = dmask; 425 let Inst{12} = cpol{CPolBit.SLC}; 426 let Inst{13} = cpol{CPolBit.DLC}; 427 let Inst{14} = cpol{CPolBit.GLC}; 428 let Inst{15} = r128; 429 let Inst{16} = a16; 430 let Inst{17} = d16; 431 let Inst{25-18} = op; 432 let Inst{31-26} = 0x3c; 433 let Inst{39-32} = vaddr0; 434 let Inst{47-40} = vdata; 435 let Inst{52-48} = srsrc{6-2}; 436 let Inst{53} = tfe; 437 let Inst{54} = lwe; 438 let Inst{62-58} = ssamp{6-2}; 439} 440 441class VIMAGE_VSAMPLE_Common <bits<8> op> : Enc96 { 442 bits<3> dim; 443 bits<1> tfe; 444 bits<1> r128; 445 bit d16; 446 bits<1> a16; 447 bits<4> dmask; 448 bits<8> vdata; 449 bits<9> rsrc; 450 bits<6> cpol; 451 bits<8> vaddr0; 452 bits<8> vaddr1; 453 bits<8> vaddr2; 454 bits<8> vaddr3; 455 456 let Inst{2-0} = dim; 457 let Inst{4} = r128; 458 let Inst{5} = d16; 459 let Inst{6} = a16; 460 let Inst{21-14} = op; 461 let Inst{25-22} = dmask; 462 let Inst{39-32} = vdata; 463 let Inst{49-41} = rsrc; 464 let Inst{51-50} = cpol{4-3}; // scope 465 let Inst{54-52} = cpol{2-0}; // th 466 let Inst{71-64} = vaddr0; 467 let Inst{79-72} = vaddr1; 468 let Inst{87-80} = vaddr2; 469 let Inst{95-88} = vaddr3; 470} 471 472class VSAMPLEe <bits<8> op> : VIMAGE_VSAMPLE_Common<op> { 473 bits<1> unorm; 474 bits<1> lwe; 475 bits<9> samp; 476 477 let Inst{3} = tfe; 478 let Inst{13} = unorm; 479 let Inst{31-26} = 0x39; 480 let Inst{40} = lwe; 481 let Inst{63-55} = samp; 482} 483 484class VIMAGEe <bits<8> op> : VIMAGE_VSAMPLE_Common<op> { 485 bits<8> vaddr4; 486 487 let Inst{31-26} = 0x34; 488 let Inst{55} = tfe; 489 let Inst{63-56} = vaddr4; 490} 491 492class EXPe : Enc64 { 493 bits<4> en; 494 bits<6> tgt; 495 bits<1> done; 496 bits<8> src0; 497 bits<8> src1; 498 bits<8> src2; 499 bits<8> src3; 500 501 let Inst{3-0} = en; 502 let Inst{9-4} = tgt; 503 let Inst{11} = done; 504 let Inst{31-26} = 0x3e; 505 let Inst{39-32} = src0; 506 let Inst{47-40} = src1; 507 let Inst{55-48} = src2; 508 let Inst{63-56} = src3; 509} 510 511// Pre-GFX11 encoding has compr and vm bits. 512class EXPe_ComprVM : EXPe { 513 bits<1> compr; 514 bits<1> vm; 515 516 let Inst{10} = compr; 517 let Inst{12} = vm; 518} 519 520// GFX11+ encoding has row bit. 521class EXPe_Row : EXPe { 522 bits<1> row; 523 524 let Inst{13} = row; 525} 526 527let Uses = [EXEC] in { 528 529class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> : 530 InstSI <outs, ins, asm, pattern> { 531 let VINTRP = 1; 532 // VINTRP instructions read parameter values from LDS, but these parameter 533 // values are stored outside of the LDS memory that is allocated to the 534 // shader for general purpose use. 535 // 536 // While it may be possible for ds_read/ds_write instructions to access 537 // the parameter values in LDS, this would essentially be an out-of-bounds 538 // memory access which we consider to be undefined behavior. 539 // 540 // So even though these instructions read memory, this memory is outside the 541 // addressable memory space for the shader, and we consider these instructions 542 // to be readnone. 543 let mayLoad = 0; 544 let mayStore = 0; 545 let hasSideEffects = 0; 546 let VALU = 1; 547} 548 549} // End Uses = [EXEC] 550