1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// SI Instruction format definitions. 10// 11//===----------------------------------------------------------------------===// 12 13class InstSI <dag outs, dag ins, string asm = "", 14 list<dag> pattern = []> : 15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl { 16 // Low bits - basic encoding information. 17 field bit SALU = 0; 18 field bit VALU = 0; 19 20 // SALU instruction formats. 21 field bit SOP1 = 0; 22 field bit SOP2 = 0; 23 field bit SOPC = 0; 24 field bit SOPK = 0; 25 field bit SOPP = 0; 26 27 // VALU instruction formats. 28 field bit VOP1 = 0; 29 field bit VOP2 = 0; 30 field bit VOPC = 0; 31 field bit VOP3 = 0; 32 field bit VOP3P = 0; 33 field bit VINTRP = 0; 34 field bit SDWA = 0; 35 field bit DPP = 0; 36 field bit TRANS = 0; 37 38 // Memory instruction formats. 39 field bit MUBUF = 0; 40 field bit MTBUF = 0; 41 field bit SMRD = 0; 42 field bit MIMG = 0; 43 field bit VIMAGE = 0; 44 field bit VSAMPLE = 0; 45 field bit EXP = 0; 46 field bit FLAT = 0; 47 field bit DS = 0; 48 49 // Combined SGPR/VGPR spill bit 50 field bit Spill = 0; 51 52 // LDSDIR instruction format. 53 field bit LDSDIR = 0; 54 55 // VINTERP instruction format. 56 field bit VINTERP = 0; 57 58 // High bits - other information. 59 field bit VM_CNT = 0; 60 field bit EXP_CNT = 0; 61 field bit LGKM_CNT = 0; 62 63 // Whether WQM _must_ be enabled for this instruction. 64 field bit WQM = 0; 65 66 // Whether WQM _must_ be disabled for this instruction. 67 field bit DisableWQM = 0; 68 69 field bit Gather4 = 0; 70 71 // This is an s_store_dword* instruction that requires a cache flush 72 // on wave termination. It is necessary to distinguish from mayStore 73 // SMEM instructions like the cache flush ones. 74 field bit ScalarStore = 0; 75 76 // Whether the operands can be ignored when computing the 77 // instruction size. 78 field bit FixedSize = 0; 79 80 // This bit indicates that this is a VOP3 opcode which supports op_sel 81 // modifier. 82 field bit VOP3_OPSEL = 0; 83 84 // Is it possible for this instruction to be atomic? 85 field bit maybeAtomic = 1; 86 87 // This bit indicates that this is a VI instruction which is renamed 88 // in GFX9. Required for correct mapping from pseudo to MC. 89 field bit renamedInGFX9 = 0; 90 91 // This bit indicates that this has a floating point result type, so 92 // the clamp modifier has floating point semantics. 93 field bit FPClamp = 0; 94 95 // This bit indicates that instruction may support integer clamping 96 // which depends on GPU features. 97 field bit IntClamp = 0; 98 99 // This field indicates that the clamp applies to the low component 100 // of a packed output register. 101 field bit ClampLo = 0; 102 103 // This field indicates that the clamp applies to the high component 104 // of a packed output register. 105 field bit ClampHi = 0; 106 107 // This bit indicates that this is a packed VOP3P instruction 108 field bit IsPacked = 0; 109 110 // This bit indicates that this is a D16 buffer instruction. 111 field bit D16Buf = 0; 112 113 // This field indicates that FLAT instruction accesses FLAT_GLBL segment. 114 // Must be 0 for non-FLAT instructions. 115 field bit FlatGlobal = 0; 116 117 // Reads the mode register, usually for FP environment. 118 field bit ReadsModeReg = 0; 119 120 // This bit indicates that this uses the floating point double precision 121 // rounding mode flags 122 field bit FPDPRounding = 0; 123 124 // Instruction is FP atomic. 125 field bit FPAtomic = 0; 126 127 // This bit indicates that this is one of MFMA instructions. 128 field bit IsMAI = 0; 129 130 // This bit indicates that this is one of DOT instructions. 131 field bit IsDOT = 0; 132 133 // This field indicates that FLAT instruction accesses FLAT_SCRATCH segment. 134 // Must be 0 for non-FLAT instructions. 135 field bit FlatScratch = 0; 136 137 // Atomic without a return. 138 field bit IsAtomicNoRet = 0; 139 140 // Atomic with return. 141 field bit IsAtomicRet = 0; 142 143 // This bit indicates that this is one of WMMA instructions. 144 field bit IsWMMA = 0; 145 146 // This bit indicates that tied source will not be read. 147 field bit TiedSourceNotRead = 0; 148 149 // This bit indicates that the instruction is never-uniform/divergent 150 field bit IsNeverUniform = 0; 151 152 // ds_gws_* instructions. 153 field bit GWS = 0; 154 155 // This bit indicates that this is one of SWMMAC instructions. 156 field bit IsSWMMAC = 0; 157 158 // These need to be kept in sync with the enum in SIInstrFlags. 159 let TSFlags{0} = SALU; 160 let TSFlags{1} = VALU; 161 162 let TSFlags{2} = SOP1; 163 let TSFlags{3} = SOP2; 164 let TSFlags{4} = SOPC; 165 let TSFlags{5} = SOPK; 166 let TSFlags{6} = SOPP; 167 168 let TSFlags{7} = VOP1; 169 let TSFlags{8} = VOP2; 170 let TSFlags{9} = VOPC; 171 let TSFlags{10} = VOP3; 172 let TSFlags{12} = VOP3P; 173 174 let TSFlags{13} = VINTRP; 175 let TSFlags{14} = SDWA; 176 let TSFlags{15} = DPP; 177 let TSFlags{16} = TRANS; 178 179 let TSFlags{17} = MUBUF; 180 let TSFlags{18} = MTBUF; 181 let TSFlags{19} = SMRD; 182 let TSFlags{20} = MIMG; 183 let TSFlags{21} = VIMAGE; 184 let TSFlags{22} = VSAMPLE; 185 let TSFlags{23} = EXP; 186 let TSFlags{24} = FLAT; 187 let TSFlags{25} = DS; 188 189 let TSFlags{26} = Spill; 190 191 // Reserved, must be 0 192 let TSFlags{27} = 0; 193 194 let TSFlags{28} = LDSDIR; 195 let TSFlags{29} = VINTERP; 196 197 let TSFlags{32} = VM_CNT; 198 let TSFlags{33} = EXP_CNT; 199 let TSFlags{34} = LGKM_CNT; 200 201 let TSFlags{35} = WQM; 202 let TSFlags{36} = DisableWQM; 203 let TSFlags{37} = Gather4; 204 205 // Reserved, must be 0. 206 let TSFlags{38} = 0; 207 208 let TSFlags{39} = ScalarStore; 209 let TSFlags{40} = FixedSize; 210 211 // Reserved, must be 0. 212 let TSFlags{41} = 0; 213 214 let TSFlags{42} = VOP3_OPSEL; 215 216 let TSFlags{43} = maybeAtomic; 217 let TSFlags{44} = renamedInGFX9; 218 219 let TSFlags{45} = FPClamp; 220 let TSFlags{46} = IntClamp; 221 let TSFlags{47} = ClampLo; 222 let TSFlags{48} = ClampHi; 223 224 let TSFlags{49} = IsPacked; 225 226 let TSFlags{50} = D16Buf; 227 228 let TSFlags{51} = FlatGlobal; 229 230 let TSFlags{52} = FPDPRounding; 231 232 let TSFlags{53} = FPAtomic; 233 234 let TSFlags{54} = IsMAI; 235 236 let TSFlags{55} = IsDOT; 237 238 let TSFlags{56} = FlatScratch; 239 240 let TSFlags{57} = IsAtomicNoRet; 241 242 let TSFlags{58} = IsAtomicRet; 243 244 let TSFlags{59} = IsWMMA; 245 246 let TSFlags{60} = TiedSourceNotRead; 247 248 let TSFlags{61} = IsNeverUniform; 249 250 let TSFlags{62} = GWS; 251 252 let TSFlags{63} = IsSWMMAC; 253 254 let SchedRW = [Write32Bit]; 255 256 let AsmVariantName = AMDGPUAsmVariants.Default; 257 258 // Avoid changing source registers in a way that violates constant bus read limitations. 259 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU); 260} 261 262class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = ""> 263 : InstSI<outs, ins, asm, pattern> { 264 let isPseudo = 1; 265 let isCodeGenOnly = 1; 266} 267 268class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = ""> 269 : PseudoInstSI<outs, ins, pattern, asm> { 270 let SALU = 1; 271} 272 273class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = ""> 274 : PseudoInstSI<outs, ins, pattern, asm> { 275 let VALU = 1; 276 let Uses = [EXEC]; 277} 278 279class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], 280 bit UseExec = 0, bit DefExec = 0> : 281 SPseudoInstSI<outs, ins, pattern> { 282 283 let Uses = !if(UseExec, [EXEC], []); 284 let Defs = !if(DefExec, [EXEC, SCC], [SCC]); 285 let mayLoad = 0; 286 let mayStore = 0; 287 let hasSideEffects = 0; 288} 289 290class Enc32 { 291 field bits<32> Inst; 292 int Size = 4; 293} 294 295class Enc64 { 296 field bits<64> Inst; 297 int Size = 8; 298} 299 300class Enc96 { 301 field bits<96> Inst; 302 int Size = 12; 303} 304 305def CPolBit { 306 int GLC = 0; 307 int SLC = 1; 308 int DLC = 2; 309 int SCC = 4; 310} 311 312class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">; 313 314def VOPDstOperand_t16 : VOPDstOperand <VGPR_16> { 315 let EncoderMethod = "getMachineOpValueT16"; 316 let DecoderMethod = "DecodeVGPR_16RegisterClass"; 317} 318 319def VOPDstOperand_t16Lo128 : VOPDstOperand <VGPR_16_Lo128> { 320 let EncoderMethod = "getMachineOpValueT16Lo128"; 321 let DecoderMethod = "DecodeVGPR_16_Lo128RegisterClass"; 322} 323 324class VINTRPe <bits<2> op> : Enc32 { 325 bits<8> vdst; 326 bits<8> vsrc; 327 bits<2> attrchan; 328 bits<6> attr; 329 330 let Inst{7-0} = vsrc; 331 let Inst{9-8} = attrchan; 332 let Inst{15-10} = attr; 333 let Inst{17-16} = op; 334 let Inst{25-18} = vdst; 335 let Inst{31-26} = 0x32; // encoding 336} 337 338class MIMGe_gfxpre11 : Enc64 { 339 bits<10> vdata; 340 bits<4> dmask; 341 bits<1> unorm; 342 bits<5> cpol; 343 bits<1> r128; 344 bits<1> tfe; 345 bits<1> lwe; 346 bit d16; 347 bits<7> srsrc; 348 bits<7> ssamp; 349 350 let Inst{11-8} = dmask; 351 let Inst{12} = unorm; 352 let Inst{13} = cpol{CPolBit.GLC}; 353 let Inst{15} = r128; 354 let Inst{17} = lwe; 355 let Inst{25} = cpol{CPolBit.SLC}; 356 let Inst{31-26} = 0x3c; 357 let Inst{47-40} = vdata{7-0}; 358 let Inst{52-48} = srsrc{6-2}; 359 let Inst{57-53} = ssamp{6-2}; 360 let Inst{63} = d16; 361} 362 363class MIMGe_gfx6789 <bits<8> op> : MIMGe_gfxpre11 { 364 bits<8> vaddr; 365 bits<1> da; 366 367 let Inst{0} = op{7}; 368 let Inst{7} = cpol{CPolBit.SCC}; 369 let Inst{14} = da; 370 let Inst{16} = tfe; 371 let Inst{24-18} = op{6-0}; 372 let Inst{39-32} = vaddr; 373} 374 375class MIMGe_gfx90a <bits<8> op> : MIMGe_gfxpre11 { 376 bits<8> vaddr; 377 bits<1> da; 378 379 let Inst{0} = op{7}; 380 let Inst{7} = cpol{CPolBit.SCC}; 381 let Inst{14} = da; 382 let Inst{16} = vdata{9}; // ACC bit 383 let Inst{24-18} = op{6-0}; 384 let Inst{39-32} = vaddr; 385} 386 387class MIMGe_gfx10 <bits<8> op> : MIMGe_gfxpre11 { 388 bits<8> vaddr0; 389 bits<3> dim; 390 bits<2> nsa; 391 bits<1> a16; 392 393 let Inst{0} = op{7}; 394 let Inst{2-1} = nsa; 395 let Inst{5-3} = dim; 396 let Inst{7} = cpol{CPolBit.DLC}; 397 let Inst{16} = tfe; 398 let Inst{24-18} = op{6-0}; 399 let Inst{39-32} = vaddr0; 400 let Inst{62} = a16; 401} 402 403class MIMGe_gfx11 <bits<8> op> : Enc64 { 404 bits<8> vdata; 405 bits<4> dmask; 406 bits<1> unorm; 407 bits<5> cpol; 408 bits<1> r128; 409 bits<1> tfe; 410 bits<1> lwe; 411 bits<7> srsrc; 412 bits<7> ssamp; 413 bit d16; 414 bits<1> a16; 415 bits<8> vaddr0; 416 bits<3> dim; 417 bits<1> nsa; 418 419 let Inst{0} = nsa; 420 let Inst{4-2} = dim; 421 let Inst{7} = unorm; 422 let Inst{11-8} = dmask; 423 let Inst{12} = cpol{CPolBit.SLC}; 424 let Inst{13} = cpol{CPolBit.DLC}; 425 let Inst{14} = cpol{CPolBit.GLC}; 426 let Inst{15} = r128; 427 let Inst{16} = a16; 428 let Inst{17} = d16; 429 let Inst{25-18} = op; 430 let Inst{31-26} = 0x3c; 431 let Inst{39-32} = vaddr0; 432 let Inst{47-40} = vdata; 433 let Inst{52-48} = srsrc{6-2}; 434 let Inst{53} = tfe; 435 let Inst{54} = lwe; 436 let Inst{62-58} = ssamp{6-2}; 437} 438 439class VIMAGE_VSAMPLE_Common <bits<8> op> : Enc96 { 440 bits<3> dim; 441 bits<1> tfe; 442 bits<1> r128; 443 bit d16; 444 bits<1> a16; 445 bits<4> dmask; 446 bits<8> vdata; 447 bits<9> rsrc; 448 bits<6> cpol; 449 bits<8> vaddr0; 450 bits<8> vaddr1; 451 bits<8> vaddr2; 452 bits<8> vaddr3; 453 454 let Inst{2-0} = dim; 455 let Inst{4} = r128; 456 let Inst{5} = d16; 457 let Inst{6} = a16; 458 let Inst{21-14} = op; 459 let Inst{25-22} = dmask; 460 let Inst{39-32} = vdata; 461 let Inst{49-41} = rsrc; 462 let Inst{51-50} = cpol{4-3}; // scope 463 let Inst{54-52} = cpol{2-0}; // th 464 let Inst{71-64} = vaddr0; 465 let Inst{79-72} = vaddr1; 466 let Inst{87-80} = vaddr2; 467 let Inst{95-88} = vaddr3; 468} 469 470class VSAMPLEe <bits<8> op> : VIMAGE_VSAMPLE_Common<op> { 471 bits<1> unorm; 472 bits<1> lwe; 473 bits<9> samp; 474 475 let Inst{3} = tfe; 476 let Inst{13} = unorm; 477 let Inst{31-26} = 0x39; 478 let Inst{40} = lwe; 479 let Inst{63-55} = samp; 480} 481 482class VIMAGEe <bits<8> op> : VIMAGE_VSAMPLE_Common<op> { 483 bits<8> vaddr4; 484 485 let Inst{31-26} = 0x34; 486 let Inst{55} = tfe; 487 let Inst{63-56} = vaddr4; 488} 489 490class EXPe : Enc64 { 491 bits<4> en; 492 bits<6> tgt; 493 bits<1> done; 494 bits<8> src0; 495 bits<8> src1; 496 bits<8> src2; 497 bits<8> src3; 498 499 let Inst{3-0} = en; 500 let Inst{9-4} = tgt; 501 let Inst{11} = done; 502 let Inst{31-26} = 0x3e; 503 let Inst{39-32} = src0; 504 let Inst{47-40} = src1; 505 let Inst{55-48} = src2; 506 let Inst{63-56} = src3; 507} 508 509// Pre-GFX11 encoding has compr and vm bits. 510class EXPe_ComprVM : EXPe { 511 bits<1> compr; 512 bits<1> vm; 513 514 let Inst{10} = compr; 515 let Inst{12} = vm; 516} 517 518// GFX11+ encoding has row bit. 519class EXPe_Row : EXPe { 520 bits<1> row; 521 522 let Inst{13} = row; 523} 524 525let Uses = [EXEC] in { 526 527class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> : 528 InstSI <outs, ins, asm, pattern> { 529 let VINTRP = 1; 530 // VINTRP instructions read parameter values from LDS, but these parameter 531 // values are stored outside of the LDS memory that is allocated to the 532 // shader for general purpose use. 533 // 534 // While it may be possible for ds_read/ds_write instructions to access 535 // the parameter values in LDS, this would essentially be an out-of-bounds 536 // memory access which we consider to be undefined behavior. 537 // 538 // So even though these instructions read memory, this memory is outside the 539 // addressable memory space for the shader, and we consider these instructions 540 // to be readnone. 541 let mayLoad = 0; 542 let mayStore = 0; 543 let hasSideEffects = 0; 544 let VALU = 1; 545} 546 547} // End Uses = [EXEC] 548