1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// SI Instruction format definitions. 10// 11//===----------------------------------------------------------------------===// 12 13class InstSI <dag outs, dag ins, string asm = "", 14 list<dag> pattern = []> : 15 AMDGPUInst<outs, ins, asm, pattern>, GCNPredicateControl { 16 // Low bits - basic encoding information. 17 field bit SALU = 0; 18 field bit VALU = 0; 19 20 // SALU instruction formats. 21 field bit SOP1 = 0; 22 field bit SOP2 = 0; 23 field bit SOPC = 0; 24 field bit SOPK = 0; 25 field bit SOPP = 0; 26 27 // VALU instruction formats. 28 field bit VOP1 = 0; 29 field bit VOP2 = 0; 30 field bit VOPC = 0; 31 field bit VOP3 = 0; 32 field bit VOP3P = 0; 33 field bit VINTRP = 0; 34 field bit SDWA = 0; 35 field bit DPP = 0; 36 37 // Memory instruction formats. 38 field bit MUBUF = 0; 39 field bit MTBUF = 0; 40 field bit SMRD = 0; 41 field bit MIMG = 0; 42 field bit EXP = 0; 43 field bit FLAT = 0; 44 field bit DS = 0; 45 46 // Pseudo instruction formats. 47 field bit VGPRSpill = 0; 48 field bit SGPRSpill = 0; 49 50 // High bits - other information. 51 field bit VM_CNT = 0; 52 field bit EXP_CNT = 0; 53 field bit LGKM_CNT = 0; 54 55 // Whether WQM _must_ be enabled for this instruction. 56 field bit WQM = 0; 57 58 // Whether WQM _must_ be disabled for this instruction. 59 field bit DisableWQM = 0; 60 61 field bit Gather4 = 0; 62 63 // Most sopk treat the immediate as a signed 16-bit, however some 64 // use it as unsigned. 65 field bit SOPKZext = 0; 66 67 // This is an s_store_dword* instruction that requires a cache flush 68 // on wave termination. It is necessary to distinguish from mayStore 69 // SMEM instructions like the cache flush ones. 70 field bit ScalarStore = 0; 71 72 // Whether the operands can be ignored when computing the 73 // instruction size. 74 field bit FixedSize = 0; 75 76 // This bit tells the assembler to use the 32-bit encoding in case it 77 // is unable to infer the encoding from the operands. 78 field bit VOPAsmPrefer32Bit = 0; 79 80 // This bit indicates that this is a VOP3 opcode which supports op_sel 81 // modifier (gfx9 only). 82 field bit VOP3_OPSEL = 0; 83 84 // Is it possible for this instruction to be atomic? 85 field bit maybeAtomic = 0; 86 87 // This bit indicates that this is a VI instruction which is renamed 88 // in GFX9. Required for correct mapping from pseudo to MC. 89 field bit renamedInGFX9 = 0; 90 91 // This bit indicates that this has a floating point result type, so 92 // the clamp modifier has floating point semantics. 93 field bit FPClamp = 0; 94 95 // This bit indicates that instruction may support integer clamping 96 // which depends on GPU features. 97 field bit IntClamp = 0; 98 99 // This field indicates that the clamp applies to the low component 100 // of a packed output register. 101 field bit ClampLo = 0; 102 103 // This field indicates that the clamp applies to the high component 104 // of a packed output register. 105 field bit ClampHi = 0; 106 107 // This bit indicates that this is a packed VOP3P instruction 108 field bit IsPacked = 0; 109 110 // This bit indicates that this is a D16 buffer instruction. 111 field bit D16Buf = 0; 112 113 // This field indicates that FLAT instruction accesses FLAT_GLBL or 114 // FLAT_SCRATCH segment. Must be 0 for non-FLAT instructions. 115 field bit IsNonFlatSeg = 0; 116 117 // This bit indicates that this uses the floating point double precision 118 // rounding mode flags 119 field bit FPDPRounding = 0; 120 121 // Instruction is FP atomic. 122 field bit FPAtomic = 0; 123 124 // This bit indicates that this is one of MFMA instructions. 125 field bit IsMAI = 0; 126 127 // These need to be kept in sync with the enum in SIInstrFlags. 128 let TSFlags{0} = SALU; 129 let TSFlags{1} = VALU; 130 131 let TSFlags{2} = SOP1; 132 let TSFlags{3} = SOP2; 133 let TSFlags{4} = SOPC; 134 let TSFlags{5} = SOPK; 135 let TSFlags{6} = SOPP; 136 137 let TSFlags{7} = VOP1; 138 let TSFlags{8} = VOP2; 139 let TSFlags{9} = VOPC; 140 let TSFlags{10} = VOP3; 141 let TSFlags{12} = VOP3P; 142 143 let TSFlags{13} = VINTRP; 144 let TSFlags{14} = SDWA; 145 let TSFlags{15} = DPP; 146 147 let TSFlags{16} = MUBUF; 148 let TSFlags{17} = MTBUF; 149 let TSFlags{18} = SMRD; 150 let TSFlags{19} = MIMG; 151 let TSFlags{20} = EXP; 152 let TSFlags{21} = FLAT; 153 let TSFlags{22} = DS; 154 155 let TSFlags{23} = VGPRSpill; 156 let TSFlags{24} = SGPRSpill; 157 158 let TSFlags{32} = VM_CNT; 159 let TSFlags{33} = EXP_CNT; 160 let TSFlags{34} = LGKM_CNT; 161 162 let TSFlags{35} = WQM; 163 let TSFlags{36} = DisableWQM; 164 let TSFlags{37} = Gather4; 165 166 let TSFlags{38} = SOPKZext; 167 let TSFlags{39} = ScalarStore; 168 let TSFlags{40} = FixedSize; 169 let TSFlags{41} = VOPAsmPrefer32Bit; 170 let TSFlags{42} = VOP3_OPSEL; 171 172 let TSFlags{43} = maybeAtomic; 173 let TSFlags{44} = renamedInGFX9; 174 175 let TSFlags{45} = FPClamp; 176 let TSFlags{46} = IntClamp; 177 let TSFlags{47} = ClampLo; 178 let TSFlags{48} = ClampHi; 179 180 let TSFlags{49} = IsPacked; 181 182 let TSFlags{50} = D16Buf; 183 184 let TSFlags{51} = IsNonFlatSeg; 185 186 let TSFlags{52} = FPDPRounding; 187 188 let TSFlags{53} = FPAtomic; 189 190 let TSFlags{54} = IsMAI; 191 192 let SchedRW = [Write32Bit]; 193 194 field bits<1> DisableSIDecoder = 0; 195 field bits<1> DisableVIDecoder = 0; 196 field bits<1> DisableDecoder = 0; 197 198 let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1); 199 let AsmVariantName = AMDGPUAsmVariants.Default; 200 201 // Avoid changing source registers in a way that violates constant bus read limitations. 202 let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)))))); 203} 204 205class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = ""> 206 : InstSI<outs, ins, asm, pattern> { 207 let isPseudo = 1; 208 let isCodeGenOnly = 1; 209} 210 211class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = ""> 212 : PseudoInstSI<outs, ins, pattern, asm> { 213 let SALU = 1; 214} 215 216class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = ""> 217 : PseudoInstSI<outs, ins, pattern, asm> { 218 let VALU = 1; 219 let Uses = [EXEC]; 220} 221 222class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], 223 bit UseExec = 0, bit DefExec = 0> : 224 SPseudoInstSI<outs, ins, pattern> { 225 226 let Uses = !if(UseExec, [EXEC], []); 227 let Defs = !if(DefExec, [EXEC, SCC], [SCC]); 228 let mayLoad = 0; 229 let mayStore = 0; 230 let hasSideEffects = 0; 231} 232 233class Enc32 { 234 field bits<32> Inst; 235 int Size = 4; 236} 237 238class Enc64 { 239 field bits<64> Inst; 240 int Size = 8; 241} 242 243class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">; 244 245class VINTRPe <bits<2> op> : Enc32 { 246 bits<8> vdst; 247 bits<8> vsrc; 248 bits<2> attrchan; 249 bits<6> attr; 250 251 let Inst{7-0} = vsrc; 252 let Inst{9-8} = attrchan; 253 let Inst{15-10} = attr; 254 let Inst{17-16} = op; 255 let Inst{25-18} = vdst; 256 let Inst{31-26} = 0x32; // encoding 257} 258 259class MIMGe : Enc64 { 260 bits<8> vdata; 261 bits<4> dmask; 262 bits<1> unorm; 263 bits<1> glc; 264 bits<1> r128; 265 bits<1> tfe; 266 bits<1> lwe; 267 bits<1> slc; 268 bit d16; 269 bits<7> srsrc; 270 bits<7> ssamp; 271 272 let Inst{11-8} = dmask; 273 let Inst{12} = unorm; 274 let Inst{13} = glc; 275 let Inst{15} = r128; 276 let Inst{16} = tfe; 277 let Inst{17} = lwe; 278 let Inst{25} = slc; 279 let Inst{31-26} = 0x3c; 280 let Inst{47-40} = vdata; 281 let Inst{52-48} = srsrc{6-2}; 282 let Inst{57-53} = ssamp{6-2}; 283 let Inst{63} = d16; 284} 285 286class MIMGe_gfx6789 <bits<8> op> : MIMGe { 287 bits<8> vaddr; 288 bits<1> da; 289 290 let Inst{0} = op{7}; 291 let Inst{14} = da; 292 let Inst{24-18} = op{6-0}; 293 let Inst{39-32} = vaddr; 294} 295 296class MIMGe_gfx10 <bits<8> op> : MIMGe { 297 bits<8> vaddr0; 298 bits<3> dim; 299 bits<2> nsa; 300 bits<1> dlc; 301 bits<1> a16 = 0; // TODO: this should be an operand 302 303 let Inst{0} = op{7}; 304 let Inst{2-1} = nsa; 305 let Inst{5-3} = dim; 306 let Inst{7} = dlc; 307 let Inst{24-18} = op{6-0}; 308 let Inst{39-32} = vaddr0; 309 let Inst{62} = a16; 310} 311 312class EXPe : Enc64 { 313 bits<4> en; 314 bits<6> tgt; 315 bits<1> compr; 316 bits<1> done; 317 bits<1> vm; 318 bits<8> src0; 319 bits<8> src1; 320 bits<8> src2; 321 bits<8> src3; 322 323 let Inst{3-0} = en; 324 let Inst{9-4} = tgt; 325 let Inst{10} = compr; 326 let Inst{11} = done; 327 let Inst{12} = vm; 328 let Inst{31-26} = 0x3e; 329 let Inst{39-32} = src0; 330 let Inst{47-40} = src1; 331 let Inst{55-48} = src2; 332 let Inst{63-56} = src3; 333} 334 335let Uses = [EXEC] in { 336 337class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> : 338 InstSI <outs, ins, asm, pattern> { 339 let VINTRP = 1; 340 // VINTRP instructions read parameter values from LDS, but these parameter 341 // values are stored outside of the LDS memory that is allocated to the 342 // shader for general purpose use. 343 // 344 // While it may be possible for ds_read/ds_write instructions to access 345 // the parameter values in LDS, this would essentially be an out-of-bounds 346 // memory access which we consider to be undefined behavior. 347 // 348 // So even though these instructions read memory, this memory is outside the 349 // addressable memory space for the shader, and we consider these instructions 350 // to be readnone. 351 let mayLoad = 0; 352 let mayStore = 0; 353 let hasSideEffects = 0; 354 let VALU = 1; 355} 356 357class EXPCommon<dag outs, dag ins, string asm, list<dag> pattern> : 358 InstSI<outs, ins, asm, pattern> { 359 let EXP = 1; 360 let EXP_CNT = 1; 361 let mayLoad = 0; // Set to 1 if done bit is set. 362 let mayStore = 1; 363 let UseNamedOperandTable = 1; 364 let Uses = [EXEC]; 365 let SchedRW = [WriteExport]; 366} 367 368} // End Uses = [EXEC] 369