1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// SI DAG Lowering interface definition 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16 17 #include "AMDGPUISelLowering.h" 18 #include "AMDGPUArgumentUsageInfo.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 21 namespace llvm { 22 23 class GCNSubtarget; 24 class SIMachineFunctionInfo; 25 class SIRegisterInfo; 26 27 namespace AMDGPU { 28 struct ImageDimIntrinsicInfo; 29 } 30 31 class SITargetLowering final : public AMDGPUTargetLowering { 32 private: 33 const GCNSubtarget *Subtarget; 34 35 public: 36 MVT getRegisterTypeForCallingConv(LLVMContext &Context, 37 CallingConv::ID CC, 38 EVT VT) const override; 39 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 40 CallingConv::ID CC, 41 EVT VT) const override; 42 43 unsigned getVectorTypeBreakdownForCallingConv( 44 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 45 unsigned &NumIntermediates, MVT &RegisterVT) const override; 46 47 private: 48 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL, 49 SDValue Chain, uint64_t Offset) const; 50 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const; 51 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, 52 const SDLoc &SL, SDValue Chain, 53 uint64_t Offset, Align Alignment, 54 bool Signed, 55 const ISD::InputArg *Arg = nullptr) const; 56 57 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, 58 const SDLoc &SL, SDValue Chain, 59 const ISD::InputArg &Arg) const; 60 SDValue getPreloadedValue(SelectionDAG &DAG, 61 const SIMachineFunctionInfo &MFI, 62 EVT VT, 63 AMDGPUFunctionArgInfo::PreloadedValue) const; 64 65 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 66 SelectionDAG &DAG) const override; 67 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 68 MVT VT, unsigned Offset) const; 69 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr, 70 SelectionDAG &DAG, bool WithChain) const; 71 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset, 72 SDValue CachePolicy, SelectionDAG &DAG) const; 73 74 SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 75 unsigned NewOpcode) const; 76 SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 77 unsigned NewOpcode) const; 78 79 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 80 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 81 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 82 83 // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset 84 // (the offset that is included in bounds checking and swizzling, to be split 85 // between the instruction's voffset and immoffset fields) and soffset (the 86 // offset that is excluded from bounds checking and swizzling, to go in the 87 // instruction's soffset field). This function takes the first kind of 88 // offset and figures out how to split it between voffset and immoffset. 89 std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset, 90 SelectionDAG &DAG) const; 91 92 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const; 93 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 94 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 95 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; 96 SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const; 97 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const; 98 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const; 99 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 100 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 101 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 102 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 103 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 104 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 105 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 106 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 107 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, 108 SelectionDAG &DAG, ArrayRef<SDValue> Ops, 109 bool IsIntrinsic = false) const; 110 111 SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG, 112 ArrayRef<SDValue> Ops) const; 113 114 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to 115 // dwordx4 if on SI. 116 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, 117 ArrayRef<SDValue> Ops, EVT MemVT, 118 MachineMemOperand *MMO, SelectionDAG &DAG) const; 119 120 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG, 121 bool ImageStore = false) const; 122 123 /// Converts \p Op, which must be of floating point type, to the 124 /// floating point type \p VT, by either extending or truncating it. 125 SDValue getFPExtOrFPRound(SelectionDAG &DAG, 126 SDValue Op, 127 const SDLoc &DL, 128 EVT VT) const; 129 130 SDValue convertArgType( 131 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, 132 bool Signed, const ISD::InputArg *Arg = nullptr) const; 133 134 /// Custom lowering for ISD::FP_ROUND for MVT::f16. 135 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 136 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const; 137 SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const; 138 SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 139 140 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL, 141 SelectionDAG &DAG) const; 142 143 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 144 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 145 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 146 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 147 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 148 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 149 150 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 151 SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const; 152 SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const; 153 SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const; 154 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const; 155 156 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 157 158 SDValue performUCharToFloatCombine(SDNode *N, 159 DAGCombinerInfo &DCI) const; 160 SDValue performSHLPtrCombine(SDNode *N, 161 unsigned AS, 162 EVT MemVT, 163 DAGCombinerInfo &DCI) const; 164 165 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const; 166 167 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL, 168 unsigned Opc, SDValue LHS, 169 const ConstantSDNode *CRHS) const; 170 171 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 172 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 173 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 174 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const; 175 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const; 176 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 177 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT, 178 const APFloat &C) const; 179 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 180 181 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 182 SDValue Op0, SDValue Op1) const; 183 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 184 SDValue Op0, SDValue Op1, bool Signed) const; 185 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 186 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const; 187 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const; 188 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 189 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 190 191 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const; 192 unsigned getFusedOpcode(const SelectionDAG &DAG, 193 const SDNode *N0, const SDNode *N1) const; 194 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 195 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const; 196 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 197 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 198 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 199 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const; 200 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 201 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; 202 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const; 203 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const; 204 205 bool isLegalFlatAddressingMode(const AddrMode &AM) const; 206 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 207 208 unsigned isCFIntrinsic(const SDNode *Intr) const; 209 210 public: 211 /// \returns True if fixup needs to be emitted for given global value \p GV, 212 /// false otherwise. 213 bool shouldEmitFixup(const GlobalValue *GV) const; 214 215 /// \returns True if GOT relocation needs to be emitted for given global value 216 /// \p GV, false otherwise. 217 bool shouldEmitGOTReloc(const GlobalValue *GV) const; 218 219 /// \returns True if PC-relative relocation needs to be emitted for given 220 /// global value \p GV, false otherwise. 221 bool shouldEmitPCReloc(const GlobalValue *GV) const; 222 223 /// \returns true if this should use a literal constant for an LDS address, 224 /// and not emit a relocation for an LDS global. 225 bool shouldUseLDSConstAddress(const GlobalValue *GV) const; 226 227 /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be 228 /// expanded into a set of cmp/select instructions. 229 static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, 230 bool IsDivergentIdx); 231 232 private: 233 // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the 234 // three offsets (voffset, soffset and instoffset) into the SDValue[3] array 235 // pointed to by Offsets. 236 void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG, 237 SDValue *Offsets, Align Alignment = Align(4)) const; 238 239 // Handle 8 bit and 16 bit buffer loads 240 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL, 241 ArrayRef<SDValue> Ops, MemSDNode *M) const; 242 243 // Handle 8 bit and 16 bit buffer stores 244 SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType, 245 SDLoc DL, SDValue Ops[], 246 MemSDNode *M) const; 247 248 public: 249 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI); 250 251 const GCNSubtarget *getSubtarget() const; 252 253 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, 254 EVT SrcVT) const override; 255 256 bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy, 257 LLT SrcTy) const override; 258 259 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override; 260 261 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 262 MachineFunction &MF, 263 unsigned IntrinsicID) const override; 264 265 bool getAddrModeArguments(IntrinsicInst * /*I*/, 266 SmallVectorImpl<Value*> &/*Ops*/, 267 Type *&/*AccessTy*/) const override; 268 269 bool isLegalGlobalAddressingMode(const AddrMode &AM) const; 270 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 271 unsigned AS, 272 Instruction *I = nullptr) const override; 273 274 bool canMergeStoresTo(unsigned AS, EVT MemVT, 275 const MachineFunction &MF) const override; 276 277 bool allowsMisalignedMemoryAccessesImpl( 278 unsigned Size, unsigned AddrSpace, Align Alignment, 279 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 280 bool *IsFast = nullptr) const; 281 282 bool allowsMisalignedMemoryAccesses( 283 LLT Ty, unsigned AddrSpace, Align Alignment, 284 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 285 bool *IsFast = nullptr) const override { 286 if (IsFast) 287 *IsFast = false; 288 return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace, 289 Alignment, Flags, IsFast); 290 } 291 292 bool allowsMisalignedMemoryAccesses( 293 EVT VT, unsigned AS, Align Alignment, 294 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 295 bool *IsFast = nullptr) const override; 296 297 EVT getOptimalMemOpType(const MemOp &Op, 298 const AttributeList &FuncAttributes) const override; 299 300 bool isMemOpUniform(const SDNode *N) const; 301 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; 302 303 static bool isNonGlobalAddrSpace(unsigned AS); 304 305 bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 306 307 TargetLoweringBase::LegalizeTypeAction 308 getPreferredVectorAction(MVT VT) const override; 309 310 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 311 Type *Ty) const override; 312 313 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 314 315 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 316 317 bool supportSplitCSR(MachineFunction *MF) const override; 318 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 319 void insertCopiesSplitCSR( 320 MachineBasicBlock *Entry, 321 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 322 323 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 324 bool isVarArg, 325 const SmallVectorImpl<ISD::InputArg> &Ins, 326 const SDLoc &DL, SelectionDAG &DAG, 327 SmallVectorImpl<SDValue> &InVals) const override; 328 329 bool CanLowerReturn(CallingConv::ID CallConv, 330 MachineFunction &MF, bool isVarArg, 331 const SmallVectorImpl<ISD::OutputArg> &Outs, 332 LLVMContext &Context) const override; 333 334 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 335 const SmallVectorImpl<ISD::OutputArg> &Outs, 336 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 337 SelectionDAG &DAG) const override; 338 339 void passSpecialInputs( 340 CallLoweringInfo &CLI, 341 CCState &CCInfo, 342 const SIMachineFunctionInfo &Info, 343 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, 344 SmallVectorImpl<SDValue> &MemOpChains, 345 SDValue Chain) const; 346 347 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 348 CallingConv::ID CallConv, bool isVarArg, 349 const SmallVectorImpl<ISD::InputArg> &Ins, 350 const SDLoc &DL, SelectionDAG &DAG, 351 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 352 SDValue ThisVal) const; 353 354 bool mayBeEmittedAsTailCall(const CallInst *) const override; 355 356 bool isEligibleForTailCallOptimization( 357 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 358 const SmallVectorImpl<ISD::OutputArg> &Outs, 359 const SmallVectorImpl<SDValue> &OutVals, 360 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 361 362 SDValue LowerCall(CallLoweringInfo &CLI, 363 SmallVectorImpl<SDValue> &InVals) const override; 364 365 SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const; 366 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 367 368 Register getRegisterByName(const char* RegName, LLT VT, 369 const MachineFunction &MF) const override; 370 371 MachineBasicBlock *splitKillBlock(MachineInstr &MI, 372 MachineBasicBlock *BB) const; 373 374 void bundleInstWithWaitcnt(MachineInstr &MI) const; 375 MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI, 376 MachineBasicBlock *BB) const; 377 378 MachineBasicBlock * 379 EmitInstrWithCustomInserter(MachineInstr &MI, 380 MachineBasicBlock *BB) const override; 381 382 bool hasBitPreservingFPLogic(EVT VT) const override; 383 bool enableAggressiveFMAFusion(EVT VT) const override; 384 bool enableAggressiveFMAFusion(LLT Ty) const override; 385 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 386 EVT VT) const override; 387 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 388 LLT getPreferredShiftAmountTy(LLT Ty) const override; 389 390 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 391 EVT VT) const override; 392 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 393 const LLT Ty) const override; 394 bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override; 395 bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override; 396 397 SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 398 SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 399 SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 400 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 401 402 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 403 SelectionDAG &DAG) const override; 404 405 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 406 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 407 void AddIMGInit(MachineInstr &MI) const; 408 void AdjustInstrPostInstrSelection(MachineInstr &MI, 409 SDNode *Node) const override; 410 411 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 412 413 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 414 SDValue Ptr) const; 415 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 416 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 417 std::pair<unsigned, const TargetRegisterClass *> 418 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 419 StringRef Constraint, MVT VT) const override; 420 ConstraintType getConstraintType(StringRef Constraint) const override; 421 void LowerAsmOperandForConstraint(SDValue Op, 422 std::string &Constraint, 423 std::vector<SDValue> &Ops, 424 SelectionDAG &DAG) const override; 425 bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const; 426 bool checkAsmConstraintVal(SDValue Op, 427 const std::string &Constraint, 428 uint64_t Val) const; 429 bool checkAsmConstraintValA(SDValue Op, 430 uint64_t Val, 431 unsigned MaxSize = 64) const; 432 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 433 SDValue V) const; 434 435 void finalizeLowering(MachineFunction &MF) const override; 436 437 void computeKnownBitsForFrameIndex(int FrameIdx, 438 KnownBits &Known, 439 const MachineFunction &MF) const override; 440 void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, 441 KnownBits &Known, 442 const APInt &DemandedElts, 443 const MachineRegisterInfo &MRI, 444 unsigned Depth = 0) const override; 445 446 Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, 447 const MachineRegisterInfo &MRI, 448 unsigned Depth = 0) const override; 449 bool isSDNodeSourceOfDivergence(const SDNode *N, 450 FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override; 451 452 bool hasMemSDNodeUser(SDNode *N) const; 453 454 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, 455 SDValue N1) const override; 456 457 bool isCanonicalized(SelectionDAG &DAG, SDValue Op, 458 unsigned MaxDepth = 5) const; 459 bool isCanonicalized(Register Reg, MachineFunction &MF, 460 unsigned MaxDepth = 5) const; 461 bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const; 462 bool denormalsEnabledForType(LLT Ty, MachineFunction &MF) const; 463 464 bool isKnownNeverNaNForTargetNode(SDValue Op, 465 const SelectionDAG &DAG, 466 bool SNaN = false, 467 unsigned Depth = 0) const override; 468 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override; 469 470 virtual const TargetRegisterClass * 471 getRegClassFor(MVT VT, bool isDivergent) const override; 472 virtual bool requiresUniformRegister(MachineFunction &MF, 473 const Value *V) const override; 474 Align getPrefLoopAlignment(MachineLoop *ML) const override; 475 476 void allocateHSAUserSGPRs(CCState &CCInfo, 477 MachineFunction &MF, 478 const SIRegisterInfo &TRI, 479 SIMachineFunctionInfo &Info) const; 480 481 void allocateSystemSGPRs(CCState &CCInfo, 482 MachineFunction &MF, 483 SIMachineFunctionInfo &Info, 484 CallingConv::ID CallConv, 485 bool IsShader) const; 486 487 void allocateSpecialEntryInputVGPRs(CCState &CCInfo, 488 MachineFunction &MF, 489 const SIRegisterInfo &TRI, 490 SIMachineFunctionInfo &Info) const; 491 void allocateSpecialInputSGPRs( 492 CCState &CCInfo, 493 MachineFunction &MF, 494 const SIRegisterInfo &TRI, 495 SIMachineFunctionInfo &Info) const; 496 497 void allocateSpecialInputVGPRs(CCState &CCInfo, 498 MachineFunction &MF, 499 const SIRegisterInfo &TRI, 500 SIMachineFunctionInfo &Info) const; 501 void allocateSpecialInputVGPRsFixed(CCState &CCInfo, 502 MachineFunction &MF, 503 const SIRegisterInfo &TRI, 504 SIMachineFunctionInfo &Info) const; 505 506 std::pair<InstructionCost, MVT> getTypeLegalizationCost(const DataLayout &DL, 507 Type *Ty) const; 508 }; 509 510 } // End namespace llvm 511 512 #endif 513