1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// SI DAG Lowering interface definition 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16 17 #include "AMDGPUISelLowering.h" 18 #include "AMDGPUArgumentUsageInfo.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 21 namespace llvm { 22 23 class GCNSubtarget; 24 class SIMachineFunctionInfo; 25 class SIRegisterInfo; 26 27 namespace AMDGPU { 28 struct ImageDimIntrinsicInfo; 29 } 30 31 class SITargetLowering final : public AMDGPUTargetLowering { 32 private: 33 const GCNSubtarget *Subtarget; 34 35 public: 36 MVT getRegisterTypeForCallingConv(LLVMContext &Context, 37 CallingConv::ID CC, 38 EVT VT) const override; 39 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 40 CallingConv::ID CC, 41 EVT VT) const override; 42 43 unsigned getVectorTypeBreakdownForCallingConv( 44 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 45 unsigned &NumIntermediates, MVT &RegisterVT) const override; 46 47 private: 48 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL, 49 SDValue Chain, uint64_t Offset) const; 50 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const; 51 SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const; 52 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, 53 const SDLoc &SL, SDValue Chain, 54 uint64_t Offset, Align Alignment, 55 bool Signed, 56 const ISD::InputArg *Arg = nullptr) const; 57 SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL, 58 Align Alignment, 59 ImplicitParameter Param) const; 60 61 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, 62 const SDLoc &SL, SDValue Chain, 63 const ISD::InputArg &Arg) const; 64 SDValue getPreloadedValue(SelectionDAG &DAG, 65 const SIMachineFunctionInfo &MFI, 66 EVT VT, 67 AMDGPUFunctionArgInfo::PreloadedValue) const; 68 69 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 70 SelectionDAG &DAG) const override; 71 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 72 MVT VT, unsigned Offset) const; 73 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr, 74 SelectionDAG &DAG, bool WithChain) const; 75 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset, 76 SDValue CachePolicy, SelectionDAG &DAG) const; 77 78 SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 79 unsigned NewOpcode) const; 80 SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 81 unsigned NewOpcode) const; 82 83 SDValue lowerWorkitemID(SelectionDAG &DAG, SDValue Op, unsigned Dim, 84 const ArgDescriptor &ArgDesc) const; 85 86 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 87 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 88 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 89 90 // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset 91 // (the offset that is included in bounds checking and swizzling, to be split 92 // between the instruction's voffset and immoffset fields) and soffset (the 93 // offset that is excluded from bounds checking and swizzling, to go in the 94 // instruction's soffset field). This function takes the first kind of 95 // offset and figures out how to split it between voffset and immoffset. 96 std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset, 97 SelectionDAG &DAG) const; 98 99 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const; 100 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 101 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 102 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; 103 SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const; 104 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const; 105 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const; 106 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 107 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 108 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 109 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 110 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 111 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 112 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 113 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 114 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, 115 SelectionDAG &DAG, ArrayRef<SDValue> Ops, 116 bool IsIntrinsic = false) const; 117 118 SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG, 119 ArrayRef<SDValue> Ops) const; 120 121 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to 122 // dwordx4 if on SI. 123 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, 124 ArrayRef<SDValue> Ops, EVT MemVT, 125 MachineMemOperand *MMO, SelectionDAG &DAG) const; 126 127 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG, 128 bool ImageStore = false) const; 129 130 /// Converts \p Op, which must be of floating point type, to the 131 /// floating point type \p VT, by either extending or truncating it. 132 SDValue getFPExtOrFPRound(SelectionDAG &DAG, 133 SDValue Op, 134 const SDLoc &DL, 135 EVT VT) const; 136 137 SDValue convertArgType( 138 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, 139 bool Signed, const ISD::InputArg *Arg = nullptr) const; 140 141 /// Custom lowering for ISD::FP_ROUND for MVT::f16. 142 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 143 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const; 144 SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const; 145 SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 146 147 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL, 148 SelectionDAG &DAG) const; 149 150 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 151 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 152 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 153 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 154 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 155 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 156 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 157 158 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 159 SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const; 160 SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const; 161 SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const; 162 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const; 163 164 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 165 166 SDValue performUCharToFloatCombine(SDNode *N, 167 DAGCombinerInfo &DCI) const; 168 SDValue performSHLPtrCombine(SDNode *N, 169 unsigned AS, 170 EVT MemVT, 171 DAGCombinerInfo &DCI) const; 172 173 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const; 174 175 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL, 176 unsigned Opc, SDValue LHS, 177 const ConstantSDNode *CRHS) const; 178 179 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 180 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 181 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 182 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const; 183 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const; 184 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 185 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT, 186 const APFloat &C) const; 187 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 188 189 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 190 SDValue Op0, SDValue Op1) const; 191 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 192 SDValue Op0, SDValue Op1, bool Signed) const; 193 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 194 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const; 195 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const; 196 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 197 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 198 199 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const; 200 unsigned getFusedOpcode(const SelectionDAG &DAG, 201 const SDNode *N0, const SDNode *N1) const; 202 SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const; 203 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 204 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const; 205 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 206 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 207 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 208 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const; 209 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 210 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; 211 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const; 212 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const; 213 214 bool isLegalFlatAddressingMode(const AddrMode &AM) const; 215 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 216 217 unsigned isCFIntrinsic(const SDNode *Intr) const; 218 219 public: 220 /// \returns True if fixup needs to be emitted for given global value \p GV, 221 /// false otherwise. 222 bool shouldEmitFixup(const GlobalValue *GV) const; 223 224 /// \returns True if GOT relocation needs to be emitted for given global value 225 /// \p GV, false otherwise. 226 bool shouldEmitGOTReloc(const GlobalValue *GV) const; 227 228 /// \returns True if PC-relative relocation needs to be emitted for given 229 /// global value \p GV, false otherwise. 230 bool shouldEmitPCReloc(const GlobalValue *GV) const; 231 232 /// \returns true if this should use a literal constant for an LDS address, 233 /// and not emit a relocation for an LDS global. 234 bool shouldUseLDSConstAddress(const GlobalValue *GV) const; 235 236 /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be 237 /// expanded into a set of cmp/select instructions. 238 static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, 239 bool IsDivergentIdx, 240 const GCNSubtarget *Subtarget); 241 242 bool shouldExpandVectorDynExt(SDNode *N) const; 243 244 private: 245 // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the 246 // three offsets (voffset, soffset and instoffset) into the SDValue[3] array 247 // pointed to by Offsets. 248 void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG, 249 SDValue *Offsets, Align Alignment = Align(4)) const; 250 251 // Handle 8 bit and 16 bit buffer loads 252 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL, 253 ArrayRef<SDValue> Ops, MemSDNode *M) const; 254 255 // Handle 8 bit and 16 bit buffer stores 256 SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType, 257 SDLoc DL, SDValue Ops[], 258 MemSDNode *M) const; 259 260 public: 261 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI); 262 263 const GCNSubtarget *getSubtarget() const; 264 265 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, 266 EVT SrcVT) const override; 267 268 bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy, 269 LLT SrcTy) const override; 270 271 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override; 272 273 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 274 MachineFunction &MF, 275 unsigned IntrinsicID) const override; 276 277 bool getAddrModeArguments(IntrinsicInst * /*I*/, 278 SmallVectorImpl<Value*> &/*Ops*/, 279 Type *&/*AccessTy*/) const override; 280 281 bool isLegalGlobalAddressingMode(const AddrMode &AM) const; 282 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 283 unsigned AS, 284 Instruction *I = nullptr) const override; 285 286 bool canMergeStoresTo(unsigned AS, EVT MemVT, 287 const MachineFunction &MF) const override; 288 289 bool allowsMisalignedMemoryAccessesImpl( 290 unsigned Size, unsigned AddrSpace, Align Alignment, 291 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 292 bool *IsFast = nullptr) const; 293 294 bool allowsMisalignedMemoryAccesses( 295 LLT Ty, unsigned AddrSpace, Align Alignment, 296 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 297 bool *IsFast = nullptr) const override { 298 if (IsFast) 299 *IsFast = false; 300 return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace, 301 Alignment, Flags, IsFast); 302 } 303 304 bool allowsMisalignedMemoryAccesses( 305 EVT VT, unsigned AS, Align Alignment, 306 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 307 bool *IsFast = nullptr) const override; 308 309 EVT getOptimalMemOpType(const MemOp &Op, 310 const AttributeList &FuncAttributes) const override; 311 312 bool isMemOpUniform(const SDNode *N) const; 313 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; 314 315 static bool isNonGlobalAddrSpace(unsigned AS); 316 317 bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 318 319 TargetLoweringBase::LegalizeTypeAction 320 getPreferredVectorAction(MVT VT) const override; 321 322 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 323 Type *Ty) const override; 324 325 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 326 unsigned Index) const override; 327 328 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 329 330 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 331 332 bool supportSplitCSR(MachineFunction *MF) const override; 333 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 334 void insertCopiesSplitCSR( 335 MachineBasicBlock *Entry, 336 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 337 338 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 339 bool isVarArg, 340 const SmallVectorImpl<ISD::InputArg> &Ins, 341 const SDLoc &DL, SelectionDAG &DAG, 342 SmallVectorImpl<SDValue> &InVals) const override; 343 344 bool CanLowerReturn(CallingConv::ID CallConv, 345 MachineFunction &MF, bool isVarArg, 346 const SmallVectorImpl<ISD::OutputArg> &Outs, 347 LLVMContext &Context) const override; 348 349 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 350 const SmallVectorImpl<ISD::OutputArg> &Outs, 351 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 352 SelectionDAG &DAG) const override; 353 354 void passSpecialInputs( 355 CallLoweringInfo &CLI, 356 CCState &CCInfo, 357 const SIMachineFunctionInfo &Info, 358 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, 359 SmallVectorImpl<SDValue> &MemOpChains, 360 SDValue Chain) const; 361 362 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 363 CallingConv::ID CallConv, bool isVarArg, 364 const SmallVectorImpl<ISD::InputArg> &Ins, 365 const SDLoc &DL, SelectionDAG &DAG, 366 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 367 SDValue ThisVal) const; 368 369 bool mayBeEmittedAsTailCall(const CallInst *) const override; 370 371 bool isEligibleForTailCallOptimization( 372 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 373 const SmallVectorImpl<ISD::OutputArg> &Outs, 374 const SmallVectorImpl<SDValue> &OutVals, 375 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 376 377 SDValue LowerCall(CallLoweringInfo &CLI, 378 SmallVectorImpl<SDValue> &InVals) const override; 379 380 SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const; 381 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 382 383 Register getRegisterByName(const char* RegName, LLT VT, 384 const MachineFunction &MF) const override; 385 386 MachineBasicBlock *splitKillBlock(MachineInstr &MI, 387 MachineBasicBlock *BB) const; 388 389 void bundleInstWithWaitcnt(MachineInstr &MI) const; 390 MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI, 391 MachineBasicBlock *BB) const; 392 393 MachineBasicBlock * 394 EmitInstrWithCustomInserter(MachineInstr &MI, 395 MachineBasicBlock *BB) const override; 396 397 bool hasBitPreservingFPLogic(EVT VT) const override; 398 bool hasAtomicFaddRtnForTy(SDValue &Op) const; 399 bool enableAggressiveFMAFusion(EVT VT) const override; 400 bool enableAggressiveFMAFusion(LLT Ty) const override; 401 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 402 EVT VT) const override; 403 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 404 LLT getPreferredShiftAmountTy(LLT Ty) const override; 405 406 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 407 EVT VT) const override; 408 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 409 const LLT Ty) const override; 410 bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override; 411 bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override; 412 413 SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 414 SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 415 SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 416 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 417 418 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 419 SelectionDAG &DAG) const override; 420 421 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 422 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 423 void AddIMGInit(MachineInstr &MI) const; 424 void AdjustInstrPostInstrSelection(MachineInstr &MI, 425 SDNode *Node) const override; 426 427 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 428 429 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 430 SDValue Ptr) const; 431 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 432 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 433 std::pair<unsigned, const TargetRegisterClass *> 434 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 435 StringRef Constraint, MVT VT) const override; 436 ConstraintType getConstraintType(StringRef Constraint) const override; 437 void LowerAsmOperandForConstraint(SDValue Op, 438 std::string &Constraint, 439 std::vector<SDValue> &Ops, 440 SelectionDAG &DAG) const override; 441 bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const; 442 bool checkAsmConstraintVal(SDValue Op, 443 const std::string &Constraint, 444 uint64_t Val) const; 445 bool checkAsmConstraintValA(SDValue Op, 446 uint64_t Val, 447 unsigned MaxSize = 64) const; 448 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 449 SDValue V) const; 450 451 void finalizeLowering(MachineFunction &MF) const override; 452 453 void computeKnownBitsForFrameIndex(int FrameIdx, 454 KnownBits &Known, 455 const MachineFunction &MF) const override; 456 void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, 457 KnownBits &Known, 458 const APInt &DemandedElts, 459 const MachineRegisterInfo &MRI, 460 unsigned Depth = 0) const override; 461 462 Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, 463 const MachineRegisterInfo &MRI, 464 unsigned Depth = 0) const override; 465 bool isSDNodeSourceOfDivergence(const SDNode *N, 466 FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override; 467 468 bool hasMemSDNodeUser(SDNode *N) const; 469 470 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, 471 SDValue N1) const override; 472 473 bool isCanonicalized(SelectionDAG &DAG, SDValue Op, 474 unsigned MaxDepth = 5) const; 475 bool isCanonicalized(Register Reg, MachineFunction &MF, 476 unsigned MaxDepth = 5) const; 477 bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const; 478 bool denormalsEnabledForType(LLT Ty, MachineFunction &MF) const; 479 480 bool isKnownNeverNaNForTargetNode(SDValue Op, 481 const SelectionDAG &DAG, 482 bool SNaN = false, 483 unsigned Depth = 0) const override; 484 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override; 485 AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 486 AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 487 AtomicExpansionKind 488 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 489 490 const TargetRegisterClass *getRegClassFor(MVT VT, 491 bool isDivergent) const override; 492 bool requiresUniformRegister(MachineFunction &MF, 493 const Value *V) const override; 494 Align getPrefLoopAlignment(MachineLoop *ML) const override; 495 496 void allocateHSAUserSGPRs(CCState &CCInfo, 497 MachineFunction &MF, 498 const SIRegisterInfo &TRI, 499 SIMachineFunctionInfo &Info) const; 500 501 void allocateSystemSGPRs(CCState &CCInfo, 502 MachineFunction &MF, 503 SIMachineFunctionInfo &Info, 504 CallingConv::ID CallConv, 505 bool IsShader) const; 506 507 void allocateSpecialEntryInputVGPRs(CCState &CCInfo, 508 MachineFunction &MF, 509 const SIRegisterInfo &TRI, 510 SIMachineFunctionInfo &Info) const; 511 void allocateSpecialInputSGPRs( 512 CCState &CCInfo, 513 MachineFunction &MF, 514 const SIRegisterInfo &TRI, 515 SIMachineFunctionInfo &Info) const; 516 517 void allocateSpecialInputVGPRs(CCState &CCInfo, 518 MachineFunction &MF, 519 const SIRegisterInfo &TRI, 520 SIMachineFunctionInfo &Info) const; 521 void allocateSpecialInputVGPRsFixed(CCState &CCInfo, 522 MachineFunction &MF, 523 const SIRegisterInfo &TRI, 524 SIMachineFunctionInfo &Info) const; 525 526 std::pair<InstructionCost, MVT> getTypeLegalizationCost(const DataLayout &DL, 527 Type *Ty) const; 528 529 MachineMemOperand::Flags 530 getTargetMMOFlags(const Instruction &I) const override; 531 }; 532 533 } // End namespace llvm 534 535 #endif 536