1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// SI DAG Lowering interface definition 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16 17 #include "AMDGPUISelLowering.h" 18 #include "AMDGPUArgumentUsageInfo.h" 19 #include "SIInstrInfo.h" 20 21 namespace llvm { 22 23 class SITargetLowering final : public AMDGPUTargetLowering { 24 private: 25 const GCNSubtarget *Subtarget; 26 27 public: 28 MVT getRegisterTypeForCallingConv(LLVMContext &Context, 29 CallingConv::ID CC, 30 EVT VT) const override; 31 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 32 CallingConv::ID CC, 33 EVT VT) const override; 34 35 unsigned getVectorTypeBreakdownForCallingConv( 36 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 37 unsigned &NumIntermediates, MVT &RegisterVT) const override; 38 39 private: 40 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL, 41 SDValue Chain, uint64_t Offset) const; 42 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const; 43 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, 44 const SDLoc &SL, SDValue Chain, 45 uint64_t Offset, unsigned Align, bool Signed, 46 const ISD::InputArg *Arg = nullptr) const; 47 48 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, 49 const SDLoc &SL, SDValue Chain, 50 const ISD::InputArg &Arg) const; 51 SDValue getPreloadedValue(SelectionDAG &DAG, 52 const SIMachineFunctionInfo &MFI, 53 EVT VT, 54 AMDGPUFunctionArgInfo::PreloadedValue) const; 55 56 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 57 SelectionDAG &DAG) const override; 58 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 59 MVT VT, unsigned Offset) const; 60 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr, 61 SelectionDAG &DAG) const; 62 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset, 63 SDValue GLC, SDValue DLC, SelectionDAG &DAG) const; 64 65 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 66 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 67 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 68 69 // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset 70 // (the offset that is included in bounds checking and swizzling, to be split 71 // between the instruction's voffset and immoffset fields) and soffset (the 72 // offset that is excluded from bounds checking and swizzling, to go in the 73 // instruction's soffset field). This function takes the first kind of 74 // offset and figures out how to split it between voffset and immoffset. 75 std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset, 76 SelectionDAG &DAG) const; 77 78 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const; 79 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 80 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 81 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; 82 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const; 83 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const; 84 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 85 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 86 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 87 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const; 88 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 89 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 90 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 91 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 92 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 93 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, 94 SelectionDAG &DAG, ArrayRef<SDValue> Ops, 95 bool IsIntrinsic = false) const; 96 97 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to 98 // dwordx4 if on SI. 99 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, 100 ArrayRef<SDValue> Ops, EVT MemVT, 101 MachineMemOperand *MMO, SelectionDAG &DAG) const; 102 103 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG) const; 104 105 /// Converts \p Op, which must be of floating point type, to the 106 /// floating point type \p VT, by either extending or truncating it. 107 SDValue getFPExtOrFPTrunc(SelectionDAG &DAG, 108 SDValue Op, 109 const SDLoc &DL, 110 EVT VT) const; 111 112 SDValue convertArgType( 113 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, 114 bool Signed, const ISD::InputArg *Arg = nullptr) const; 115 116 /// Custom lowering for ISD::FP_ROUND for MVT::f16. 117 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 118 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const; 119 120 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL, 121 SelectionDAG &DAG) const; 122 123 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 124 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 125 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 126 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 127 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 128 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 129 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 130 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const; 131 132 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 133 134 SDValue performUCharToFloatCombine(SDNode *N, 135 DAGCombinerInfo &DCI) const; 136 SDValue performSHLPtrCombine(SDNode *N, 137 unsigned AS, 138 EVT MemVT, 139 DAGCombinerInfo &DCI) const; 140 141 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const; 142 143 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL, 144 unsigned Opc, SDValue LHS, 145 const ConstantSDNode *CRHS) const; 146 147 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 148 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 149 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 150 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const; 151 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const; 152 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 153 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT, 154 const APFloat &C) const; 155 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 156 157 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 158 SDValue Op0, SDValue Op1) const; 159 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 160 SDValue Op0, SDValue Op1, bool Signed) const; 161 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 162 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const; 163 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const; 164 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 165 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 166 167 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const; 168 unsigned getFusedOpcode(const SelectionDAG &DAG, 169 const SDNode *N0, const SDNode *N1) const; 170 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 171 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const; 172 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 173 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 174 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 175 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const; 176 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 177 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; 178 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const; 179 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const; 180 181 bool isLegalFlatAddressingMode(const AddrMode &AM) const; 182 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 183 184 unsigned isCFIntrinsic(const SDNode *Intr) const; 185 186 /// \returns True if fixup needs to be emitted for given global value \p GV, 187 /// false otherwise. 188 bool shouldEmitFixup(const GlobalValue *GV) const; 189 190 /// \returns True if GOT relocation needs to be emitted for given global value 191 /// \p GV, false otherwise. 192 bool shouldEmitGOTReloc(const GlobalValue *GV) const; 193 194 /// \returns True if PC-relative relocation needs to be emitted for given 195 /// global value \p GV, false otherwise. 196 bool shouldEmitPCReloc(const GlobalValue *GV) const; 197 198 // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the 199 // three offsets (voffset, soffset and instoffset) into the SDValue[3] array 200 // pointed to by Offsets. 201 void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG, 202 SDValue *Offsets, unsigned Align = 4) const; 203 204 // Handle 8 bit and 16 bit buffer loads 205 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL, 206 ArrayRef<SDValue> Ops, MemSDNode *M) const; 207 208 // Handle 8 bit and 16 bit buffer stores 209 SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType, 210 SDLoc DL, SDValue Ops[], 211 MemSDNode *M) const; 212 213 public: 214 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI); 215 216 const GCNSubtarget *getSubtarget() const; 217 218 bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override; 219 220 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override; 221 222 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 223 MachineFunction &MF, 224 unsigned IntrinsicID) const override; 225 226 bool getAddrModeArguments(IntrinsicInst * /*I*/, 227 SmallVectorImpl<Value*> &/*Ops*/, 228 Type *&/*AccessTy*/) const override; 229 230 bool isLegalGlobalAddressingMode(const AddrMode &AM) const; 231 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 232 unsigned AS, 233 Instruction *I = nullptr) const override; 234 235 bool canMergeStoresTo(unsigned AS, EVT MemVT, 236 const SelectionDAG &DAG) const override; 237 238 bool allowsMisalignedMemoryAccesses( 239 EVT VT, unsigned AS, unsigned Align, 240 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 241 bool *IsFast = nullptr) const override; 242 243 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 244 unsigned SrcAlign, bool IsMemset, 245 bool ZeroMemset, 246 bool MemcpyStrSrc, 247 const AttributeList &FuncAttributes) const override; 248 249 bool isMemOpUniform(const SDNode *N) const; 250 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; 251 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 252 bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 253 254 TargetLoweringBase::LegalizeTypeAction 255 getPreferredVectorAction(MVT VT) const override; 256 257 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 258 Type *Ty) const override; 259 260 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 261 262 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 263 264 bool supportSplitCSR(MachineFunction *MF) const override; 265 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 266 void insertCopiesSplitCSR( 267 MachineBasicBlock *Entry, 268 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 269 270 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 271 bool isVarArg, 272 const SmallVectorImpl<ISD::InputArg> &Ins, 273 const SDLoc &DL, SelectionDAG &DAG, 274 SmallVectorImpl<SDValue> &InVals) const override; 275 276 bool CanLowerReturn(CallingConv::ID CallConv, 277 MachineFunction &MF, bool isVarArg, 278 const SmallVectorImpl<ISD::OutputArg> &Outs, 279 LLVMContext &Context) const override; 280 281 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 282 const SmallVectorImpl<ISD::OutputArg> &Outs, 283 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 284 SelectionDAG &DAG) const override; 285 286 void passSpecialInputs( 287 CallLoweringInfo &CLI, 288 CCState &CCInfo, 289 const SIMachineFunctionInfo &Info, 290 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, 291 SmallVectorImpl<SDValue> &MemOpChains, 292 SDValue Chain) const; 293 294 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 295 CallingConv::ID CallConv, bool isVarArg, 296 const SmallVectorImpl<ISD::InputArg> &Ins, 297 const SDLoc &DL, SelectionDAG &DAG, 298 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 299 SDValue ThisVal) const; 300 301 bool mayBeEmittedAsTailCall(const CallInst *) const override; 302 303 bool isEligibleForTailCallOptimization( 304 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 305 const SmallVectorImpl<ISD::OutputArg> &Outs, 306 const SmallVectorImpl<SDValue> &OutVals, 307 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 308 309 SDValue LowerCall(CallLoweringInfo &CLI, 310 SmallVectorImpl<SDValue> &InVals) const override; 311 312 unsigned getRegisterByName(const char* RegName, EVT VT, 313 SelectionDAG &DAG) const override; 314 315 MachineBasicBlock *splitKillBlock(MachineInstr &MI, 316 MachineBasicBlock *BB) const; 317 318 MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI, 319 MachineBasicBlock *BB) const; 320 321 MachineBasicBlock * 322 EmitInstrWithCustomInserter(MachineInstr &MI, 323 MachineBasicBlock *BB) const override; 324 325 bool hasBitPreservingFPLogic(EVT VT) const override; 326 bool enableAggressiveFMAFusion(EVT VT) const override; 327 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 328 EVT VT) const override; 329 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 330 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 331 SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 332 SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 333 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 334 335 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 336 SelectionDAG &DAG) const override; 337 338 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 339 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 340 void AdjustInstrPostInstrSelection(MachineInstr &MI, 341 SDNode *Node) const override; 342 343 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 344 345 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 346 SDValue Ptr) const; 347 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 348 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 349 std::pair<unsigned, const TargetRegisterClass *> 350 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 351 StringRef Constraint, MVT VT) const override; 352 ConstraintType getConstraintType(StringRef Constraint) const override; 353 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 354 SDValue V) const; 355 356 void finalizeLowering(MachineFunction &MF) const override; 357 358 void computeKnownBitsForFrameIndex(const SDValue Op, 359 KnownBits &Known, 360 const APInt &DemandedElts, 361 const SelectionDAG &DAG, 362 unsigned Depth = 0) const override; 363 364 bool isSDNodeSourceOfDivergence(const SDNode *N, 365 FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override; 366 367 bool isCanonicalized(SelectionDAG &DAG, SDValue Op, 368 unsigned MaxDepth = 5) const; 369 bool denormalsEnabledForType(EVT VT) const; 370 371 bool isKnownNeverNaNForTargetNode(SDValue Op, 372 const SelectionDAG &DAG, 373 bool SNaN = false, 374 unsigned Depth = 0) const override; 375 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override; 376 377 unsigned getPrefLoopAlignment(MachineLoop *ML) const override; 378 }; 379 380 } // End namespace llvm 381 382 #endif 383