1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// SI DAG Lowering interface definition 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16 17 #include "AMDGPUISelLowering.h" 18 #include "AMDGPUArgumentUsageInfo.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 21 namespace llvm { 22 23 class GCNSubtarget; 24 class SIMachineFunctionInfo; 25 class SIRegisterInfo; 26 27 namespace AMDGPU { 28 struct ImageDimIntrinsicInfo; 29 } 30 31 class SITargetLowering final : public AMDGPUTargetLowering { 32 private: 33 const GCNSubtarget *Subtarget; 34 35 public: 36 MVT getRegisterTypeForCallingConv(LLVMContext &Context, 37 CallingConv::ID CC, 38 EVT VT) const override; 39 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 40 CallingConv::ID CC, 41 EVT VT) const override; 42 43 unsigned getVectorTypeBreakdownForCallingConv( 44 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 45 unsigned &NumIntermediates, MVT &RegisterVT) const override; 46 47 private: 48 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL, 49 SDValue Chain, uint64_t Offset) const; 50 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const; 51 SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const; 52 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, 53 const SDLoc &SL, SDValue Chain, 54 uint64_t Offset, Align Alignment, 55 bool Signed, 56 const ISD::InputArg *Arg = nullptr) const; 57 SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL, 58 Align Alignment, 59 ImplicitParameter Param) const; 60 61 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, 62 const SDLoc &SL, SDValue Chain, 63 const ISD::InputArg &Arg) const; 64 SDValue getPreloadedValue(SelectionDAG &DAG, 65 const SIMachineFunctionInfo &MFI, 66 EVT VT, 67 AMDGPUFunctionArgInfo::PreloadedValue) const; 68 69 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 70 SelectionDAG &DAG) const override; 71 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 72 MVT VT, unsigned Offset) const; 73 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr, 74 SelectionDAG &DAG, bool WithChain) const; 75 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset, 76 SDValue CachePolicy, SelectionDAG &DAG) const; 77 78 SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 79 unsigned NewOpcode) const; 80 SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 81 unsigned NewOpcode) const; 82 83 SDValue lowerWorkitemID(SelectionDAG &DAG, SDValue Op, unsigned Dim, 84 const ArgDescriptor &ArgDesc) const; 85 86 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 87 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 88 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 89 90 SDValue makeV_ILLEGAL(SDValue Op, SelectionDAG &DAG) const; 91 92 // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset 93 // (the offset that is included in bounds checking and swizzling, to be split 94 // between the instruction's voffset and immoffset fields) and soffset (the 95 // offset that is excluded from bounds checking and swizzling, to go in the 96 // instruction's soffset field). This function takes the first kind of 97 // offset and figures out how to split it between voffset and immoffset. 98 std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset, 99 SelectionDAG &DAG) const; 100 101 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const; 102 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 103 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 104 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; 105 SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const; 106 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const; 107 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const; 108 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 109 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 110 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 111 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 112 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 113 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 114 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 115 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 116 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, 117 SelectionDAG &DAG, ArrayRef<SDValue> Ops, 118 bool IsIntrinsic = false) const; 119 120 SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG, 121 ArrayRef<SDValue> Ops) const; 122 123 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to 124 // dwordx4 if on SI. 125 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, 126 ArrayRef<SDValue> Ops, EVT MemVT, 127 MachineMemOperand *MMO, SelectionDAG &DAG) const; 128 129 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG, 130 bool ImageStore = false) const; 131 132 /// Converts \p Op, which must be of floating point type, to the 133 /// floating point type \p VT, by either extending or truncating it. 134 SDValue getFPExtOrFPRound(SelectionDAG &DAG, 135 SDValue Op, 136 const SDLoc &DL, 137 EVT VT) const; 138 139 SDValue convertArgType( 140 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, 141 bool Signed, const ISD::InputArg *Arg = nullptr) const; 142 143 /// Custom lowering for ISD::FP_ROUND for MVT::f16. 144 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 145 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const; 146 SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const; 147 SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 148 149 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL, 150 SelectionDAG &DAG) const; 151 152 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 153 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 154 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 155 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 156 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 157 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 158 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 159 160 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 161 SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const; 162 SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const; 163 SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const; 164 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const; 165 166 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 167 168 SDValue performUCharToFloatCombine(SDNode *N, 169 DAGCombinerInfo &DCI) const; 170 SDValue performSHLPtrCombine(SDNode *N, 171 unsigned AS, 172 EVT MemVT, 173 DAGCombinerInfo &DCI) const; 174 175 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const; 176 177 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL, 178 unsigned Opc, SDValue LHS, 179 const ConstantSDNode *CRHS) const; 180 181 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 182 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 183 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 184 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const; 185 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const; 186 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 187 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT, 188 const APFloat &C) const; 189 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 190 191 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 192 SDValue Op0, SDValue Op1) const; 193 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 194 SDValue Op0, SDValue Op1, bool Signed) const; 195 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 196 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const; 197 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const; 198 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 199 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 200 201 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const; 202 unsigned getFusedOpcode(const SelectionDAG &DAG, 203 const SDNode *N0, const SDNode *N1) const; 204 SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const; 205 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 206 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const; 207 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 208 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 209 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 210 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const; 211 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 212 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; 213 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const; 214 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const; 215 216 bool isLegalFlatAddressingMode(const AddrMode &AM) const; 217 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 218 219 unsigned isCFIntrinsic(const SDNode *Intr) const; 220 221 public: 222 /// \returns True if fixup needs to be emitted for given global value \p GV, 223 /// false otherwise. 224 bool shouldEmitFixup(const GlobalValue *GV) const; 225 226 /// \returns True if GOT relocation needs to be emitted for given global value 227 /// \p GV, false otherwise. 228 bool shouldEmitGOTReloc(const GlobalValue *GV) const; 229 230 /// \returns True if PC-relative relocation needs to be emitted for given 231 /// global value \p GV, false otherwise. 232 bool shouldEmitPCReloc(const GlobalValue *GV) const; 233 234 /// \returns true if this should use a literal constant for an LDS address, 235 /// and not emit a relocation for an LDS global. 236 bool shouldUseLDSConstAddress(const GlobalValue *GV) const; 237 238 /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be 239 /// expanded into a set of cmp/select instructions. 240 static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, 241 bool IsDivergentIdx, 242 const GCNSubtarget *Subtarget); 243 244 bool shouldExpandVectorDynExt(SDNode *N) const; 245 246 private: 247 // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the 248 // three offsets (voffset, soffset and instoffset) into the SDValue[3] array 249 // pointed to by Offsets. 250 void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG, 251 SDValue *Offsets, Align Alignment = Align(4)) const; 252 253 // Handle 8 bit and 16 bit buffer loads 254 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL, 255 ArrayRef<SDValue> Ops, MemSDNode *M) const; 256 257 // Handle 8 bit and 16 bit buffer stores 258 SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType, 259 SDLoc DL, SDValue Ops[], 260 MemSDNode *M) const; 261 262 public: 263 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI); 264 265 const GCNSubtarget *getSubtarget() const; 266 267 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, 268 EVT SrcVT) const override; 269 270 bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy, 271 LLT SrcTy) const override; 272 273 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override; 274 275 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 276 MachineFunction &MF, 277 unsigned IntrinsicID) const override; 278 279 bool getAddrModeArguments(IntrinsicInst * /*I*/, 280 SmallVectorImpl<Value*> &/*Ops*/, 281 Type *&/*AccessTy*/) const override; 282 283 bool isLegalGlobalAddressingMode(const AddrMode &AM) const; 284 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 285 unsigned AS, 286 Instruction *I = nullptr) const override; 287 288 bool canMergeStoresTo(unsigned AS, EVT MemVT, 289 const MachineFunction &MF) const override; 290 291 bool allowsMisalignedMemoryAccessesImpl( 292 unsigned Size, unsigned AddrSpace, Align Alignment, 293 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 294 unsigned *IsFast = nullptr) const; 295 296 bool allowsMisalignedMemoryAccesses( 297 LLT Ty, unsigned AddrSpace, Align Alignment, 298 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 299 unsigned *IsFast = nullptr) const override { 300 if (IsFast) 301 *IsFast = 0; 302 return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace, 303 Alignment, Flags, IsFast); 304 } 305 306 bool allowsMisalignedMemoryAccesses( 307 EVT VT, unsigned AS, Align Alignment, 308 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 309 unsigned *IsFast = nullptr) const override; 310 311 EVT getOptimalMemOpType(const MemOp &Op, 312 const AttributeList &FuncAttributes) const override; 313 314 bool isMemOpUniform(const SDNode *N) const; 315 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; 316 317 static bool isNonGlobalAddrSpace(unsigned AS); 318 319 bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 320 321 TargetLoweringBase::LegalizeTypeAction 322 getPreferredVectorAction(MVT VT) const override; 323 324 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 325 Type *Ty) const override; 326 327 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 328 unsigned Index) const override; 329 330 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 331 332 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 333 334 bool supportSplitCSR(MachineFunction *MF) const override; 335 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 336 void insertCopiesSplitCSR( 337 MachineBasicBlock *Entry, 338 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 339 340 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 341 bool isVarArg, 342 const SmallVectorImpl<ISD::InputArg> &Ins, 343 const SDLoc &DL, SelectionDAG &DAG, 344 SmallVectorImpl<SDValue> &InVals) const override; 345 346 bool CanLowerReturn(CallingConv::ID CallConv, 347 MachineFunction &MF, bool isVarArg, 348 const SmallVectorImpl<ISD::OutputArg> &Outs, 349 LLVMContext &Context) const override; 350 351 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 352 const SmallVectorImpl<ISD::OutputArg> &Outs, 353 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 354 SelectionDAG &DAG) const override; 355 356 void passSpecialInputs( 357 CallLoweringInfo &CLI, 358 CCState &CCInfo, 359 const SIMachineFunctionInfo &Info, 360 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, 361 SmallVectorImpl<SDValue> &MemOpChains, 362 SDValue Chain) const; 363 364 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 365 CallingConv::ID CallConv, bool isVarArg, 366 const SmallVectorImpl<ISD::InputArg> &Ins, 367 const SDLoc &DL, SelectionDAG &DAG, 368 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 369 SDValue ThisVal) const; 370 371 bool mayBeEmittedAsTailCall(const CallInst *) const override; 372 373 bool isEligibleForTailCallOptimization( 374 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 375 const SmallVectorImpl<ISD::OutputArg> &Outs, 376 const SmallVectorImpl<SDValue> &OutVals, 377 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 378 379 SDValue LowerCall(CallLoweringInfo &CLI, 380 SmallVectorImpl<SDValue> &InVals) const override; 381 382 SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const; 383 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 384 385 Register getRegisterByName(const char* RegName, LLT VT, 386 const MachineFunction &MF) const override; 387 388 MachineBasicBlock *splitKillBlock(MachineInstr &MI, 389 MachineBasicBlock *BB) const; 390 391 void bundleInstWithWaitcnt(MachineInstr &MI) const; 392 MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI, 393 MachineBasicBlock *BB) const; 394 395 MachineBasicBlock * 396 EmitInstrWithCustomInserter(MachineInstr &MI, 397 MachineBasicBlock *BB) const override; 398 399 bool hasBitPreservingFPLogic(EVT VT) const override; 400 bool hasAtomicFaddRtnForTy(SDValue &Op) const; 401 bool enableAggressiveFMAFusion(EVT VT) const override; 402 bool enableAggressiveFMAFusion(LLT Ty) const override; 403 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 404 EVT VT) const override; 405 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 406 LLT getPreferredShiftAmountTy(LLT Ty) const override; 407 408 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 409 EVT VT) const override; 410 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 411 const LLT Ty) const override; 412 bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override; 413 bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override; 414 415 SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 416 SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 417 SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 418 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 419 420 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 421 SelectionDAG &DAG) const override; 422 423 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 424 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 425 void AddIMGInit(MachineInstr &MI) const; 426 void AdjustInstrPostInstrSelection(MachineInstr &MI, 427 SDNode *Node) const override; 428 429 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 430 431 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 432 SDValue Ptr) const; 433 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 434 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 435 std::pair<unsigned, const TargetRegisterClass *> 436 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 437 StringRef Constraint, MVT VT) const override; 438 ConstraintType getConstraintType(StringRef Constraint) const override; 439 void LowerAsmOperandForConstraint(SDValue Op, 440 std::string &Constraint, 441 std::vector<SDValue> &Ops, 442 SelectionDAG &DAG) const override; 443 bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const; 444 bool checkAsmConstraintVal(SDValue Op, 445 const std::string &Constraint, 446 uint64_t Val) const; 447 bool checkAsmConstraintValA(SDValue Op, 448 uint64_t Val, 449 unsigned MaxSize = 64) const; 450 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 451 SDValue V) const; 452 453 void finalizeLowering(MachineFunction &MF) const override; 454 455 void computeKnownBitsForFrameIndex(int FrameIdx, 456 KnownBits &Known, 457 const MachineFunction &MF) const override; 458 void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, 459 KnownBits &Known, 460 const APInt &DemandedElts, 461 const MachineRegisterInfo &MRI, 462 unsigned Depth = 0) const override; 463 464 Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, 465 const MachineRegisterInfo &MRI, 466 unsigned Depth = 0) const override; 467 bool isSDNodeSourceOfDivergence(const SDNode *N, 468 FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override; 469 470 bool hasMemSDNodeUser(SDNode *N) const; 471 472 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, 473 SDValue N1) const override; 474 475 bool isCanonicalized(SelectionDAG &DAG, SDValue Op, 476 unsigned MaxDepth = 5) const; 477 bool isCanonicalized(Register Reg, MachineFunction &MF, 478 unsigned MaxDepth = 5) const; 479 bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const; 480 bool denormalsEnabledForType(LLT Ty, MachineFunction &MF) const; 481 482 bool checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, 483 const TargetRegisterInfo *TRI, 484 const TargetInstrInfo *TII, unsigned &PhysReg, 485 int &Cost) const override; 486 487 bool isKnownNeverNaNForTargetNode(SDValue Op, 488 const SelectionDAG &DAG, 489 bool SNaN = false, 490 unsigned Depth = 0) const override; 491 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override; 492 AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 493 AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 494 AtomicExpansionKind 495 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 496 void emitExpandAtomicRMW(AtomicRMWInst *AI) const override; 497 498 const TargetRegisterClass *getRegClassFor(MVT VT, 499 bool isDivergent) const override; 500 bool requiresUniformRegister(MachineFunction &MF, 501 const Value *V) const override; 502 Align getPrefLoopAlignment(MachineLoop *ML) const override; 503 504 void allocateHSAUserSGPRs(CCState &CCInfo, 505 MachineFunction &MF, 506 const SIRegisterInfo &TRI, 507 SIMachineFunctionInfo &Info) const; 508 509 void allocateSystemSGPRs(CCState &CCInfo, 510 MachineFunction &MF, 511 SIMachineFunctionInfo &Info, 512 CallingConv::ID CallConv, 513 bool IsShader) const; 514 515 void allocateSpecialEntryInputVGPRs(CCState &CCInfo, 516 MachineFunction &MF, 517 const SIRegisterInfo &TRI, 518 SIMachineFunctionInfo &Info) const; 519 void allocateSpecialInputSGPRs( 520 CCState &CCInfo, 521 MachineFunction &MF, 522 const SIRegisterInfo &TRI, 523 SIMachineFunctionInfo &Info) const; 524 525 void allocateSpecialInputVGPRs(CCState &CCInfo, 526 MachineFunction &MF, 527 const SIRegisterInfo &TRI, 528 SIMachineFunctionInfo &Info) const; 529 void allocateSpecialInputVGPRsFixed(CCState &CCInfo, 530 MachineFunction &MF, 531 const SIRegisterInfo &TRI, 532 SIMachineFunctionInfo &Info) const; 533 534 MachineMemOperand::Flags 535 getTargetMMOFlags(const Instruction &I) const override; 536 }; 537 538 } // End namespace llvm 539 540 #endif 541