xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.h (revision 0d8fe2373503aeac48492f28073049a8bfa4feb5)
1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// SI DAG Lowering interface definition
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16 
17 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUArgumentUsageInfo.h"
19 
20 namespace llvm {
21 
22 class GCNSubtarget;
23 class SIMachineFunctionInfo;
24 class SIRegisterInfo;
25 
26 namespace AMDGPU {
27 struct ImageDimIntrinsicInfo;
28 }
29 
30 class SITargetLowering final : public AMDGPUTargetLowering {
31 private:
32   const GCNSubtarget *Subtarget;
33 
34 public:
35   MVT getRegisterTypeForCallingConv(LLVMContext &Context,
36                                     CallingConv::ID CC,
37                                     EVT VT) const override;
38   unsigned getNumRegistersForCallingConv(LLVMContext &Context,
39                                          CallingConv::ID CC,
40                                          EVT VT) const override;
41 
42   unsigned getVectorTypeBreakdownForCallingConv(
43     LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
44     unsigned &NumIntermediates, MVT &RegisterVT) const override;
45 
46 private:
47   SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
48                                    SDValue Chain, uint64_t Offset) const;
49   SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
50   SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
51                                    const SDLoc &SL, SDValue Chain,
52                                    uint64_t Offset, Align Alignment,
53                                    bool Signed,
54                                    const ISD::InputArg *Arg = nullptr) const;
55 
56   SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
57                               const SDLoc &SL, SDValue Chain,
58                               const ISD::InputArg &Arg) const;
59   SDValue getPreloadedValue(SelectionDAG &DAG,
60                             const SIMachineFunctionInfo &MFI,
61                             EVT VT,
62                             AMDGPUFunctionArgInfo::PreloadedValue) const;
63 
64   SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
65                              SelectionDAG &DAG) const override;
66   SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
67                                  MVT VT, unsigned Offset) const;
68   SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr,
69                      SelectionDAG &DAG, bool WithChain) const;
70   SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
71                        SDValue CachePolicy, SelectionDAG &DAG) const;
72 
73   SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
74                                      unsigned NewOpcode) const;
75   SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
76                                         unsigned NewOpcode) const;
77 
78   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
79   SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
80   SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
81 
82   // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
83   // (the offset that is included in bounds checking and swizzling, to be split
84   // between the instruction's voffset and immoffset fields) and soffset (the
85   // offset that is excluded from bounds checking and swizzling, to go in the
86   // instruction's soffset field).  This function takes the first kind of
87   // offset and figures out how to split it between voffset and immoffset.
88   std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
89                                                  SelectionDAG &DAG) const;
90 
91   SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
92   SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
93   SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
94   SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
95   SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const;
96   SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
97   SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
98   SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
99   SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
100   SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
101   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
102   SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
103   SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
104   SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
105   SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
106   SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
107                               SelectionDAG &DAG, ArrayRef<SDValue> Ops,
108                               bool IsIntrinsic = false) const;
109 
110   SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG,
111                              ArrayRef<SDValue> Ops) const;
112 
113   // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
114   // dwordx4 if on SI.
115   SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
116                               ArrayRef<SDValue> Ops, EVT MemVT,
117                               MachineMemOperand *MMO, SelectionDAG &DAG) const;
118 
119   SDValue handleD16VData(SDValue VData, SelectionDAG &DAG,
120                          bool ImageStore = false) const;
121 
122   /// Converts \p Op, which must be of floating point type, to the
123   /// floating point type \p VT, by either extending or truncating it.
124   SDValue getFPExtOrFPRound(SelectionDAG &DAG,
125                             SDValue Op,
126                             const SDLoc &DL,
127                             EVT VT) const;
128 
129   SDValue convertArgType(
130     SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
131     bool Signed, const ISD::InputArg *Arg = nullptr) const;
132 
133   /// Custom lowering for ISD::FP_ROUND for MVT::f16.
134   SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
135   SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
136   SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const;
137 
138   SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
139                              SelectionDAG &DAG) const;
140 
141   SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
142   SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
143   SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
144   SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
145   SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
146   SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
147   SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
148   SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
149 
150   SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
151 
152   SDValue performUCharToFloatCombine(SDNode *N,
153                                      DAGCombinerInfo &DCI) const;
154   SDValue performSHLPtrCombine(SDNode *N,
155                                unsigned AS,
156                                EVT MemVT,
157                                DAGCombinerInfo &DCI) const;
158 
159   SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
160 
161   SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
162                                    unsigned Opc, SDValue LHS,
163                                    const ConstantSDNode *CRHS) const;
164 
165   SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
166   SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
167   SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
168   SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
169   SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
170   SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
171   SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
172                                  const APFloat &C) const;
173   SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
174 
175   SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
176                                   SDValue Op0, SDValue Op1) const;
177   SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
178                                    SDValue Op0, SDValue Op1, bool Signed) const;
179   SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
180   SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
181   SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
182   SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
183   SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
184 
185   SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
186   unsigned getFusedOpcode(const SelectionDAG &DAG,
187                           const SDNode *N0, const SDNode *N1) const;
188   SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
189   SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
190   SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
191   SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
192   SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
193   SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
194   SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
195   SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
196   SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
197   SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
198 
199   bool isLegalFlatAddressingMode(const AddrMode &AM) const;
200   bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
201 
202   unsigned isCFIntrinsic(const SDNode *Intr) const;
203 
204 public:
205   /// \returns True if fixup needs to be emitted for given global value \p GV,
206   /// false otherwise.
207   bool shouldEmitFixup(const GlobalValue *GV) const;
208 
209   /// \returns True if GOT relocation needs to be emitted for given global value
210   /// \p GV, false otherwise.
211   bool shouldEmitGOTReloc(const GlobalValue *GV) const;
212 
213   /// \returns True if PC-relative relocation needs to be emitted for given
214   /// global value \p GV, false otherwise.
215   bool shouldEmitPCReloc(const GlobalValue *GV) const;
216 
217   /// \returns true if this should use a literal constant for an LDS address,
218   /// and not emit a relocation for an LDS global.
219   bool shouldUseLDSConstAddress(const GlobalValue *GV) const;
220 
221   /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be
222   /// expanded into a set of cmp/select instructions.
223   static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem,
224                                        bool IsDivergentIdx);
225 
226 private:
227   // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the
228   // three offsets (voffset, soffset and instoffset) into the SDValue[3] array
229   // pointed to by Offsets.
230   /// \returns 0 If there is a non-constant offset or if the offset is 0.
231   /// Otherwise returns the constant offset.
232   unsigned setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
233                             SDValue *Offsets, Align Alignment = Align(4)) const;
234 
235   // Handle 8 bit and 16 bit buffer loads
236   SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
237                                      ArrayRef<SDValue> Ops, MemSDNode *M) const;
238 
239   // Handle 8 bit and 16 bit buffer stores
240   SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
241                                       SDLoc DL, SDValue Ops[],
242                                       MemSDNode *M) const;
243 
244 public:
245   SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
246 
247   const GCNSubtarget *getSubtarget() const;
248 
249   bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
250                        EVT SrcVT) const override;
251 
252   bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
253 
254   bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
255                           MachineFunction &MF,
256                           unsigned IntrinsicID) const override;
257 
258   bool getAddrModeArguments(IntrinsicInst * /*I*/,
259                             SmallVectorImpl<Value*> &/*Ops*/,
260                             Type *&/*AccessTy*/) const override;
261 
262   bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
263   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
264                              unsigned AS,
265                              Instruction *I = nullptr) const override;
266 
267   bool canMergeStoresTo(unsigned AS, EVT MemVT,
268                         const SelectionDAG &DAG) const override;
269 
270   bool allowsMisalignedMemoryAccessesImpl(
271       unsigned Size, unsigned AddrSpace, Align Alignment,
272       MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
273       bool *IsFast = nullptr) const;
274 
275   bool allowsMisalignedMemoryAccesses(
276       LLT Ty, unsigned AddrSpace, Align Alignment,
277       MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
278       bool *IsFast = nullptr) const override {
279     if (IsFast)
280       *IsFast = false;
281     return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace,
282                                               Alignment, Flags, IsFast);
283   }
284 
285   bool allowsMisalignedMemoryAccesses(
286       EVT VT, unsigned AS, unsigned Alignment,
287       MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
288       bool *IsFast = nullptr) const override;
289 
290   EVT getOptimalMemOpType(const MemOp &Op,
291                           const AttributeList &FuncAttributes) const override;
292 
293   bool isMemOpUniform(const SDNode *N) const;
294   bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
295 
296   static bool isNonGlobalAddrSpace(unsigned AS);
297 
298   bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
299 
300   TargetLoweringBase::LegalizeTypeAction
301   getPreferredVectorAction(MVT VT) const override;
302 
303   bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
304                                         Type *Ty) const override;
305 
306   bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
307 
308   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
309 
310   bool supportSplitCSR(MachineFunction *MF) const override;
311   void initializeSplitCSR(MachineBasicBlock *Entry) const override;
312   void insertCopiesSplitCSR(
313     MachineBasicBlock *Entry,
314     const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
315 
316   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
317                                bool isVarArg,
318                                const SmallVectorImpl<ISD::InputArg> &Ins,
319                                const SDLoc &DL, SelectionDAG &DAG,
320                                SmallVectorImpl<SDValue> &InVals) const override;
321 
322   bool CanLowerReturn(CallingConv::ID CallConv,
323                       MachineFunction &MF, bool isVarArg,
324                       const SmallVectorImpl<ISD::OutputArg> &Outs,
325                       LLVMContext &Context) const override;
326 
327   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
328                       const SmallVectorImpl<ISD::OutputArg> &Outs,
329                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
330                       SelectionDAG &DAG) const override;
331 
332   void passSpecialInputs(
333     CallLoweringInfo &CLI,
334     CCState &CCInfo,
335     const SIMachineFunctionInfo &Info,
336     SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
337     SmallVectorImpl<SDValue> &MemOpChains,
338     SDValue Chain) const;
339 
340   SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
341                           CallingConv::ID CallConv, bool isVarArg,
342                           const SmallVectorImpl<ISD::InputArg> &Ins,
343                           const SDLoc &DL, SelectionDAG &DAG,
344                           SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
345                           SDValue ThisVal) const;
346 
347   bool mayBeEmittedAsTailCall(const CallInst *) const override;
348 
349   bool isEligibleForTailCallOptimization(
350     SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
351     const SmallVectorImpl<ISD::OutputArg> &Outs,
352     const SmallVectorImpl<SDValue> &OutVals,
353     const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
354 
355   SDValue LowerCall(CallLoweringInfo &CLI,
356                     SmallVectorImpl<SDValue> &InVals) const override;
357 
358   SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const;
359   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
360 
361   Register getRegisterByName(const char* RegName, LLT VT,
362                              const MachineFunction &MF) const override;
363 
364   MachineBasicBlock *splitKillBlock(MachineInstr &MI,
365                                     MachineBasicBlock *BB) const;
366 
367   void bundleInstWithWaitcnt(MachineInstr &MI) const;
368   MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI,
369                                             MachineBasicBlock *BB) const;
370 
371   MachineBasicBlock *
372   EmitInstrWithCustomInserter(MachineInstr &MI,
373                               MachineBasicBlock *BB) const override;
374 
375   bool hasBitPreservingFPLogic(EVT VT) const override;
376   bool enableAggressiveFMAFusion(EVT VT) const override;
377   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
378                          EVT VT) const override;
379   MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
380   LLT getPreferredShiftAmountTy(LLT Ty) const override;
381 
382   bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
383                                   EVT VT) const override;
384   bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override;
385 
386   SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
387   SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
388   SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
389   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
390 
391   void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
392                           SelectionDAG &DAG) const override;
393 
394   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
395   SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
396   void AdjustInstrPostInstrSelection(MachineInstr &MI,
397                                      SDNode *Node) const override;
398 
399   SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
400 
401   MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
402                                 SDValue Ptr) const;
403   MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
404                            uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
405   std::pair<unsigned, const TargetRegisterClass *>
406   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
407                                StringRef Constraint, MVT VT) const override;
408   ConstraintType getConstraintType(StringRef Constraint) const override;
409   void LowerAsmOperandForConstraint(SDValue Op,
410                                     std::string &Constraint,
411                                     std::vector<SDValue> &Ops,
412                                     SelectionDAG &DAG) const override;
413   bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
414   bool checkAsmConstraintVal(SDValue Op,
415                              const std::string &Constraint,
416                              uint64_t Val) const;
417   bool checkAsmConstraintValA(SDValue Op,
418                               uint64_t Val,
419                               unsigned MaxSize = 64) const;
420   SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
421                    SDValue V) const;
422 
423   void finalizeLowering(MachineFunction &MF) const override;
424 
425   void computeKnownBitsForFrameIndex(int FrameIdx,
426                                      KnownBits &Known,
427                                      const MachineFunction &MF) const override;
428   void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R,
429                                       KnownBits &Known,
430                                       const APInt &DemandedElts,
431                                       const MachineRegisterInfo &MRI,
432                                       unsigned Depth = 0) const override;
433 
434   Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R,
435                                         const MachineRegisterInfo &MRI,
436                                         unsigned Depth = 0) const override;
437   bool isSDNodeSourceOfDivergence(const SDNode *N,
438     FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override;
439 
440   bool isCanonicalized(SelectionDAG &DAG, SDValue Op,
441                        unsigned MaxDepth = 5) const;
442   bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const;
443 
444   bool isKnownNeverNaNForTargetNode(SDValue Op,
445                                     const SelectionDAG &DAG,
446                                     bool SNaN = false,
447                                     unsigned Depth = 0) const override;
448   AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
449 
450   virtual const TargetRegisterClass *
451   getRegClassFor(MVT VT, bool isDivergent) const override;
452   virtual bool requiresUniformRegister(MachineFunction &MF,
453                                        const Value *V) const override;
454   Align getPrefLoopAlignment(MachineLoop *ML) const override;
455 
456   void allocateHSAUserSGPRs(CCState &CCInfo,
457                             MachineFunction &MF,
458                             const SIRegisterInfo &TRI,
459                             SIMachineFunctionInfo &Info) const;
460 
461   void allocateSystemSGPRs(CCState &CCInfo,
462                            MachineFunction &MF,
463                            SIMachineFunctionInfo &Info,
464                            CallingConv::ID CallConv,
465                            bool IsShader) const;
466 
467   void allocateSpecialEntryInputVGPRs(CCState &CCInfo,
468                                       MachineFunction &MF,
469                                       const SIRegisterInfo &TRI,
470                                       SIMachineFunctionInfo &Info) const;
471   void allocateSpecialInputSGPRs(
472     CCState &CCInfo,
473     MachineFunction &MF,
474     const SIRegisterInfo &TRI,
475     SIMachineFunctionInfo &Info) const;
476 
477   void allocateSpecialInputVGPRs(CCState &CCInfo,
478                                  MachineFunction &MF,
479                                  const SIRegisterInfo &TRI,
480                                  SIMachineFunctionInfo &Info) const;
481   void allocateSpecialInputVGPRsFixed(CCState &CCInfo,
482                                       MachineFunction &MF,
483                                       const SIRegisterInfo &TRI,
484                                       SIMachineFunctionInfo &Info) const;
485 
486   std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
487                                               Type *Ty) const;
488 };
489 
490 } // End namespace llvm
491 
492 #endif
493