1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// SI DAG Lowering interface definition 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16 17 #include "AMDGPUISelLowering.h" 18 #include "AMDGPUArgumentUsageInfo.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 21 namespace llvm { 22 23 class GCNSubtarget; 24 class SIMachineFunctionInfo; 25 class SIRegisterInfo; 26 27 namespace AMDGPU { 28 struct ImageDimIntrinsicInfo; 29 } 30 31 class SITargetLowering final : public AMDGPUTargetLowering { 32 private: 33 const GCNSubtarget *Subtarget; 34 35 public: 36 MVT getRegisterTypeForCallingConv(LLVMContext &Context, 37 CallingConv::ID CC, 38 EVT VT) const override; 39 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 40 CallingConv::ID CC, 41 EVT VT) const override; 42 43 unsigned getVectorTypeBreakdownForCallingConv( 44 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 45 unsigned &NumIntermediates, MVT &RegisterVT) const override; 46 47 private: 48 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL, 49 SDValue Chain, uint64_t Offset) const; 50 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const; 51 SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const; 52 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, 53 const SDLoc &SL, SDValue Chain, 54 uint64_t Offset, Align Alignment, 55 bool Signed, 56 const ISD::InputArg *Arg = nullptr) const; 57 SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL, 58 Align Alignment, 59 ImplicitParameter Param) const; 60 61 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, 62 const SDLoc &SL, SDValue Chain, 63 const ISD::InputArg &Arg) const; 64 SDValue getPreloadedValue(SelectionDAG &DAG, 65 const SIMachineFunctionInfo &MFI, 66 EVT VT, 67 AMDGPUFunctionArgInfo::PreloadedValue) const; 68 69 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 70 SelectionDAG &DAG) const override; 71 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 72 MVT VT, unsigned Offset) const; 73 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr, 74 SelectionDAG &DAG, bool WithChain) const; 75 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset, 76 SDValue CachePolicy, SelectionDAG &DAG) const; 77 78 SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 79 unsigned NewOpcode) const; 80 SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 81 unsigned NewOpcode) const; 82 83 SDValue lowerWorkitemID(SelectionDAG &DAG, SDValue Op, unsigned Dim, 84 const ArgDescriptor &ArgDesc) const; 85 86 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 87 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 88 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 89 90 // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset 91 // (the offset that is included in bounds checking and swizzling, to be split 92 // between the instruction's voffset and immoffset fields) and soffset (the 93 // offset that is excluded from bounds checking and swizzling, to go in the 94 // instruction's soffset field). This function takes the first kind of 95 // offset and figures out how to split it between voffset and immoffset. 96 std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset, 97 SelectionDAG &DAG) const; 98 99 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const; 100 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 101 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 102 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; 103 SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const; 104 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const; 105 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const; 106 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 107 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 108 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 109 SDValue LowerFFREXP(SDValue Op, SelectionDAG &DAG) const; 110 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 111 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 112 SDValue lowerFSQRTF64(SDValue Op, SelectionDAG &DAG) const; 113 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 114 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 115 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 116 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, 117 SelectionDAG &DAG, ArrayRef<SDValue> Ops, 118 bool IsIntrinsic = false) const; 119 120 SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG, 121 ArrayRef<SDValue> Ops) const; 122 123 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to 124 // dwordx4 if on SI. 125 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, 126 ArrayRef<SDValue> Ops, EVT MemVT, 127 MachineMemOperand *MMO, SelectionDAG &DAG) const; 128 129 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG, 130 bool ImageStore = false) const; 131 132 /// Converts \p Op, which must be of floating point type, to the 133 /// floating point type \p VT, by either extending or truncating it. 134 SDValue getFPExtOrFPRound(SelectionDAG &DAG, 135 SDValue Op, 136 const SDLoc &DL, 137 EVT VT) const; 138 139 SDValue convertArgType( 140 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, 141 bool Signed, const ISD::InputArg *Arg = nullptr) const; 142 143 /// Custom lowering for ISD::FP_ROUND for MVT::f16. 144 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 145 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const; 146 SDValue lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const; 147 SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const; 148 SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 149 150 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL, 151 SelectionDAG &DAG) const; 152 153 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 154 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 155 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 156 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 157 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 158 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 159 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 160 161 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 162 SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const; 163 SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const; 164 SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const; 165 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const; 166 167 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 168 169 SDValue performUCharToFloatCombine(SDNode *N, 170 DAGCombinerInfo &DCI) const; 171 SDValue performFCopySignCombine(SDNode *N, DAGCombinerInfo &DCI) const; 172 173 SDValue performSHLPtrCombine(SDNode *N, 174 unsigned AS, 175 EVT MemVT, 176 DAGCombinerInfo &DCI) const; 177 178 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const; 179 180 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL, 181 unsigned Opc, SDValue LHS, 182 const ConstantSDNode *CRHS) const; 183 184 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 185 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 186 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 187 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const; 188 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const; 189 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 190 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT, 191 const APFloat &C) const; 192 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 193 194 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 195 SDValue Op0, SDValue Op1) const; 196 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 197 SDValue Src, SDValue MinVal, SDValue MaxVal, 198 bool Signed) const; 199 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 200 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const; 201 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const; 202 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 203 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 204 SDValue performFPRoundCombine(SDNode *N, DAGCombinerInfo &DCI) const; 205 206 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const; 207 unsigned getFusedOpcode(const SelectionDAG &DAG, 208 const SDNode *N0, const SDNode *N1) const; 209 SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const; 210 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 211 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const; 212 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 213 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 214 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 215 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const; 216 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 217 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; 218 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const; 219 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const; 220 221 bool isLegalFlatAddressingMode(const AddrMode &AM) const; 222 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 223 224 unsigned isCFIntrinsic(const SDNode *Intr) const; 225 226 public: 227 /// \returns True if fixup needs to be emitted for given global value \p GV, 228 /// false otherwise. 229 bool shouldEmitFixup(const GlobalValue *GV) const; 230 231 /// \returns True if GOT relocation needs to be emitted for given global value 232 /// \p GV, false otherwise. 233 bool shouldEmitGOTReloc(const GlobalValue *GV) const; 234 235 /// \returns True if PC-relative relocation needs to be emitted for given 236 /// global value \p GV, false otherwise. 237 bool shouldEmitPCReloc(const GlobalValue *GV) const; 238 239 /// \returns true if this should use a literal constant for an LDS address, 240 /// and not emit a relocation for an LDS global. 241 bool shouldUseLDSConstAddress(const GlobalValue *GV) const; 242 243 /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be 244 /// expanded into a set of cmp/select instructions. 245 static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, 246 bool IsDivergentIdx, 247 const GCNSubtarget *Subtarget); 248 249 bool shouldExpandVectorDynExt(SDNode *N) const; 250 251 private: 252 // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the 253 // three offsets (voffset, soffset and instoffset) into the SDValue[3] array 254 // pointed to by Offsets. 255 void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG, 256 SDValue *Offsets, Align Alignment = Align(4)) const; 257 258 // Convert the i128 that an addrspace(8) pointer is natively represented as 259 // into the v4i32 that all the buffer intrinsics expect to receive. We can't 260 // add register classes for i128 on pain of the promotion logic going haywire, 261 // so this slightly ugly hack is what we've got. If passed a non-pointer 262 // argument (as would be seen in older buffer intrinsics), does nothing. 263 SDValue bufferRsrcPtrToVector(SDValue MaybePointer, SelectionDAG &DAG) const; 264 265 // Wrap a 64-bit pointer into a v4i32 (which is how all SelectionDAG code 266 // represents ptr addrspace(8)) using the flags specified in the intrinsic. 267 SDValue lowerPointerAsRsrcIntrin(SDNode *Op, SelectionDAG &DAG) const; 268 269 // Handle 8 bit and 16 bit buffer loads 270 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL, 271 ArrayRef<SDValue> Ops, MemSDNode *M) const; 272 273 // Handle 8 bit and 16 bit buffer stores 274 SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType, 275 SDLoc DL, SDValue Ops[], 276 MemSDNode *M) const; 277 278 public: 279 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI); 280 281 const GCNSubtarget *getSubtarget() const; 282 283 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, 284 EVT SrcVT) const override; 285 286 bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy, 287 LLT SrcTy) const override; 288 289 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override; 290 291 // While address space 7 should never make it to codegen, it still needs to 292 // have a MVT to prevent some analyses that query this function from breaking, 293 // so, to work around the lack of i160, map it to v5i32. 294 MVT getPointerTy(const DataLayout &DL, unsigned AS) const override; 295 MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override; 296 297 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 298 MachineFunction &MF, 299 unsigned IntrinsicID) const override; 300 301 bool getAddrModeArguments(IntrinsicInst * /*I*/, 302 SmallVectorImpl<Value*> &/*Ops*/, 303 Type *&/*AccessTy*/) const override; 304 305 bool isLegalGlobalAddressingMode(const AddrMode &AM) const; 306 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 307 unsigned AS, 308 Instruction *I = nullptr) const override; 309 310 bool canMergeStoresTo(unsigned AS, EVT MemVT, 311 const MachineFunction &MF) const override; 312 313 bool allowsMisalignedMemoryAccessesImpl( 314 unsigned Size, unsigned AddrSpace, Align Alignment, 315 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 316 unsigned *IsFast = nullptr) const; 317 318 bool allowsMisalignedMemoryAccesses( 319 LLT Ty, unsigned AddrSpace, Align Alignment, 320 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 321 unsigned *IsFast = nullptr) const override { 322 if (IsFast) 323 *IsFast = 0; 324 return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace, 325 Alignment, Flags, IsFast); 326 } 327 328 bool allowsMisalignedMemoryAccesses( 329 EVT VT, unsigned AS, Align Alignment, 330 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 331 unsigned *IsFast = nullptr) const override; 332 333 EVT getOptimalMemOpType(const MemOp &Op, 334 const AttributeList &FuncAttributes) const override; 335 336 bool isMemOpUniform(const SDNode *N) const; 337 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; 338 339 static bool isNonGlobalAddrSpace(unsigned AS); 340 341 bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 342 343 TargetLoweringBase::LegalizeTypeAction 344 getPreferredVectorAction(MVT VT) const override; 345 346 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 347 Type *Ty) const override; 348 349 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 350 unsigned Index) const override; 351 352 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 353 354 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 355 356 unsigned combineRepeatedFPDivisors() const override { 357 // Combine multiple FDIVs with the same divisor into multiple FMULs by the 358 // reciprocal. 359 return 2; 360 } 361 362 bool supportSplitCSR(MachineFunction *MF) const override; 363 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 364 void insertCopiesSplitCSR( 365 MachineBasicBlock *Entry, 366 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 367 368 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 369 bool isVarArg, 370 const SmallVectorImpl<ISD::InputArg> &Ins, 371 const SDLoc &DL, SelectionDAG &DAG, 372 SmallVectorImpl<SDValue> &InVals) const override; 373 374 bool CanLowerReturn(CallingConv::ID CallConv, 375 MachineFunction &MF, bool isVarArg, 376 const SmallVectorImpl<ISD::OutputArg> &Outs, 377 LLVMContext &Context) const override; 378 379 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 380 const SmallVectorImpl<ISD::OutputArg> &Outs, 381 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 382 SelectionDAG &DAG) const override; 383 384 void passSpecialInputs( 385 CallLoweringInfo &CLI, 386 CCState &CCInfo, 387 const SIMachineFunctionInfo &Info, 388 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, 389 SmallVectorImpl<SDValue> &MemOpChains, 390 SDValue Chain) const; 391 392 SDValue LowerCallResult(SDValue Chain, SDValue InGlue, 393 CallingConv::ID CallConv, bool isVarArg, 394 const SmallVectorImpl<ISD::InputArg> &Ins, 395 const SDLoc &DL, SelectionDAG &DAG, 396 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 397 SDValue ThisVal) const; 398 399 bool mayBeEmittedAsTailCall(const CallInst *) const override; 400 401 bool isEligibleForTailCallOptimization( 402 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 403 const SmallVectorImpl<ISD::OutputArg> &Outs, 404 const SmallVectorImpl<SDValue> &OutVals, 405 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 406 407 SDValue LowerCall(CallLoweringInfo &CLI, 408 SmallVectorImpl<SDValue> &InVals) const override; 409 410 SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const; 411 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 412 413 Register getRegisterByName(const char* RegName, LLT VT, 414 const MachineFunction &MF) const override; 415 416 MachineBasicBlock *splitKillBlock(MachineInstr &MI, 417 MachineBasicBlock *BB) const; 418 419 void bundleInstWithWaitcnt(MachineInstr &MI) const; 420 MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI, 421 MachineBasicBlock *BB) const; 422 423 MachineBasicBlock * 424 EmitInstrWithCustomInserter(MachineInstr &MI, 425 MachineBasicBlock *BB) const override; 426 427 bool hasAtomicFaddRtnForTy(SDValue &Op) const; 428 bool enableAggressiveFMAFusion(EVT VT) const override; 429 bool enableAggressiveFMAFusion(LLT Ty) const override; 430 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 431 EVT VT) const override; 432 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 433 LLT getPreferredShiftAmountTy(LLT Ty) const override; 434 435 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 436 EVT VT) const override; 437 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 438 const LLT Ty) const override; 439 bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override; 440 bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override; 441 442 SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 443 SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 444 SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 445 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 446 447 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 448 SelectionDAG &DAG) const override; 449 450 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 451 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 452 void AddIMGInit(MachineInstr &MI) const; 453 void AdjustInstrPostInstrSelection(MachineInstr &MI, 454 SDNode *Node) const override; 455 456 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 457 458 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 459 SDValue Ptr) const; 460 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 461 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 462 std::pair<unsigned, const TargetRegisterClass *> 463 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 464 StringRef Constraint, MVT VT) const override; 465 ConstraintType getConstraintType(StringRef Constraint) const override; 466 void LowerAsmOperandForConstraint(SDValue Op, 467 std::string &Constraint, 468 std::vector<SDValue> &Ops, 469 SelectionDAG &DAG) const override; 470 bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const; 471 bool checkAsmConstraintVal(SDValue Op, 472 const std::string &Constraint, 473 uint64_t Val) const; 474 bool checkAsmConstraintValA(SDValue Op, 475 uint64_t Val, 476 unsigned MaxSize = 64) const; 477 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 478 SDValue V) const; 479 480 void finalizeLowering(MachineFunction &MF) const override; 481 482 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 483 const APInt &DemandedElts, 484 const SelectionDAG &DAG, 485 unsigned Depth = 0) const override; 486 void computeKnownBitsForFrameIndex(int FrameIdx, 487 KnownBits &Known, 488 const MachineFunction &MF) const override; 489 void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, 490 KnownBits &Known, 491 const APInt &DemandedElts, 492 const MachineRegisterInfo &MRI, 493 unsigned Depth = 0) const override; 494 495 Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, 496 const MachineRegisterInfo &MRI, 497 unsigned Depth = 0) const override; 498 bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, 499 UniformityInfo *UA) const override; 500 501 bool hasMemSDNodeUser(SDNode *N) const; 502 503 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, 504 SDValue N1) const override; 505 506 bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0, 507 Register N1) const override; 508 509 bool isCanonicalized(SelectionDAG &DAG, SDValue Op, 510 unsigned MaxDepth = 5) const; 511 bool isCanonicalized(Register Reg, MachineFunction &MF, 512 unsigned MaxDepth = 5) const; 513 bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const; 514 bool denormalsEnabledForType(LLT Ty, MachineFunction &MF) const; 515 516 bool checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, 517 const TargetRegisterInfo *TRI, 518 const TargetInstrInfo *TII, unsigned &PhysReg, 519 int &Cost) const override; 520 521 bool isKnownNeverNaNForTargetNode(SDValue Op, 522 const SelectionDAG &DAG, 523 bool SNaN = false, 524 unsigned Depth = 0) const override; 525 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override; 526 AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 527 AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 528 AtomicExpansionKind 529 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 530 void emitExpandAtomicRMW(AtomicRMWInst *AI) const override; 531 532 LoadInst * 533 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override; 534 535 const TargetRegisterClass *getRegClassFor(MVT VT, 536 bool isDivergent) const override; 537 bool requiresUniformRegister(MachineFunction &MF, 538 const Value *V) const override; 539 Align getPrefLoopAlignment(MachineLoop *ML) const override; 540 541 void allocateHSAUserSGPRs(CCState &CCInfo, 542 MachineFunction &MF, 543 const SIRegisterInfo &TRI, 544 SIMachineFunctionInfo &Info) const; 545 546 void allocateSystemSGPRs(CCState &CCInfo, 547 MachineFunction &MF, 548 SIMachineFunctionInfo &Info, 549 CallingConv::ID CallConv, 550 bool IsShader) const; 551 552 void allocateSpecialEntryInputVGPRs(CCState &CCInfo, 553 MachineFunction &MF, 554 const SIRegisterInfo &TRI, 555 SIMachineFunctionInfo &Info) const; 556 void allocateSpecialInputSGPRs( 557 CCState &CCInfo, 558 MachineFunction &MF, 559 const SIRegisterInfo &TRI, 560 SIMachineFunctionInfo &Info) const; 561 562 void allocateSpecialInputVGPRs(CCState &CCInfo, 563 MachineFunction &MF, 564 const SIRegisterInfo &TRI, 565 SIMachineFunctionInfo &Info) const; 566 void allocateSpecialInputVGPRsFixed(CCState &CCInfo, 567 MachineFunction &MF, 568 const SIRegisterInfo &TRI, 569 SIMachineFunctionInfo &Info) const; 570 571 MachineMemOperand::Flags 572 getTargetMMOFlags(const Instruction &I) const override; 573 }; 574 575 } // End namespace llvm 576 577 #endif 578