1 //===--------------------- SIFrameLowering.h --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H 10 #define LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H 11 12 #include "AMDGPUFrameLowering.h" 13 14 namespace llvm { 15 16 class SIInstrInfo; 17 class SIMachineFunctionInfo; 18 class SIRegisterInfo; 19 class GCNSubtarget; 20 21 class SIFrameLowering final : public AMDGPUFrameLowering { 22 public: 23 SIFrameLowering(StackDirection D, Align StackAl, int LAO, 24 Align TransAl = Align::None()) 25 : AMDGPUFrameLowering(D, StackAl, LAO, TransAl) {} 26 ~SIFrameLowering() override = default; 27 28 void emitEntryFunctionPrologue(MachineFunction &MF, 29 MachineBasicBlock &MBB) const; 30 void emitPrologue(MachineFunction &MF, 31 MachineBasicBlock &MBB) const override; 32 void emitEpilogue(MachineFunction &MF, 33 MachineBasicBlock &MBB) const override; 34 int getFrameIndexReference(const MachineFunction &MF, int FI, 35 unsigned &FrameReg) const override; 36 37 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, 38 RegScavenger *RS = nullptr) const override; 39 void determineCalleeSavesSGPR(MachineFunction &MF, BitVector &SavedRegs, 40 RegScavenger *RS = nullptr) const; 41 bool 42 assignCalleeSavedSpillSlots(MachineFunction &MF, 43 const TargetRegisterInfo *TRI, 44 std::vector<CalleeSavedInfo> &CSI) const override; 45 46 bool isSupportedStackID(TargetStackID::Value ID) const override; 47 48 void processFunctionBeforeFrameFinalized( 49 MachineFunction &MF, 50 RegScavenger *RS = nullptr) const override; 51 52 MachineBasicBlock::iterator 53 eliminateCallFramePseudoInstr(MachineFunction &MF, 54 MachineBasicBlock &MBB, 55 MachineBasicBlock::iterator MI) const override; 56 57 private: 58 void emitFlatScratchInit(const GCNSubtarget &ST, 59 MachineFunction &MF, 60 MachineBasicBlock &MBB) const; 61 62 unsigned getReservedPrivateSegmentBufferReg( 63 const GCNSubtarget &ST, 64 const SIInstrInfo *TII, 65 const SIRegisterInfo *TRI, 66 SIMachineFunctionInfo *MFI, 67 MachineFunction &MF) const; 68 69 std::pair<unsigned, bool> getReservedPrivateSegmentWaveByteOffsetReg( 70 const GCNSubtarget &ST, const SIInstrInfo *TII, const SIRegisterInfo *TRI, 71 SIMachineFunctionInfo *MFI, MachineFunction &MF) const; 72 73 // Emit scratch setup code for AMDPAL or Mesa, assuming ResourceRegUsed is set. 74 void emitEntryFunctionScratchSetup(const GCNSubtarget &ST, MachineFunction &MF, 75 MachineBasicBlock &MBB, SIMachineFunctionInfo *MFI, 76 MachineBasicBlock::iterator I, unsigned PreloadedPrivateBufferReg, 77 unsigned ScratchRsrcReg) const; 78 79 public: 80 bool hasFP(const MachineFunction &MF) const override; 81 }; 82 83 } // end namespace llvm 84 85 #endif // LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H 86