xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp (revision 6ba2210ee039f2f12878c217bcf058e9c8b26b29)
1 //===-- SIFoldOperands.cpp - Fold operands --- ----------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 //
10 
11 #include "AMDGPU.h"
12 #include "GCNSubtarget.h"
13 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
14 #include "SIMachineFunctionInfo.h"
15 #include "llvm/ADT/DepthFirstIterator.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
17 
18 #define DEBUG_TYPE "si-fold-operands"
19 using namespace llvm;
20 
21 namespace {
22 
23 struct FoldCandidate {
24   MachineInstr *UseMI;
25   union {
26     MachineOperand *OpToFold;
27     uint64_t ImmToFold;
28     int FrameIndexToFold;
29   };
30   int ShrinkOpcode;
31   unsigned UseOpNo;
32   MachineOperand::MachineOperandType Kind;
33   bool Commuted;
34 
35   FoldCandidate(MachineInstr *MI, unsigned OpNo, MachineOperand *FoldOp,
36                 bool Commuted_ = false,
37                 int ShrinkOp = -1) :
38     UseMI(MI), OpToFold(nullptr), ShrinkOpcode(ShrinkOp), UseOpNo(OpNo),
39     Kind(FoldOp->getType()),
40     Commuted(Commuted_) {
41     if (FoldOp->isImm()) {
42       ImmToFold = FoldOp->getImm();
43     } else if (FoldOp->isFI()) {
44       FrameIndexToFold = FoldOp->getIndex();
45     } else {
46       assert(FoldOp->isReg() || FoldOp->isGlobal());
47       OpToFold = FoldOp;
48     }
49   }
50 
51   bool isFI() const {
52     return Kind == MachineOperand::MO_FrameIndex;
53   }
54 
55   bool isImm() const {
56     return Kind == MachineOperand::MO_Immediate;
57   }
58 
59   bool isReg() const {
60     return Kind == MachineOperand::MO_Register;
61   }
62 
63   bool isGlobal() const { return Kind == MachineOperand::MO_GlobalAddress; }
64 
65   bool isCommuted() const {
66     return Commuted;
67   }
68 
69   bool needsShrink() const {
70     return ShrinkOpcode != -1;
71   }
72 
73   int getShrinkOpcode() const {
74     return ShrinkOpcode;
75   }
76 };
77 
78 class SIFoldOperands : public MachineFunctionPass {
79 public:
80   static char ID;
81   MachineRegisterInfo *MRI;
82   const SIInstrInfo *TII;
83   const SIRegisterInfo *TRI;
84   const GCNSubtarget *ST;
85   const SIMachineFunctionInfo *MFI;
86 
87   void foldOperand(MachineOperand &OpToFold,
88                    MachineInstr *UseMI,
89                    int UseOpIdx,
90                    SmallVectorImpl<FoldCandidate> &FoldList,
91                    SmallVectorImpl<MachineInstr *> &CopiesToReplace) const;
92 
93   void foldInstOperand(MachineInstr &MI, MachineOperand &OpToFold) const;
94 
95   const MachineOperand *isClamp(const MachineInstr &MI) const;
96   bool tryFoldClamp(MachineInstr &MI);
97 
98   std::pair<const MachineOperand *, int> isOMod(const MachineInstr &MI) const;
99   bool tryFoldOMod(MachineInstr &MI);
100 
101 public:
102   SIFoldOperands() : MachineFunctionPass(ID) {
103     initializeSIFoldOperandsPass(*PassRegistry::getPassRegistry());
104   }
105 
106   bool runOnMachineFunction(MachineFunction &MF) override;
107 
108   StringRef getPassName() const override { return "SI Fold Operands"; }
109 
110   void getAnalysisUsage(AnalysisUsage &AU) const override {
111     AU.setPreservesCFG();
112     MachineFunctionPass::getAnalysisUsage(AU);
113   }
114 };
115 
116 } // End anonymous namespace.
117 
118 INITIALIZE_PASS(SIFoldOperands, DEBUG_TYPE,
119                 "SI Fold Operands", false, false)
120 
121 char SIFoldOperands::ID = 0;
122 
123 char &llvm::SIFoldOperandsID = SIFoldOperands::ID;
124 
125 // Map multiply-accumulate opcode to corresponding multiply-add opcode if any.
126 static unsigned macToMad(unsigned Opc) {
127   switch (Opc) {
128   case AMDGPU::V_MAC_F32_e64:
129     return AMDGPU::V_MAD_F32_e64;
130   case AMDGPU::V_MAC_F16_e64:
131     return AMDGPU::V_MAD_F16_e64;
132   case AMDGPU::V_FMAC_F32_e64:
133     return AMDGPU::V_FMA_F32_e64;
134   case AMDGPU::V_FMAC_F16_e64:
135     return AMDGPU::V_FMA_F16_gfx9_e64;
136   case AMDGPU::V_FMAC_LEGACY_F32_e64:
137     return AMDGPU::V_FMA_LEGACY_F32_e64;
138   }
139   return AMDGPU::INSTRUCTION_LIST_END;
140 }
141 
142 // Wrapper around isInlineConstant that understands special cases when
143 // instruction types are replaced during operand folding.
144 static bool isInlineConstantIfFolded(const SIInstrInfo *TII,
145                                      const MachineInstr &UseMI,
146                                      unsigned OpNo,
147                                      const MachineOperand &OpToFold) {
148   if (TII->isInlineConstant(UseMI, OpNo, OpToFold))
149     return true;
150 
151   unsigned Opc = UseMI.getOpcode();
152   unsigned NewOpc = macToMad(Opc);
153   if (NewOpc != AMDGPU::INSTRUCTION_LIST_END) {
154     // Special case for mac. Since this is replaced with mad when folded into
155     // src2, we need to check the legality for the final instruction.
156     int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
157     if (static_cast<int>(OpNo) == Src2Idx) {
158       const MCInstrDesc &MadDesc = TII->get(NewOpc);
159       return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType);
160     }
161   }
162 
163   return false;
164 }
165 
166 // TODO: Add heuristic that the frame index might not fit in the addressing mode
167 // immediate offset to avoid materializing in loops.
168 static bool frameIndexMayFold(const SIInstrInfo *TII,
169                               const MachineInstr &UseMI,
170                               int OpNo,
171                               const MachineOperand &OpToFold) {
172   if (!OpToFold.isFI())
173     return false;
174 
175   if (TII->isMUBUF(UseMI))
176     return OpNo == AMDGPU::getNamedOperandIdx(UseMI.getOpcode(),
177                                               AMDGPU::OpName::vaddr);
178   if (!TII->isFLATScratch(UseMI))
179     return false;
180 
181   int SIdx = AMDGPU::getNamedOperandIdx(UseMI.getOpcode(),
182                                         AMDGPU::OpName::saddr);
183   if (OpNo == SIdx)
184     return true;
185 
186   int VIdx = AMDGPU::getNamedOperandIdx(UseMI.getOpcode(),
187                                         AMDGPU::OpName::vaddr);
188   return OpNo == VIdx && SIdx == -1;
189 }
190 
191 FunctionPass *llvm::createSIFoldOperandsPass() {
192   return new SIFoldOperands();
193 }
194 
195 static bool updateOperand(FoldCandidate &Fold,
196                           const SIInstrInfo &TII,
197                           const TargetRegisterInfo &TRI,
198                           const GCNSubtarget &ST) {
199   MachineInstr *MI = Fold.UseMI;
200   MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
201   assert(Old.isReg());
202 
203   if (Fold.isImm()) {
204     if (MI->getDesc().TSFlags & SIInstrFlags::IsPacked &&
205         !(MI->getDesc().TSFlags & SIInstrFlags::IsMAI) &&
206         AMDGPU::isFoldableLiteralV216(Fold.ImmToFold,
207                                       ST.hasInv2PiInlineImm())) {
208       // Set op_sel/op_sel_hi on this operand or bail out if op_sel is
209       // already set.
210       unsigned Opcode = MI->getOpcode();
211       int OpNo = MI->getOperandNo(&Old);
212       int ModIdx = -1;
213       if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0))
214         ModIdx = AMDGPU::OpName::src0_modifiers;
215       else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1))
216         ModIdx = AMDGPU::OpName::src1_modifiers;
217       else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2))
218         ModIdx = AMDGPU::OpName::src2_modifiers;
219       assert(ModIdx != -1);
220       ModIdx = AMDGPU::getNamedOperandIdx(Opcode, ModIdx);
221       MachineOperand &Mod = MI->getOperand(ModIdx);
222       unsigned Val = Mod.getImm();
223       if (!(Val & SISrcMods::OP_SEL_0) && (Val & SISrcMods::OP_SEL_1)) {
224         // Only apply the following transformation if that operand requries
225         // a packed immediate.
226         switch (TII.get(Opcode).OpInfo[OpNo].OperandType) {
227         case AMDGPU::OPERAND_REG_IMM_V2FP16:
228         case AMDGPU::OPERAND_REG_IMM_V2INT16:
229         case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
230         case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
231           // If upper part is all zero we do not need op_sel_hi.
232           if (!isUInt<16>(Fold.ImmToFold)) {
233             if (!(Fold.ImmToFold & 0xffff)) {
234               Mod.setImm(Mod.getImm() | SISrcMods::OP_SEL_0);
235               Mod.setImm(Mod.getImm() & ~SISrcMods::OP_SEL_1);
236               Old.ChangeToImmediate((Fold.ImmToFold >> 16) & 0xffff);
237               return true;
238             }
239             Mod.setImm(Mod.getImm() & ~SISrcMods::OP_SEL_1);
240             Old.ChangeToImmediate(Fold.ImmToFold & 0xffff);
241             return true;
242           }
243           break;
244         default:
245           break;
246         }
247       }
248     }
249   }
250 
251   if ((Fold.isImm() || Fold.isFI() || Fold.isGlobal()) && Fold.needsShrink()) {
252     MachineBasicBlock *MBB = MI->getParent();
253     auto Liveness = MBB->computeRegisterLiveness(&TRI, AMDGPU::VCC, MI, 16);
254     if (Liveness != MachineBasicBlock::LQR_Dead) {
255       LLVM_DEBUG(dbgs() << "Not shrinking " << MI << " due to vcc liveness\n");
256       return false;
257     }
258 
259     MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
260     int Op32 = Fold.getShrinkOpcode();
261     MachineOperand &Dst0 = MI->getOperand(0);
262     MachineOperand &Dst1 = MI->getOperand(1);
263     assert(Dst0.isDef() && Dst1.isDef());
264 
265     bool HaveNonDbgCarryUse = !MRI.use_nodbg_empty(Dst1.getReg());
266 
267     const TargetRegisterClass *Dst0RC = MRI.getRegClass(Dst0.getReg());
268     Register NewReg0 = MRI.createVirtualRegister(Dst0RC);
269 
270     MachineInstr *Inst32 = TII.buildShrunkInst(*MI, Op32);
271 
272     if (HaveNonDbgCarryUse) {
273       BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), Dst1.getReg())
274         .addReg(AMDGPU::VCC, RegState::Kill);
275     }
276 
277     // Keep the old instruction around to avoid breaking iterators, but
278     // replace it with a dummy instruction to remove uses.
279     //
280     // FIXME: We should not invert how this pass looks at operands to avoid
281     // this. Should track set of foldable movs instead of looking for uses
282     // when looking at a use.
283     Dst0.setReg(NewReg0);
284     for (unsigned I = MI->getNumOperands() - 1; I > 0; --I)
285       MI->RemoveOperand(I);
286     MI->setDesc(TII.get(AMDGPU::IMPLICIT_DEF));
287 
288     if (Fold.isCommuted())
289       TII.commuteInstruction(*Inst32, false);
290     return true;
291   }
292 
293   assert(!Fold.needsShrink() && "not handled");
294 
295   if (Fold.isImm()) {
296     Old.ChangeToImmediate(Fold.ImmToFold);
297     return true;
298   }
299 
300   if (Fold.isGlobal()) {
301     Old.ChangeToGA(Fold.OpToFold->getGlobal(), Fold.OpToFold->getOffset(),
302                    Fold.OpToFold->getTargetFlags());
303     return true;
304   }
305 
306   if (Fold.isFI()) {
307     Old.ChangeToFrameIndex(Fold.FrameIndexToFold);
308     return true;
309   }
310 
311   MachineOperand *New = Fold.OpToFold;
312   Old.substVirtReg(New->getReg(), New->getSubReg(), TRI);
313   Old.setIsUndef(New->isUndef());
314   return true;
315 }
316 
317 static bool isUseMIInFoldList(ArrayRef<FoldCandidate> FoldList,
318                               const MachineInstr *MI) {
319   for (auto Candidate : FoldList) {
320     if (Candidate.UseMI == MI)
321       return true;
322   }
323   return false;
324 }
325 
326 static void appendFoldCandidate(SmallVectorImpl<FoldCandidate> &FoldList,
327                                 MachineInstr *MI, unsigned OpNo,
328                                 MachineOperand *FoldOp, bool Commuted = false,
329                                 int ShrinkOp = -1) {
330   // Skip additional folding on the same operand.
331   for (FoldCandidate &Fold : FoldList)
332     if (Fold.UseMI == MI && Fold.UseOpNo == OpNo)
333       return;
334   LLVM_DEBUG(dbgs() << "Append " << (Commuted ? "commuted" : "normal")
335                     << " operand " << OpNo << "\n  " << *MI << '\n');
336   FoldList.push_back(FoldCandidate(MI, OpNo, FoldOp, Commuted, ShrinkOp));
337 }
338 
339 static bool tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
340                              MachineInstr *MI, unsigned OpNo,
341                              MachineOperand *OpToFold,
342                              const SIInstrInfo *TII) {
343   if (!TII->isOperandLegal(*MI, OpNo, OpToFold)) {
344     // Special case for v_mac_{f16, f32}_e64 if we are trying to fold into src2
345     unsigned Opc = MI->getOpcode();
346     unsigned NewOpc = macToMad(Opc);
347     if (NewOpc != AMDGPU::INSTRUCTION_LIST_END) {
348       // Check if changing this to a v_mad_{f16, f32} instruction will allow us
349       // to fold the operand.
350       MI->setDesc(TII->get(NewOpc));
351       bool FoldAsMAD = tryAddToFoldList(FoldList, MI, OpNo, OpToFold, TII);
352       if (FoldAsMAD) {
353         MI->untieRegOperand(OpNo);
354         return true;
355       }
356       MI->setDesc(TII->get(Opc));
357     }
358 
359     // Special case for s_setreg_b32
360     if (OpToFold->isImm()) {
361       unsigned ImmOpc = 0;
362       if (Opc == AMDGPU::S_SETREG_B32)
363         ImmOpc = AMDGPU::S_SETREG_IMM32_B32;
364       else if (Opc == AMDGPU::S_SETREG_B32_mode)
365         ImmOpc = AMDGPU::S_SETREG_IMM32_B32_mode;
366       if (ImmOpc) {
367         MI->setDesc(TII->get(ImmOpc));
368         appendFoldCandidate(FoldList, MI, OpNo, OpToFold);
369         return true;
370       }
371     }
372 
373     // If we are already folding into another operand of MI, then
374     // we can't commute the instruction, otherwise we risk making the
375     // other fold illegal.
376     if (isUseMIInFoldList(FoldList, MI))
377       return false;
378 
379     unsigned CommuteOpNo = OpNo;
380 
381     // Operand is not legal, so try to commute the instruction to
382     // see if this makes it possible to fold.
383     unsigned CommuteIdx0 = TargetInstrInfo::CommuteAnyOperandIndex;
384     unsigned CommuteIdx1 = TargetInstrInfo::CommuteAnyOperandIndex;
385     bool CanCommute = TII->findCommutedOpIndices(*MI, CommuteIdx0, CommuteIdx1);
386 
387     if (CanCommute) {
388       if (CommuteIdx0 == OpNo)
389         CommuteOpNo = CommuteIdx1;
390       else if (CommuteIdx1 == OpNo)
391         CommuteOpNo = CommuteIdx0;
392     }
393 
394 
395     // One of operands might be an Imm operand, and OpNo may refer to it after
396     // the call of commuteInstruction() below. Such situations are avoided
397     // here explicitly as OpNo must be a register operand to be a candidate
398     // for memory folding.
399     if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() ||
400                        !MI->getOperand(CommuteIdx1).isReg()))
401       return false;
402 
403     if (!CanCommute ||
404         !TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1))
405       return false;
406 
407     if (!TII->isOperandLegal(*MI, CommuteOpNo, OpToFold)) {
408       if ((Opc == AMDGPU::V_ADD_CO_U32_e64 ||
409            Opc == AMDGPU::V_SUB_CO_U32_e64 ||
410            Opc == AMDGPU::V_SUBREV_CO_U32_e64) && // FIXME
411           (OpToFold->isImm() || OpToFold->isFI() || OpToFold->isGlobal())) {
412         MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
413 
414         // Verify the other operand is a VGPR, otherwise we would violate the
415         // constant bus restriction.
416         unsigned OtherIdx = CommuteOpNo == CommuteIdx0 ? CommuteIdx1 : CommuteIdx0;
417         MachineOperand &OtherOp = MI->getOperand(OtherIdx);
418         if (!OtherOp.isReg() ||
419             !TII->getRegisterInfo().isVGPR(MRI, OtherOp.getReg()))
420           return false;
421 
422         assert(MI->getOperand(1).isDef());
423 
424         // Make sure to get the 32-bit version of the commuted opcode.
425         unsigned MaybeCommutedOpc = MI->getOpcode();
426         int Op32 = AMDGPU::getVOPe32(MaybeCommutedOpc);
427 
428         appendFoldCandidate(FoldList, MI, CommuteOpNo, OpToFold, true, Op32);
429         return true;
430       }
431 
432       TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1);
433       return false;
434     }
435 
436     appendFoldCandidate(FoldList, MI, CommuteOpNo, OpToFold, true);
437     return true;
438   }
439 
440   // Check the case where we might introduce a second constant operand to a
441   // scalar instruction
442   if (TII->isSALU(MI->getOpcode())) {
443     const MCInstrDesc &InstDesc = MI->getDesc();
444     const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];
445     const SIRegisterInfo &SRI = TII->getRegisterInfo();
446 
447     // Fine if the operand can be encoded as an inline constant
448     if (OpToFold->isImm()) {
449       if (!SRI.opCanUseInlineConstant(OpInfo.OperandType) ||
450           !TII->isInlineConstant(*OpToFold, OpInfo)) {
451         // Otherwise check for another constant
452         for (unsigned i = 0, e = InstDesc.getNumOperands(); i != e; ++i) {
453           auto &Op = MI->getOperand(i);
454           if (OpNo != i &&
455               TII->isLiteralConstantLike(Op, OpInfo)) {
456             return false;
457           }
458         }
459       }
460     }
461   }
462 
463   appendFoldCandidate(FoldList, MI, OpNo, OpToFold);
464   return true;
465 }
466 
467 // If the use operand doesn't care about the value, this may be an operand only
468 // used for register indexing, in which case it is unsafe to fold.
469 static bool isUseSafeToFold(const SIInstrInfo *TII,
470                             const MachineInstr &MI,
471                             const MachineOperand &UseMO) {
472   if (UseMO.isUndef() || TII->isSDWA(MI))
473     return false;
474 
475   switch (MI.getOpcode()) {
476   case AMDGPU::V_MOV_B32_e32:
477   case AMDGPU::V_MOV_B32_e64:
478   case AMDGPU::V_MOV_B64_PSEUDO:
479     // Do not fold into an indirect mov.
480     return !MI.hasRegisterImplicitUseOperand(AMDGPU::M0);
481   }
482 
483   return true;
484   //return !MI.hasRegisterImplicitUseOperand(UseMO.getReg());
485 }
486 
487 // Find a def of the UseReg, check if it is a reg_seqence and find initializers
488 // for each subreg, tracking it to foldable inline immediate if possible.
489 // Returns true on success.
490 static bool getRegSeqInit(
491     SmallVectorImpl<std::pair<MachineOperand*, unsigned>> &Defs,
492     Register UseReg, uint8_t OpTy,
493     const SIInstrInfo *TII, const MachineRegisterInfo &MRI) {
494   MachineInstr *Def = MRI.getUniqueVRegDef(UseReg);
495   if (!Def || !Def->isRegSequence())
496     return false;
497 
498   for (unsigned I = 1, E = Def->getNumExplicitOperands(); I < E; I += 2) {
499     MachineOperand *Sub = &Def->getOperand(I);
500     assert (Sub->isReg());
501 
502     for (MachineInstr *SubDef = MRI.getUniqueVRegDef(Sub->getReg());
503          SubDef && Sub->isReg() && !Sub->getSubReg() &&
504          TII->isFoldableCopy(*SubDef);
505          SubDef = MRI.getUniqueVRegDef(Sub->getReg())) {
506       MachineOperand *Op = &SubDef->getOperand(1);
507       if (Op->isImm()) {
508         if (TII->isInlineConstant(*Op, OpTy))
509           Sub = Op;
510         break;
511       }
512       if (!Op->isReg())
513         break;
514       Sub = Op;
515     }
516 
517     Defs.push_back(std::make_pair(Sub, Def->getOperand(I + 1).getImm()));
518   }
519 
520   return true;
521 }
522 
523 static bool tryToFoldACImm(const SIInstrInfo *TII,
524                            const MachineOperand &OpToFold,
525                            MachineInstr *UseMI,
526                            unsigned UseOpIdx,
527                            SmallVectorImpl<FoldCandidate> &FoldList) {
528   const MCInstrDesc &Desc = UseMI->getDesc();
529   const MCOperandInfo *OpInfo = Desc.OpInfo;
530   if (!OpInfo || UseOpIdx >= Desc.getNumOperands())
531     return false;
532 
533   uint8_t OpTy = OpInfo[UseOpIdx].OperandType;
534   if (OpTy < AMDGPU::OPERAND_REG_INLINE_AC_FIRST ||
535       OpTy > AMDGPU::OPERAND_REG_INLINE_AC_LAST)
536     return false;
537 
538   if (OpToFold.isImm() && TII->isInlineConstant(OpToFold, OpTy) &&
539       TII->isOperandLegal(*UseMI, UseOpIdx, &OpToFold)) {
540     UseMI->getOperand(UseOpIdx).ChangeToImmediate(OpToFold.getImm());
541     return true;
542   }
543 
544   if (!OpToFold.isReg())
545     return false;
546 
547   Register UseReg = OpToFold.getReg();
548   if (!UseReg.isVirtual())
549     return false;
550 
551   if (llvm::any_of(FoldList, [UseMI](const FoldCandidate &FC) {
552         return FC.UseMI == UseMI;
553       }))
554     return false;
555 
556   MachineRegisterInfo &MRI = UseMI->getParent()->getParent()->getRegInfo();
557   SmallVector<std::pair<MachineOperand*, unsigned>, 32> Defs;
558   if (!getRegSeqInit(Defs, UseReg, OpTy, TII, MRI))
559     return false;
560 
561   int32_t Imm;
562   for (unsigned I = 0, E = Defs.size(); I != E; ++I) {
563     const MachineOperand *Op = Defs[I].first;
564     if (!Op->isImm())
565       return false;
566 
567     auto SubImm = Op->getImm();
568     if (!I) {
569       Imm = SubImm;
570       if (!TII->isInlineConstant(*Op, OpTy) ||
571           !TII->isOperandLegal(*UseMI, UseOpIdx, Op))
572         return false;
573 
574       continue;
575     }
576     if (Imm != SubImm)
577       return false; // Can only fold splat constants
578   }
579 
580   appendFoldCandidate(FoldList, UseMI, UseOpIdx, Defs[0].first);
581   return true;
582 }
583 
584 void SIFoldOperands::foldOperand(
585   MachineOperand &OpToFold,
586   MachineInstr *UseMI,
587   int UseOpIdx,
588   SmallVectorImpl<FoldCandidate> &FoldList,
589   SmallVectorImpl<MachineInstr *> &CopiesToReplace) const {
590   const MachineOperand &UseOp = UseMI->getOperand(UseOpIdx);
591 
592   if (!isUseSafeToFold(TII, *UseMI, UseOp))
593     return;
594 
595   // FIXME: Fold operands with subregs.
596   if (UseOp.isReg() && OpToFold.isReg()) {
597     if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister)
598       return;
599   }
600 
601   // Special case for REG_SEQUENCE: We can't fold literals into
602   // REG_SEQUENCE instructions, so we have to fold them into the
603   // uses of REG_SEQUENCE.
604   if (UseMI->isRegSequence()) {
605     Register RegSeqDstReg = UseMI->getOperand(0).getReg();
606     unsigned RegSeqDstSubReg = UseMI->getOperand(UseOpIdx + 1).getImm();
607 
608     MachineRegisterInfo::use_nodbg_iterator Next;
609     for (MachineRegisterInfo::use_nodbg_iterator
610            RSUse = MRI->use_nodbg_begin(RegSeqDstReg), RSE = MRI->use_nodbg_end();
611          RSUse != RSE; RSUse = Next) {
612       Next = std::next(RSUse);
613 
614       MachineInstr *RSUseMI = RSUse->getParent();
615 
616       if (tryToFoldACImm(TII, UseMI->getOperand(0), RSUseMI,
617                          RSUse.getOperandNo(), FoldList))
618         continue;
619 
620       if (RSUse->getSubReg() != RegSeqDstSubReg)
621         continue;
622 
623       foldOperand(OpToFold, RSUseMI, RSUse.getOperandNo(), FoldList,
624                   CopiesToReplace);
625     }
626 
627     return;
628   }
629 
630   if (tryToFoldACImm(TII, OpToFold, UseMI, UseOpIdx, FoldList))
631     return;
632 
633   if (frameIndexMayFold(TII, *UseMI, UseOpIdx, OpToFold)) {
634     // Sanity check that this is a stack access.
635     // FIXME: Should probably use stack pseudos before frame lowering.
636 
637     if (TII->isMUBUF(*UseMI)) {
638       if (TII->getNamedOperand(*UseMI, AMDGPU::OpName::srsrc)->getReg() !=
639           MFI->getScratchRSrcReg())
640         return;
641 
642       // Ensure this is either relative to the current frame or the current
643       // wave.
644       MachineOperand &SOff =
645           *TII->getNamedOperand(*UseMI, AMDGPU::OpName::soffset);
646       if (!SOff.isImm() || SOff.getImm() != 0)
647         return;
648     }
649 
650     // A frame index will resolve to a positive constant, so it should always be
651     // safe to fold the addressing mode, even pre-GFX9.
652     UseMI->getOperand(UseOpIdx).ChangeToFrameIndex(OpToFold.getIndex());
653 
654     if (TII->isFLATScratch(*UseMI) &&
655         AMDGPU::getNamedOperandIdx(UseMI->getOpcode(),
656                                    AMDGPU::OpName::vaddr) != -1) {
657       unsigned NewOpc = AMDGPU::getFlatScratchInstSSfromSV(UseMI->getOpcode());
658       UseMI->setDesc(TII->get(NewOpc));
659     }
660 
661     return;
662   }
663 
664   bool FoldingImmLike =
665       OpToFold.isImm() || OpToFold.isFI() || OpToFold.isGlobal();
666 
667   if (FoldingImmLike && UseMI->isCopy()) {
668     Register DestReg = UseMI->getOperand(0).getReg();
669     Register SrcReg = UseMI->getOperand(1).getReg();
670     assert(SrcReg.isVirtual());
671 
672     const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcReg);
673 
674     // Don't fold into a copy to a physical register with the same class. Doing
675     // so would interfere with the register coalescer's logic which would avoid
676     // redundant initalizations.
677     if (DestReg.isPhysical() && SrcRC->contains(DestReg))
678       return;
679 
680     const TargetRegisterClass *DestRC = TRI->getRegClassForReg(*MRI, DestReg);
681     if (!DestReg.isPhysical()) {
682       if (TRI->isSGPRClass(SrcRC) && TRI->hasVectorRegisters(DestRC)) {
683         MachineRegisterInfo::use_nodbg_iterator NextUse;
684         SmallVector<FoldCandidate, 4> CopyUses;
685         for (MachineRegisterInfo::use_nodbg_iterator Use = MRI->use_nodbg_begin(DestReg),
686                E = MRI->use_nodbg_end();
687              Use != E; Use = NextUse) {
688           NextUse = std::next(Use);
689           // There's no point trying to fold into an implicit operand.
690           if (Use->isImplicit())
691             continue;
692 
693           FoldCandidate FC = FoldCandidate(Use->getParent(), Use.getOperandNo(),
694                                            &UseMI->getOperand(1));
695           CopyUses.push_back(FC);
696         }
697         for (auto &F : CopyUses) {
698           foldOperand(*F.OpToFold, F.UseMI, F.UseOpNo, FoldList, CopiesToReplace);
699         }
700       }
701 
702       if (DestRC == &AMDGPU::AGPR_32RegClass &&
703           TII->isInlineConstant(OpToFold, AMDGPU::OPERAND_REG_INLINE_C_INT32)) {
704         UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64));
705         UseMI->getOperand(1).ChangeToImmediate(OpToFold.getImm());
706         CopiesToReplace.push_back(UseMI);
707         return;
708       }
709     }
710 
711     // In order to fold immediates into copies, we need to change the
712     // copy to a MOV.
713 
714     unsigned MovOp = TII->getMovOpcode(DestRC);
715     if (MovOp == AMDGPU::COPY)
716       return;
717 
718     UseMI->setDesc(TII->get(MovOp));
719     MachineInstr::mop_iterator ImpOpI = UseMI->implicit_operands().begin();
720     MachineInstr::mop_iterator ImpOpE = UseMI->implicit_operands().end();
721     while (ImpOpI != ImpOpE) {
722       MachineInstr::mop_iterator Tmp = ImpOpI;
723       ImpOpI++;
724       UseMI->RemoveOperand(UseMI->getOperandNo(Tmp));
725     }
726     CopiesToReplace.push_back(UseMI);
727   } else {
728     if (UseMI->isCopy() && OpToFold.isReg() &&
729         UseMI->getOperand(0).getReg().isVirtual() &&
730         !UseMI->getOperand(1).getSubReg()) {
731       LLVM_DEBUG(dbgs() << "Folding " << OpToFold
732                         << "\n into " << *UseMI << '\n');
733       unsigned Size = TII->getOpSize(*UseMI, 1);
734       Register UseReg = OpToFold.getReg();
735       UseMI->getOperand(1).setReg(UseReg);
736       UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
737       UseMI->getOperand(1).setIsKill(false);
738       CopiesToReplace.push_back(UseMI);
739       OpToFold.setIsKill(false);
740 
741       // That is very tricky to store a value into an AGPR. v_accvgpr_write_b32
742       // can only accept VGPR or inline immediate. Recreate a reg_sequence with
743       // its initializers right here, so we will rematerialize immediates and
744       // avoid copies via different reg classes.
745       SmallVector<std::pair<MachineOperand*, unsigned>, 32> Defs;
746       if (Size > 4 && TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg()) &&
747           getRegSeqInit(Defs, UseReg, AMDGPU::OPERAND_REG_INLINE_C_INT32, TII,
748                         *MRI)) {
749         const DebugLoc &DL = UseMI->getDebugLoc();
750         MachineBasicBlock &MBB = *UseMI->getParent();
751 
752         UseMI->setDesc(TII->get(AMDGPU::REG_SEQUENCE));
753         for (unsigned I = UseMI->getNumOperands() - 1; I > 0; --I)
754           UseMI->RemoveOperand(I);
755 
756         MachineInstrBuilder B(*MBB.getParent(), UseMI);
757         DenseMap<TargetInstrInfo::RegSubRegPair, Register> VGPRCopies;
758         SmallSetVector<TargetInstrInfo::RegSubRegPair, 32> SeenAGPRs;
759         for (unsigned I = 0; I < Size / 4; ++I) {
760           MachineOperand *Def = Defs[I].first;
761           TargetInstrInfo::RegSubRegPair CopyToVGPR;
762           if (Def->isImm() &&
763               TII->isInlineConstant(*Def, AMDGPU::OPERAND_REG_INLINE_C_INT32)) {
764             int64_t Imm = Def->getImm();
765 
766             auto Tmp = MRI->createVirtualRegister(&AMDGPU::AGPR_32RegClass);
767             BuildMI(MBB, UseMI, DL,
768                     TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), Tmp).addImm(Imm);
769             B.addReg(Tmp);
770           } else if (Def->isReg() && TRI->isAGPR(*MRI, Def->getReg())) {
771             auto Src = getRegSubRegPair(*Def);
772             Def->setIsKill(false);
773             if (!SeenAGPRs.insert(Src)) {
774               // We cannot build a reg_sequence out of the same registers, they
775               // must be copied. Better do it here before copyPhysReg() created
776               // several reads to do the AGPR->VGPR->AGPR copy.
777               CopyToVGPR = Src;
778             } else {
779               B.addReg(Src.Reg, Def->isUndef() ? RegState::Undef : 0,
780                        Src.SubReg);
781             }
782           } else {
783             assert(Def->isReg());
784             Def->setIsKill(false);
785             auto Src = getRegSubRegPair(*Def);
786 
787             // Direct copy from SGPR to AGPR is not possible. To avoid creation
788             // of exploded copies SGPR->VGPR->AGPR in the copyPhysReg() later,
789             // create a copy here and track if we already have such a copy.
790             if (TRI->isSGPRReg(*MRI, Src.Reg)) {
791               CopyToVGPR = Src;
792             } else {
793               auto Tmp = MRI->createVirtualRegister(&AMDGPU::AGPR_32RegClass);
794               BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Tmp).add(*Def);
795               B.addReg(Tmp);
796             }
797           }
798 
799           if (CopyToVGPR.Reg) {
800             Register Vgpr;
801             if (VGPRCopies.count(CopyToVGPR)) {
802               Vgpr = VGPRCopies[CopyToVGPR];
803             } else {
804               Vgpr = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
805               BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Vgpr).add(*Def);
806               VGPRCopies[CopyToVGPR] = Vgpr;
807             }
808             auto Tmp = MRI->createVirtualRegister(&AMDGPU::AGPR_32RegClass);
809             BuildMI(MBB, UseMI, DL,
810                     TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), Tmp).addReg(Vgpr);
811             B.addReg(Tmp);
812           }
813 
814           B.addImm(Defs[I].second);
815         }
816         LLVM_DEBUG(dbgs() << "Folded " << *UseMI << '\n');
817         return;
818       }
819 
820       if (Size != 4)
821         return;
822       if (TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg()) &&
823           TRI->isVGPR(*MRI, UseMI->getOperand(1).getReg()))
824         UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64));
825       else if (TRI->isVGPR(*MRI, UseMI->getOperand(0).getReg()) &&
826                TRI->isAGPR(*MRI, UseMI->getOperand(1).getReg()))
827         UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_READ_B32_e64));
828       return;
829     }
830 
831     unsigned UseOpc = UseMI->getOpcode();
832     if (UseOpc == AMDGPU::V_READFIRSTLANE_B32 ||
833         (UseOpc == AMDGPU::V_READLANE_B32 &&
834          (int)UseOpIdx ==
835          AMDGPU::getNamedOperandIdx(UseOpc, AMDGPU::OpName::src0))) {
836       // %vgpr = V_MOV_B32 imm
837       // %sgpr = V_READFIRSTLANE_B32 %vgpr
838       // =>
839       // %sgpr = S_MOV_B32 imm
840       if (FoldingImmLike) {
841         if (execMayBeModifiedBeforeUse(*MRI,
842                                        UseMI->getOperand(UseOpIdx).getReg(),
843                                        *OpToFold.getParent(),
844                                        *UseMI))
845           return;
846 
847         UseMI->setDesc(TII->get(AMDGPU::S_MOV_B32));
848 
849         if (OpToFold.isImm())
850           UseMI->getOperand(1).ChangeToImmediate(OpToFold.getImm());
851         else
852           UseMI->getOperand(1).ChangeToFrameIndex(OpToFold.getIndex());
853         UseMI->RemoveOperand(2); // Remove exec read (or src1 for readlane)
854         return;
855       }
856 
857       if (OpToFold.isReg() && TRI->isSGPRReg(*MRI, OpToFold.getReg())) {
858         if (execMayBeModifiedBeforeUse(*MRI,
859                                        UseMI->getOperand(UseOpIdx).getReg(),
860                                        *OpToFold.getParent(),
861                                        *UseMI))
862           return;
863 
864         // %vgpr = COPY %sgpr0
865         // %sgpr1 = V_READFIRSTLANE_B32 %vgpr
866         // =>
867         // %sgpr1 = COPY %sgpr0
868         UseMI->setDesc(TII->get(AMDGPU::COPY));
869         UseMI->getOperand(1).setReg(OpToFold.getReg());
870         UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
871         UseMI->getOperand(1).setIsKill(false);
872         UseMI->RemoveOperand(2); // Remove exec read (or src1 for readlane)
873         return;
874       }
875     }
876 
877     const MCInstrDesc &UseDesc = UseMI->getDesc();
878 
879     // Don't fold into target independent nodes.  Target independent opcodes
880     // don't have defined register classes.
881     if (UseDesc.isVariadic() ||
882         UseOp.isImplicit() ||
883         UseDesc.OpInfo[UseOpIdx].RegClass == -1)
884       return;
885   }
886 
887   if (!FoldingImmLike) {
888     tryAddToFoldList(FoldList, UseMI, UseOpIdx, &OpToFold, TII);
889 
890     // FIXME: We could try to change the instruction from 64-bit to 32-bit
891     // to enable more folding opportunites.  The shrink operands pass
892     // already does this.
893     return;
894   }
895 
896 
897   const MCInstrDesc &FoldDesc = OpToFold.getParent()->getDesc();
898   const TargetRegisterClass *FoldRC =
899     TRI->getRegClass(FoldDesc.OpInfo[0].RegClass);
900 
901   // Split 64-bit constants into 32-bits for folding.
902   if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) {
903     Register UseReg = UseOp.getReg();
904     const TargetRegisterClass *UseRC = MRI->getRegClass(UseReg);
905 
906     if (AMDGPU::getRegBitWidth(UseRC->getID()) != 64)
907       return;
908 
909     APInt Imm(64, OpToFold.getImm());
910     if (UseOp.getSubReg() == AMDGPU::sub0) {
911       Imm = Imm.getLoBits(32);
912     } else {
913       assert(UseOp.getSubReg() == AMDGPU::sub1);
914       Imm = Imm.getHiBits(32);
915     }
916 
917     MachineOperand ImmOp = MachineOperand::CreateImm(Imm.getSExtValue());
918     tryAddToFoldList(FoldList, UseMI, UseOpIdx, &ImmOp, TII);
919     return;
920   }
921 
922 
923 
924   tryAddToFoldList(FoldList, UseMI, UseOpIdx, &OpToFold, TII);
925 }
926 
927 static bool evalBinaryInstruction(unsigned Opcode, int32_t &Result,
928                                   uint32_t LHS, uint32_t RHS) {
929   switch (Opcode) {
930   case AMDGPU::V_AND_B32_e64:
931   case AMDGPU::V_AND_B32_e32:
932   case AMDGPU::S_AND_B32:
933     Result = LHS & RHS;
934     return true;
935   case AMDGPU::V_OR_B32_e64:
936   case AMDGPU::V_OR_B32_e32:
937   case AMDGPU::S_OR_B32:
938     Result = LHS | RHS;
939     return true;
940   case AMDGPU::V_XOR_B32_e64:
941   case AMDGPU::V_XOR_B32_e32:
942   case AMDGPU::S_XOR_B32:
943     Result = LHS ^ RHS;
944     return true;
945   case AMDGPU::S_XNOR_B32:
946     Result = ~(LHS ^ RHS);
947     return true;
948   case AMDGPU::S_NAND_B32:
949     Result = ~(LHS & RHS);
950     return true;
951   case AMDGPU::S_NOR_B32:
952     Result = ~(LHS | RHS);
953     return true;
954   case AMDGPU::S_ANDN2_B32:
955     Result = LHS & ~RHS;
956     return true;
957   case AMDGPU::S_ORN2_B32:
958     Result = LHS | ~RHS;
959     return true;
960   case AMDGPU::V_LSHL_B32_e64:
961   case AMDGPU::V_LSHL_B32_e32:
962   case AMDGPU::S_LSHL_B32:
963     // The instruction ignores the high bits for out of bounds shifts.
964     Result = LHS << (RHS & 31);
965     return true;
966   case AMDGPU::V_LSHLREV_B32_e64:
967   case AMDGPU::V_LSHLREV_B32_e32:
968     Result = RHS << (LHS & 31);
969     return true;
970   case AMDGPU::V_LSHR_B32_e64:
971   case AMDGPU::V_LSHR_B32_e32:
972   case AMDGPU::S_LSHR_B32:
973     Result = LHS >> (RHS & 31);
974     return true;
975   case AMDGPU::V_LSHRREV_B32_e64:
976   case AMDGPU::V_LSHRREV_B32_e32:
977     Result = RHS >> (LHS & 31);
978     return true;
979   case AMDGPU::V_ASHR_I32_e64:
980   case AMDGPU::V_ASHR_I32_e32:
981   case AMDGPU::S_ASHR_I32:
982     Result = static_cast<int32_t>(LHS) >> (RHS & 31);
983     return true;
984   case AMDGPU::V_ASHRREV_I32_e64:
985   case AMDGPU::V_ASHRREV_I32_e32:
986     Result = static_cast<int32_t>(RHS) >> (LHS & 31);
987     return true;
988   default:
989     return false;
990   }
991 }
992 
993 static unsigned getMovOpc(bool IsScalar) {
994   return IsScalar ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
995 }
996 
997 /// Remove any leftover implicit operands from mutating the instruction. e.g.
998 /// if we replace an s_and_b32 with a copy, we don't need the implicit scc def
999 /// anymore.
1000 static void stripExtraCopyOperands(MachineInstr &MI) {
1001   const MCInstrDesc &Desc = MI.getDesc();
1002   unsigned NumOps = Desc.getNumOperands() +
1003                     Desc.getNumImplicitUses() +
1004                     Desc.getNumImplicitDefs();
1005 
1006   for (unsigned I = MI.getNumOperands() - 1; I >= NumOps; --I)
1007     MI.RemoveOperand(I);
1008 }
1009 
1010 static void mutateCopyOp(MachineInstr &MI, const MCInstrDesc &NewDesc) {
1011   MI.setDesc(NewDesc);
1012   stripExtraCopyOperands(MI);
1013 }
1014 
1015 static MachineOperand *getImmOrMaterializedImm(MachineRegisterInfo &MRI,
1016                                                MachineOperand &Op) {
1017   if (Op.isReg()) {
1018     // If this has a subregister, it obviously is a register source.
1019     if (Op.getSubReg() != AMDGPU::NoSubRegister || !Op.getReg().isVirtual())
1020       return &Op;
1021 
1022     MachineInstr *Def = MRI.getVRegDef(Op.getReg());
1023     if (Def && Def->isMoveImmediate()) {
1024       MachineOperand &ImmSrc = Def->getOperand(1);
1025       if (ImmSrc.isImm())
1026         return &ImmSrc;
1027     }
1028   }
1029 
1030   return &Op;
1031 }
1032 
1033 // Try to simplify operations with a constant that may appear after instruction
1034 // selection.
1035 // TODO: See if a frame index with a fixed offset can fold.
1036 static bool tryConstantFoldOp(MachineRegisterInfo &MRI,
1037                               const SIInstrInfo *TII,
1038                               MachineInstr *MI,
1039                               MachineOperand *ImmOp) {
1040   unsigned Opc = MI->getOpcode();
1041   if (Opc == AMDGPU::V_NOT_B32_e64 || Opc == AMDGPU::V_NOT_B32_e32 ||
1042       Opc == AMDGPU::S_NOT_B32) {
1043     MI->getOperand(1).ChangeToImmediate(~ImmOp->getImm());
1044     mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_NOT_B32)));
1045     return true;
1046   }
1047 
1048   int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
1049   if (Src1Idx == -1)
1050     return false;
1051 
1052   int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
1053   MachineOperand *Src0 = getImmOrMaterializedImm(MRI, MI->getOperand(Src0Idx));
1054   MachineOperand *Src1 = getImmOrMaterializedImm(MRI, MI->getOperand(Src1Idx));
1055 
1056   if (!Src0->isImm() && !Src1->isImm())
1057     return false;
1058 
1059   // and k0, k1 -> v_mov_b32 (k0 & k1)
1060   // or k0, k1 -> v_mov_b32 (k0 | k1)
1061   // xor k0, k1 -> v_mov_b32 (k0 ^ k1)
1062   if (Src0->isImm() && Src1->isImm()) {
1063     int32_t NewImm;
1064     if (!evalBinaryInstruction(Opc, NewImm, Src0->getImm(), Src1->getImm()))
1065       return false;
1066 
1067     const SIRegisterInfo &TRI = TII->getRegisterInfo();
1068     bool IsSGPR = TRI.isSGPRReg(MRI, MI->getOperand(0).getReg());
1069 
1070     // Be careful to change the right operand, src0 may belong to a different
1071     // instruction.
1072     MI->getOperand(Src0Idx).ChangeToImmediate(NewImm);
1073     MI->RemoveOperand(Src1Idx);
1074     mutateCopyOp(*MI, TII->get(getMovOpc(IsSGPR)));
1075     return true;
1076   }
1077 
1078   if (!MI->isCommutable())
1079     return false;
1080 
1081   if (Src0->isImm() && !Src1->isImm()) {
1082     std::swap(Src0, Src1);
1083     std::swap(Src0Idx, Src1Idx);
1084   }
1085 
1086   int32_t Src1Val = static_cast<int32_t>(Src1->getImm());
1087   if (Opc == AMDGPU::V_OR_B32_e64 ||
1088       Opc == AMDGPU::V_OR_B32_e32 ||
1089       Opc == AMDGPU::S_OR_B32) {
1090     if (Src1Val == 0) {
1091       // y = or x, 0 => y = copy x
1092       MI->RemoveOperand(Src1Idx);
1093       mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
1094     } else if (Src1Val == -1) {
1095       // y = or x, -1 => y = v_mov_b32 -1
1096       MI->RemoveOperand(Src1Idx);
1097       mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_OR_B32)));
1098     } else
1099       return false;
1100 
1101     return true;
1102   }
1103 
1104   if (MI->getOpcode() == AMDGPU::V_AND_B32_e64 ||
1105       MI->getOpcode() == AMDGPU::V_AND_B32_e32 ||
1106       MI->getOpcode() == AMDGPU::S_AND_B32) {
1107     if (Src1Val == 0) {
1108       // y = and x, 0 => y = v_mov_b32 0
1109       MI->RemoveOperand(Src0Idx);
1110       mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_AND_B32)));
1111     } else if (Src1Val == -1) {
1112       // y = and x, -1 => y = copy x
1113       MI->RemoveOperand(Src1Idx);
1114       mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
1115       stripExtraCopyOperands(*MI);
1116     } else
1117       return false;
1118 
1119     return true;
1120   }
1121 
1122   if (MI->getOpcode() == AMDGPU::V_XOR_B32_e64 ||
1123       MI->getOpcode() == AMDGPU::V_XOR_B32_e32 ||
1124       MI->getOpcode() == AMDGPU::S_XOR_B32) {
1125     if (Src1Val == 0) {
1126       // y = xor x, 0 => y = copy x
1127       MI->RemoveOperand(Src1Idx);
1128       mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
1129       return true;
1130     }
1131   }
1132 
1133   return false;
1134 }
1135 
1136 // Try to fold an instruction into a simpler one
1137 static bool tryFoldInst(const SIInstrInfo *TII,
1138                         MachineInstr *MI) {
1139   unsigned Opc = MI->getOpcode();
1140 
1141   if (Opc == AMDGPU::V_CNDMASK_B32_e32    ||
1142       Opc == AMDGPU::V_CNDMASK_B32_e64    ||
1143       Opc == AMDGPU::V_CNDMASK_B64_PSEUDO) {
1144     const MachineOperand *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0);
1145     const MachineOperand *Src1 = TII->getNamedOperand(*MI, AMDGPU::OpName::src1);
1146     int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
1147     int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1148     if (Src1->isIdenticalTo(*Src0) &&
1149         (Src1ModIdx == -1 || !MI->getOperand(Src1ModIdx).getImm()) &&
1150         (Src0ModIdx == -1 || !MI->getOperand(Src0ModIdx).getImm())) {
1151       LLVM_DEBUG(dbgs() << "Folded " << *MI << " into ");
1152       auto &NewDesc =
1153           TII->get(Src0->isReg() ? (unsigned)AMDGPU::COPY : getMovOpc(false));
1154       int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
1155       if (Src2Idx != -1)
1156         MI->RemoveOperand(Src2Idx);
1157       MI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1));
1158       if (Src1ModIdx != -1)
1159         MI->RemoveOperand(Src1ModIdx);
1160       if (Src0ModIdx != -1)
1161         MI->RemoveOperand(Src0ModIdx);
1162       mutateCopyOp(*MI, NewDesc);
1163       LLVM_DEBUG(dbgs() << *MI << '\n');
1164       return true;
1165     }
1166   }
1167 
1168   return false;
1169 }
1170 
1171 void SIFoldOperands::foldInstOperand(MachineInstr &MI,
1172                                      MachineOperand &OpToFold) const {
1173   // We need mutate the operands of new mov instructions to add implicit
1174   // uses of EXEC, but adding them invalidates the use_iterator, so defer
1175   // this.
1176   SmallVector<MachineInstr *, 4> CopiesToReplace;
1177   SmallVector<FoldCandidate, 4> FoldList;
1178   MachineOperand &Dst = MI.getOperand(0);
1179 
1180   bool FoldingImm = OpToFold.isImm() || OpToFold.isFI() || OpToFold.isGlobal();
1181   if (FoldingImm) {
1182     unsigned NumLiteralUses = 0;
1183     MachineOperand *NonInlineUse = nullptr;
1184     int NonInlineUseOpNo = -1;
1185 
1186     MachineRegisterInfo::use_nodbg_iterator NextUse;
1187     for (MachineRegisterInfo::use_nodbg_iterator
1188            Use = MRI->use_nodbg_begin(Dst.getReg()), E = MRI->use_nodbg_end();
1189          Use != E; Use = NextUse) {
1190       NextUse = std::next(Use);
1191       MachineInstr *UseMI = Use->getParent();
1192       unsigned OpNo = Use.getOperandNo();
1193 
1194       // Folding the immediate may reveal operations that can be constant
1195       // folded or replaced with a copy. This can happen for example after
1196       // frame indices are lowered to constants or from splitting 64-bit
1197       // constants.
1198       //
1199       // We may also encounter cases where one or both operands are
1200       // immediates materialized into a register, which would ordinarily not
1201       // be folded due to multiple uses or operand constraints.
1202 
1203       if (OpToFold.isImm() && tryConstantFoldOp(*MRI, TII, UseMI, &OpToFold)) {
1204         LLVM_DEBUG(dbgs() << "Constant folded " << *UseMI << '\n');
1205 
1206         // Some constant folding cases change the same immediate's use to a new
1207         // instruction, e.g. and x, 0 -> 0. Make sure we re-visit the user
1208         // again. The same constant folded instruction could also have a second
1209         // use operand.
1210         NextUse = MRI->use_nodbg_begin(Dst.getReg());
1211         FoldList.clear();
1212         continue;
1213       }
1214 
1215       // Try to fold any inline immediate uses, and then only fold other
1216       // constants if they have one use.
1217       //
1218       // The legality of the inline immediate must be checked based on the use
1219       // operand, not the defining instruction, because 32-bit instructions
1220       // with 32-bit inline immediate sources may be used to materialize
1221       // constants used in 16-bit operands.
1222       //
1223       // e.g. it is unsafe to fold:
1224       //  s_mov_b32 s0, 1.0    // materializes 0x3f800000
1225       //  v_add_f16 v0, v1, s0 // 1.0 f16 inline immediate sees 0x00003c00
1226 
1227       // Folding immediates with more than one use will increase program size.
1228       // FIXME: This will also reduce register usage, which may be better
1229       // in some cases. A better heuristic is needed.
1230       if (isInlineConstantIfFolded(TII, *UseMI, OpNo, OpToFold)) {
1231         foldOperand(OpToFold, UseMI, OpNo, FoldList, CopiesToReplace);
1232       } else if (frameIndexMayFold(TII, *UseMI, OpNo, OpToFold)) {
1233         foldOperand(OpToFold, UseMI, OpNo, FoldList,
1234                     CopiesToReplace);
1235       } else {
1236         if (++NumLiteralUses == 1) {
1237           NonInlineUse = &*Use;
1238           NonInlineUseOpNo = OpNo;
1239         }
1240       }
1241     }
1242 
1243     if (NumLiteralUses == 1) {
1244       MachineInstr *UseMI = NonInlineUse->getParent();
1245       foldOperand(OpToFold, UseMI, NonInlineUseOpNo, FoldList, CopiesToReplace);
1246     }
1247   } else {
1248     // Folding register.
1249     SmallVector <MachineRegisterInfo::use_nodbg_iterator, 4> UsesToProcess;
1250     for (MachineRegisterInfo::use_nodbg_iterator
1251            Use = MRI->use_nodbg_begin(Dst.getReg()), E = MRI->use_nodbg_end();
1252          Use != E; ++Use) {
1253       UsesToProcess.push_back(Use);
1254     }
1255     for (auto U : UsesToProcess) {
1256       MachineInstr *UseMI = U->getParent();
1257 
1258       foldOperand(OpToFold, UseMI, U.getOperandNo(),
1259         FoldList, CopiesToReplace);
1260     }
1261   }
1262 
1263   MachineFunction *MF = MI.getParent()->getParent();
1264   // Make sure we add EXEC uses to any new v_mov instructions created.
1265   for (MachineInstr *Copy : CopiesToReplace)
1266     Copy->addImplicitDefUseOperands(*MF);
1267 
1268   SmallPtrSet<MachineInstr *, 16> Folded;
1269   for (FoldCandidate &Fold : FoldList) {
1270     assert(!Fold.isReg() || Fold.OpToFold);
1271     if (Folded.count(Fold.UseMI))
1272       continue;
1273     if (Fold.isReg() && Fold.OpToFold->getReg().isVirtual()) {
1274       Register Reg = Fold.OpToFold->getReg();
1275       MachineInstr *DefMI = Fold.OpToFold->getParent();
1276       if (DefMI->readsRegister(AMDGPU::EXEC, TRI) &&
1277           execMayBeModifiedBeforeUse(*MRI, Reg, *DefMI, *Fold.UseMI))
1278         continue;
1279     }
1280     if (updateOperand(Fold, *TII, *TRI, *ST)) {
1281       // Clear kill flags.
1282       if (Fold.isReg()) {
1283         assert(Fold.OpToFold && Fold.OpToFold->isReg());
1284         // FIXME: Probably shouldn't bother trying to fold if not an
1285         // SGPR. PeepholeOptimizer can eliminate redundant VGPR->VGPR
1286         // copies.
1287         MRI->clearKillFlags(Fold.OpToFold->getReg());
1288       }
1289       LLVM_DEBUG(dbgs() << "Folded source from " << MI << " into OpNo "
1290                         << static_cast<int>(Fold.UseOpNo) << " of "
1291                         << *Fold.UseMI << '\n');
1292       if (tryFoldInst(TII, Fold.UseMI))
1293         Folded.insert(Fold.UseMI);
1294     } else if (Fold.isCommuted()) {
1295       // Restoring instruction's original operand order if fold has failed.
1296       TII->commuteInstruction(*Fold.UseMI, false);
1297     }
1298   }
1299 }
1300 
1301 // Clamp patterns are canonically selected to v_max_* instructions, so only
1302 // handle them.
1303 const MachineOperand *SIFoldOperands::isClamp(const MachineInstr &MI) const {
1304   unsigned Op = MI.getOpcode();
1305   switch (Op) {
1306   case AMDGPU::V_MAX_F32_e64:
1307   case AMDGPU::V_MAX_F16_e64:
1308   case AMDGPU::V_MAX_F64_e64:
1309   case AMDGPU::V_PK_MAX_F16: {
1310     if (!TII->getNamedOperand(MI, AMDGPU::OpName::clamp)->getImm())
1311       return nullptr;
1312 
1313     // Make sure sources are identical.
1314     const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
1315     const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
1316     if (!Src0->isReg() || !Src1->isReg() ||
1317         Src0->getReg() != Src1->getReg() ||
1318         Src0->getSubReg() != Src1->getSubReg() ||
1319         Src0->getSubReg() != AMDGPU::NoSubRegister)
1320       return nullptr;
1321 
1322     // Can't fold up if we have modifiers.
1323     if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod))
1324       return nullptr;
1325 
1326     unsigned Src0Mods
1327       = TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)->getImm();
1328     unsigned Src1Mods
1329       = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers)->getImm();
1330 
1331     // Having a 0 op_sel_hi would require swizzling the output in the source
1332     // instruction, which we can't do.
1333     unsigned UnsetMods = (Op == AMDGPU::V_PK_MAX_F16) ? SISrcMods::OP_SEL_1
1334                                                       : 0u;
1335     if (Src0Mods != UnsetMods && Src1Mods != UnsetMods)
1336       return nullptr;
1337     return Src0;
1338   }
1339   default:
1340     return nullptr;
1341   }
1342 }
1343 
1344 // We obviously have multiple uses in a clamp since the register is used twice
1345 // in the same instruction.
1346 static bool hasOneNonDBGUseInst(const MachineRegisterInfo &MRI, unsigned Reg) {
1347   int Count = 0;
1348   for (auto I = MRI.use_instr_nodbg_begin(Reg), E = MRI.use_instr_nodbg_end();
1349        I != E; ++I) {
1350     if (++Count > 1)
1351       return false;
1352   }
1353 
1354   return true;
1355 }
1356 
1357 // FIXME: Clamp for v_mad_mixhi_f16 handled during isel.
1358 bool SIFoldOperands::tryFoldClamp(MachineInstr &MI) {
1359   const MachineOperand *ClampSrc = isClamp(MI);
1360   if (!ClampSrc || !hasOneNonDBGUseInst(*MRI, ClampSrc->getReg()))
1361     return false;
1362 
1363   MachineInstr *Def = MRI->getVRegDef(ClampSrc->getReg());
1364 
1365   // The type of clamp must be compatible.
1366   if (TII->getClampMask(*Def) != TII->getClampMask(MI))
1367     return false;
1368 
1369   MachineOperand *DefClamp = TII->getNamedOperand(*Def, AMDGPU::OpName::clamp);
1370   if (!DefClamp)
1371     return false;
1372 
1373   LLVM_DEBUG(dbgs() << "Folding clamp " << *DefClamp << " into " << *Def
1374                     << '\n');
1375 
1376   // Clamp is applied after omod, so it is OK if omod is set.
1377   DefClamp->setImm(1);
1378   MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());
1379   MI.eraseFromParent();
1380   return true;
1381 }
1382 
1383 static int getOModValue(unsigned Opc, int64_t Val) {
1384   switch (Opc) {
1385   case AMDGPU::V_MUL_F32_e64: {
1386     switch (static_cast<uint32_t>(Val)) {
1387     case 0x3f000000: // 0.5
1388       return SIOutMods::DIV2;
1389     case 0x40000000: // 2.0
1390       return SIOutMods::MUL2;
1391     case 0x40800000: // 4.0
1392       return SIOutMods::MUL4;
1393     default:
1394       return SIOutMods::NONE;
1395     }
1396   }
1397   case AMDGPU::V_MUL_F16_e64: {
1398     switch (static_cast<uint16_t>(Val)) {
1399     case 0x3800: // 0.5
1400       return SIOutMods::DIV2;
1401     case 0x4000: // 2.0
1402       return SIOutMods::MUL2;
1403     case 0x4400: // 4.0
1404       return SIOutMods::MUL4;
1405     default:
1406       return SIOutMods::NONE;
1407     }
1408   }
1409   default:
1410     llvm_unreachable("invalid mul opcode");
1411   }
1412 }
1413 
1414 // FIXME: Does this really not support denormals with f16?
1415 // FIXME: Does this need to check IEEE mode bit? SNaNs are generally not
1416 // handled, so will anything other than that break?
1417 std::pair<const MachineOperand *, int>
1418 SIFoldOperands::isOMod(const MachineInstr &MI) const {
1419   unsigned Op = MI.getOpcode();
1420   switch (Op) {
1421   case AMDGPU::V_MUL_F32_e64:
1422   case AMDGPU::V_MUL_F16_e64: {
1423     // If output denormals are enabled, omod is ignored.
1424     if ((Op == AMDGPU::V_MUL_F32_e64 && MFI->getMode().FP32OutputDenormals) ||
1425         (Op == AMDGPU::V_MUL_F16_e64 && MFI->getMode().FP64FP16OutputDenormals))
1426       return std::make_pair(nullptr, SIOutMods::NONE);
1427 
1428     const MachineOperand *RegOp = nullptr;
1429     const MachineOperand *ImmOp = nullptr;
1430     const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
1431     const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
1432     if (Src0->isImm()) {
1433       ImmOp = Src0;
1434       RegOp = Src1;
1435     } else if (Src1->isImm()) {
1436       ImmOp = Src1;
1437       RegOp = Src0;
1438     } else
1439       return std::make_pair(nullptr, SIOutMods::NONE);
1440 
1441     int OMod = getOModValue(Op, ImmOp->getImm());
1442     if (OMod == SIOutMods::NONE ||
1443         TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) ||
1444         TII->hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) ||
1445         TII->hasModifiersSet(MI, AMDGPU::OpName::omod) ||
1446         TII->hasModifiersSet(MI, AMDGPU::OpName::clamp))
1447       return std::make_pair(nullptr, SIOutMods::NONE);
1448 
1449     return std::make_pair(RegOp, OMod);
1450   }
1451   case AMDGPU::V_ADD_F32_e64:
1452   case AMDGPU::V_ADD_F16_e64: {
1453     // If output denormals are enabled, omod is ignored.
1454     if ((Op == AMDGPU::V_ADD_F32_e64 && MFI->getMode().FP32OutputDenormals) ||
1455         (Op == AMDGPU::V_ADD_F16_e64 && MFI->getMode().FP64FP16OutputDenormals))
1456       return std::make_pair(nullptr, SIOutMods::NONE);
1457 
1458     // Look through the DAGCombiner canonicalization fmul x, 2 -> fadd x, x
1459     const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
1460     const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
1461 
1462     if (Src0->isReg() && Src1->isReg() && Src0->getReg() == Src1->getReg() &&
1463         Src0->getSubReg() == Src1->getSubReg() &&
1464         !TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) &&
1465         !TII->hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) &&
1466         !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp) &&
1467         !TII->hasModifiersSet(MI, AMDGPU::OpName::omod))
1468       return std::make_pair(Src0, SIOutMods::MUL2);
1469 
1470     return std::make_pair(nullptr, SIOutMods::NONE);
1471   }
1472   default:
1473     return std::make_pair(nullptr, SIOutMods::NONE);
1474   }
1475 }
1476 
1477 // FIXME: Does this need to check IEEE bit on function?
1478 bool SIFoldOperands::tryFoldOMod(MachineInstr &MI) {
1479   const MachineOperand *RegOp;
1480   int OMod;
1481   std::tie(RegOp, OMod) = isOMod(MI);
1482   if (OMod == SIOutMods::NONE || !RegOp->isReg() ||
1483       RegOp->getSubReg() != AMDGPU::NoSubRegister ||
1484       !hasOneNonDBGUseInst(*MRI, RegOp->getReg()))
1485     return false;
1486 
1487   MachineInstr *Def = MRI->getVRegDef(RegOp->getReg());
1488   MachineOperand *DefOMod = TII->getNamedOperand(*Def, AMDGPU::OpName::omod);
1489   if (!DefOMod || DefOMod->getImm() != SIOutMods::NONE)
1490     return false;
1491 
1492   // Clamp is applied after omod. If the source already has clamp set, don't
1493   // fold it.
1494   if (TII->hasModifiersSet(*Def, AMDGPU::OpName::clamp))
1495     return false;
1496 
1497   LLVM_DEBUG(dbgs() << "Folding omod " << MI << " into " << *Def << '\n');
1498 
1499   DefOMod->setImm(OMod);
1500   MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());
1501   MI.eraseFromParent();
1502   return true;
1503 }
1504 
1505 bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
1506   if (skipFunction(MF.getFunction()))
1507     return false;
1508 
1509   MRI = &MF.getRegInfo();
1510   ST = &MF.getSubtarget<GCNSubtarget>();
1511   TII = ST->getInstrInfo();
1512   TRI = &TII->getRegisterInfo();
1513   MFI = MF.getInfo<SIMachineFunctionInfo>();
1514 
1515   // omod is ignored by hardware if IEEE bit is enabled. omod also does not
1516   // correctly handle signed zeros.
1517   //
1518   // FIXME: Also need to check strictfp
1519   bool IsIEEEMode = MFI->getMode().IEEE;
1520   bool HasNSZ = MFI->hasNoSignedZerosFPMath();
1521 
1522   for (MachineBasicBlock *MBB : depth_first(&MF)) {
1523     MachineBasicBlock::iterator I, Next;
1524 
1525     MachineOperand *CurrentKnownM0Val = nullptr;
1526     for (I = MBB->begin(); I != MBB->end(); I = Next) {
1527       Next = std::next(I);
1528       MachineInstr &MI = *I;
1529 
1530       tryFoldInst(TII, &MI);
1531 
1532       if (!TII->isFoldableCopy(MI)) {
1533         // Saw an unknown clobber of m0, so we no longer know what it is.
1534         if (CurrentKnownM0Val && MI.modifiesRegister(AMDGPU::M0, TRI))
1535           CurrentKnownM0Val = nullptr;
1536 
1537         // TODO: Omod might be OK if there is NSZ only on the source
1538         // instruction, and not the omod multiply.
1539         if (IsIEEEMode || (!HasNSZ && !MI.getFlag(MachineInstr::FmNsz)) ||
1540             !tryFoldOMod(MI))
1541           tryFoldClamp(MI);
1542 
1543         continue;
1544       }
1545 
1546       // Specially track simple redefs of m0 to the same value in a block, so we
1547       // can erase the later ones.
1548       if (MI.getOperand(0).getReg() == AMDGPU::M0) {
1549         MachineOperand &NewM0Val = MI.getOperand(1);
1550         if (CurrentKnownM0Val && CurrentKnownM0Val->isIdenticalTo(NewM0Val)) {
1551           MI.eraseFromParent();
1552           continue;
1553         }
1554 
1555         // We aren't tracking other physical registers
1556         CurrentKnownM0Val = (NewM0Val.isReg() && NewM0Val.getReg().isPhysical()) ?
1557           nullptr : &NewM0Val;
1558         continue;
1559       }
1560 
1561       MachineOperand &OpToFold = MI.getOperand(1);
1562       bool FoldingImm =
1563           OpToFold.isImm() || OpToFold.isFI() || OpToFold.isGlobal();
1564 
1565       // FIXME: We could also be folding things like TargetIndexes.
1566       if (!FoldingImm && !OpToFold.isReg())
1567         continue;
1568 
1569       if (OpToFold.isReg() && !OpToFold.getReg().isVirtual())
1570         continue;
1571 
1572       // Prevent folding operands backwards in the function. For example,
1573       // the COPY opcode must not be replaced by 1 in this example:
1574       //
1575       //    %3 = COPY %vgpr0; VGPR_32:%3
1576       //    ...
1577       //    %vgpr0 = V_MOV_B32_e32 1, implicit %exec
1578       MachineOperand &Dst = MI.getOperand(0);
1579       if (Dst.isReg() && !Dst.getReg().isVirtual())
1580         continue;
1581 
1582       foldInstOperand(MI, OpToFold);
1583     }
1584   }
1585   return true;
1586 }
1587