1 //===-- SIFixVGPRCopies.cpp - Fix VGPR Copies after regalloc --------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// Add implicit use of exec to vector register copies. 11 /// 12 //===----------------------------------------------------------------------===// 13 14 #include "AMDGPU.h" 15 #include "GCNSubtarget.h" 16 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 17 #include "llvm/CodeGen/MachineFunctionPass.h" 18 19 using namespace llvm; 20 21 #define DEBUG_TYPE "si-fix-vgpr-copies" 22 23 namespace { 24 25 class SIFixVGPRCopies : public MachineFunctionPass { 26 public: 27 static char ID; 28 29 public: 30 SIFixVGPRCopies() : MachineFunctionPass(ID) { 31 initializeSIFixVGPRCopiesPass(*PassRegistry::getPassRegistry()); 32 } 33 34 bool runOnMachineFunction(MachineFunction &MF) override; 35 36 StringRef getPassName() const override { return "SI Fix VGPR copies"; } 37 }; 38 39 } // End anonymous namespace. 40 41 INITIALIZE_PASS(SIFixVGPRCopies, DEBUG_TYPE, "SI Fix VGPR copies", false, false) 42 43 char SIFixVGPRCopies::ID = 0; 44 45 char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopies::ID; 46 47 bool SIFixVGPRCopies::runOnMachineFunction(MachineFunction &MF) { 48 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); 49 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 50 const SIInstrInfo *TII = ST.getInstrInfo(); 51 bool Changed = false; 52 53 for (MachineBasicBlock &MBB : MF) { 54 for (MachineInstr &MI : MBB) { 55 switch (MI.getOpcode()) { 56 case AMDGPU::COPY: 57 if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) { 58 MI.addOperand(MF, 59 MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); 60 LLVM_DEBUG(dbgs() << "Add exec use to " << MI); 61 Changed = true; 62 } 63 break; 64 default: 65 break; 66 } 67 } 68 } 69 70 return Changed; 71 } 72