1 //===-- SIFixVGPRCopies.cpp - Fix VGPR Copies after regalloc --------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// Add implicit use of exec to vector register copies. 11 /// 12 //===----------------------------------------------------------------------===// 13 14 #include "SIFixVGPRCopies.h" 15 #include "AMDGPU.h" 16 #include "GCNSubtarget.h" 17 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 18 #include "llvm/CodeGen/MachineFunctionPass.h" 19 20 using namespace llvm; 21 22 #define DEBUG_TYPE "si-fix-vgpr-copies" 23 24 namespace { 25 26 class SIFixVGPRCopiesLegacy : public MachineFunctionPass { 27 public: 28 static char ID; 29 30 SIFixVGPRCopiesLegacy() : MachineFunctionPass(ID) { 31 initializeSIFixVGPRCopiesLegacyPass(*PassRegistry::getPassRegistry()); 32 } 33 34 void getAnalysisUsage(AnalysisUsage &AU) const override { 35 AU.setPreservesAll(); 36 MachineFunctionPass::getAnalysisUsage(AU); 37 } 38 39 bool runOnMachineFunction(MachineFunction &MF) override; 40 41 StringRef getPassName() const override { return "SI Fix VGPR copies"; } 42 }; 43 44 class SIFixVGPRCopies { 45 public: 46 bool run(MachineFunction &MF); 47 }; 48 49 } // End anonymous namespace. 50 51 INITIALIZE_PASS(SIFixVGPRCopiesLegacy, DEBUG_TYPE, "SI Fix VGPR copies", false, 52 false) 53 54 char SIFixVGPRCopiesLegacy::ID = 0; 55 56 char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopiesLegacy::ID; 57 58 PreservedAnalyses SIFixVGPRCopiesPass::run(MachineFunction &MF, 59 MachineFunctionAnalysisManager &) { 60 SIFixVGPRCopies().run(MF); 61 return PreservedAnalyses::all(); 62 } 63 64 bool SIFixVGPRCopiesLegacy::runOnMachineFunction(MachineFunction &MF) { 65 return SIFixVGPRCopies().run(MF); 66 } 67 68 bool SIFixVGPRCopies::run(MachineFunction &MF) { 69 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); 70 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 71 const SIInstrInfo *TII = ST.getInstrInfo(); 72 bool Changed = false; 73 74 for (MachineBasicBlock &MBB : MF) { 75 for (MachineInstr &MI : MBB) { 76 switch (MI.getOpcode()) { 77 case AMDGPU::COPY: 78 if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) { 79 MI.addOperand(MF, 80 MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); 81 LLVM_DEBUG(dbgs() << "Add exec use to " << MI); 82 Changed = true; 83 } 84 break; 85 default: 86 break; 87 } 88 } 89 } 90 91 return Changed; 92 } 93