xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/SIDefines.h (revision a521f2116473fbd8c09db395518f060a27d02334)
1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/MC/MCInstrDesc.h"
11 
12 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
13 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
14 
15 namespace llvm {
16 
17 namespace SIInstrFlags {
18 // This needs to be kept in sync with the field bits in InstSI.
19 enum : uint64_t {
20   // Low bits - basic encoding information.
21   SALU = 1 << 0,
22   VALU = 1 << 1,
23 
24   // SALU instruction formats.
25   SOP1 = 1 << 2,
26   SOP2 = 1 << 3,
27   SOPC = 1 << 4,
28   SOPK = 1 << 5,
29   SOPP = 1 << 6,
30 
31   // VALU instruction formats.
32   VOP1 = 1 << 7,
33   VOP2 = 1 << 8,
34   VOPC = 1 << 9,
35 
36  // TODO: Should this be spilt into VOP3 a and b?
37   VOP3 = 1 << 10,
38   VOP3P = 1 << 12,
39 
40   VINTRP = 1 << 13,
41   SDWA = 1 << 14,
42   DPP = 1 << 15,
43 
44   // Memory instruction formats.
45   MUBUF = 1 << 16,
46   MTBUF = 1 << 17,
47   SMRD = 1 << 18,
48   MIMG = 1 << 19,
49   EXP = 1 << 20,
50   FLAT = 1 << 21,
51   DS = 1 << 22,
52 
53   // Pseudo instruction formats.
54   VGPRSpill = 1 << 23,
55   SGPRSpill = 1 << 24,
56 
57   // High bits - other information.
58   VM_CNT = UINT64_C(1) << 32,
59   EXP_CNT = UINT64_C(1) << 33,
60   LGKM_CNT = UINT64_C(1) << 34,
61 
62   WQM = UINT64_C(1) << 35,
63   DisableWQM = UINT64_C(1) << 36,
64   Gather4 = UINT64_C(1) << 37,
65   SOPK_ZEXT = UINT64_C(1) << 38,
66   SCALAR_STORE = UINT64_C(1) << 39,
67   FIXED_SIZE = UINT64_C(1) << 40,
68   VOPAsmPrefer32Bit = UINT64_C(1) << 41,
69   VOP3_OPSEL = UINT64_C(1) << 42,
70   maybeAtomic = UINT64_C(1) << 43,
71   renamedInGFX9 = UINT64_C(1) << 44,
72 
73   // Is a clamp on FP type.
74   FPClamp = UINT64_C(1) << 45,
75 
76   // Is an integer clamp
77   IntClamp = UINT64_C(1) << 46,
78 
79   // Clamps lo component of register.
80   ClampLo = UINT64_C(1) << 47,
81 
82   // Clamps hi component of register.
83   // ClampLo and ClampHi set for packed clamp.
84   ClampHi = UINT64_C(1) << 48,
85 
86   // Is a packed VOP3P instruction.
87   IsPacked = UINT64_C(1) << 49,
88 
89   // Is a D16 buffer instruction.
90   D16Buf = UINT64_C(1) << 50,
91 
92   // FLAT instruction accesses FLAT_GLBL or FLAT_SCRATCH segment.
93   IsNonFlatSeg = UINT64_C(1) << 51,
94 
95   // Uses floating point double precision rounding mode
96   FPDPRounding = UINT64_C(1) << 52,
97 
98   // Instruction is FP atomic.
99   FPAtomic = UINT64_C(1) << 53,
100 
101   // Is a MFMA instruction.
102   IsMAI = UINT64_C(1) << 54,
103 
104   // Is a DOT instruction.
105   IsDOT = UINT64_C(1) << 55
106 };
107 
108 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
109 // The result is true if any of these tests are true.
110 enum ClassFlags : unsigned {
111   S_NAN = 1 << 0,        // Signaling NaN
112   Q_NAN = 1 << 1,        // Quiet NaN
113   N_INFINITY = 1 << 2,   // Negative infinity
114   N_NORMAL = 1 << 3,     // Negative normal
115   N_SUBNORMAL = 1 << 4,  // Negative subnormal
116   N_ZERO = 1 << 5,       // Negative zero
117   P_ZERO = 1 << 6,       // Positive zero
118   P_SUBNORMAL = 1 << 7,  // Positive subnormal
119   P_NORMAL = 1 << 8,     // Positive normal
120   P_INFINITY = 1 << 9    // Positive infinity
121 };
122 }
123 
124 namespace AMDGPU {
125   enum OperandType : unsigned {
126     /// Operands with register or 32-bit immediate
127     OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
128     OPERAND_REG_IMM_INT64,
129     OPERAND_REG_IMM_INT16,
130     OPERAND_REG_IMM_FP32,
131     OPERAND_REG_IMM_FP64,
132     OPERAND_REG_IMM_FP16,
133     OPERAND_REG_IMM_V2FP16,
134     OPERAND_REG_IMM_V2INT16,
135 
136     /// Operands with register or inline constant
137     OPERAND_REG_INLINE_C_INT16,
138     OPERAND_REG_INLINE_C_INT32,
139     OPERAND_REG_INLINE_C_INT64,
140     OPERAND_REG_INLINE_C_FP16,
141     OPERAND_REG_INLINE_C_FP32,
142     OPERAND_REG_INLINE_C_FP64,
143     OPERAND_REG_INLINE_C_V2FP16,
144     OPERAND_REG_INLINE_C_V2INT16,
145 
146     /// Operands with an AccVGPR register or inline constant
147     OPERAND_REG_INLINE_AC_INT16,
148     OPERAND_REG_INLINE_AC_INT32,
149     OPERAND_REG_INLINE_AC_FP16,
150     OPERAND_REG_INLINE_AC_FP32,
151     OPERAND_REG_INLINE_AC_V2FP16,
152     OPERAND_REG_INLINE_AC_V2INT16,
153 
154     OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
155     OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2INT16,
156 
157     OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
158     OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2INT16,
159 
160     OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16,
161     OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2INT16,
162 
163     OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
164     OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
165 
166     // Operand for source modifiers for VOP instructions
167     OPERAND_INPUT_MODS,
168 
169     // Operand for SDWA instructions
170     OPERAND_SDWA_VOPC_DST,
171 
172     /// Operand with 32-bit immediate that uses the constant bus.
173     OPERAND_KIMM32,
174     OPERAND_KIMM16
175   };
176 }
177 
178 // Input operand modifiers bit-masks
179 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
180 namespace SISrcMods {
181   enum : unsigned {
182    NEG = 1 << 0,   // Floating-point negate modifier
183    ABS = 1 << 1,   // Floating-point absolute modifier
184    SEXT = 1 << 0,  // Integer sign-extend modifier
185    NEG_HI = ABS,   // Floating-point negate high packed component modifier.
186    OP_SEL_0 = 1 << 2,
187    OP_SEL_1 = 1 << 3,
188    DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
189   };
190 }
191 
192 namespace SIOutMods {
193   enum : unsigned {
194     NONE = 0,
195     MUL2 = 1,
196     MUL4 = 2,
197     DIV2 = 3
198   };
199 }
200 
201 namespace AMDGPU {
202 namespace VGPRIndexMode {
203 
204 enum Id : unsigned { // id of symbolic names
205   ID_SRC0 = 0,
206   ID_SRC1,
207   ID_SRC2,
208   ID_DST,
209 
210   ID_MIN = ID_SRC0,
211   ID_MAX = ID_DST
212 };
213 
214 enum EncBits : unsigned {
215   OFF = 0,
216   SRC0_ENABLE = 1 << ID_SRC0,
217   SRC1_ENABLE = 1 << ID_SRC1,
218   SRC2_ENABLE = 1 << ID_SRC2,
219   DST_ENABLE = 1 << ID_DST,
220   ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE
221 };
222 
223 } // namespace VGPRIndexMode
224 } // namespace AMDGPU
225 
226 namespace AMDGPUAsmVariants {
227   enum : unsigned {
228     DEFAULT = 0,
229     VOP3 = 1,
230     SDWA = 2,
231     SDWA9 = 3,
232     DPP = 4
233   };
234 }
235 
236 namespace AMDGPU {
237 namespace EncValues { // Encoding values of enum9/8/7 operands
238 
239 enum : unsigned {
240   SGPR_MIN = 0,
241   SGPR_MAX_SI = 101,
242   SGPR_MAX_GFX10 = 105,
243   TTMP_VI_MIN = 112,
244   TTMP_VI_MAX = 123,
245   TTMP_GFX9_GFX10_MIN = 108,
246   TTMP_GFX9_GFX10_MAX = 123,
247   INLINE_INTEGER_C_MIN = 128,
248   INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
249   INLINE_INTEGER_C_MAX = 208,
250   INLINE_FLOATING_C_MIN = 240,
251   INLINE_FLOATING_C_MAX = 248,
252   LITERAL_CONST = 255,
253   VGPR_MIN = 256,
254   VGPR_MAX = 511
255 };
256 
257 } // namespace EncValues
258 } // namespace AMDGPU
259 
260 namespace AMDGPU {
261 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
262 
263 enum Id { // Message ID, width(4) [3:0].
264   ID_UNKNOWN_ = -1,
265   ID_INTERRUPT = 1,
266   ID_GS,
267   ID_GS_DONE,
268   ID_GS_ALLOC_REQ = 9,
269   ID_GET_DOORBELL = 10,
270   ID_SYSMSG = 15,
271   ID_GAPS_LAST_, // Indicate that sequence has gaps.
272   ID_GAPS_FIRST_ = ID_INTERRUPT,
273   ID_SHIFT_ = 0,
274   ID_WIDTH_ = 4,
275   ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
276 };
277 
278 enum Op { // Both GS and SYS operation IDs.
279   OP_UNKNOWN_ = -1,
280   OP_SHIFT_ = 4,
281   OP_NONE_ = 0,
282   // Bits used for operation encoding
283   OP_WIDTH_ = 3,
284   OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
285   // GS operations are encoded in bits 5:4
286   OP_GS_NOP = 0,
287   OP_GS_CUT,
288   OP_GS_EMIT,
289   OP_GS_EMIT_CUT,
290   OP_GS_LAST_,
291   OP_GS_FIRST_ = OP_GS_NOP,
292   // SYS operations are encoded in bits 6:4
293   OP_SYS_ECC_ERR_INTERRUPT = 1,
294   OP_SYS_REG_RD,
295   OP_SYS_HOST_TRAP_ACK,
296   OP_SYS_TTRACE_PC,
297   OP_SYS_LAST_,
298   OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
299 };
300 
301 enum StreamId : unsigned { // Stream ID, (2) [9:8].
302   STREAM_ID_NONE_ = 0,
303   STREAM_ID_DEFAULT_ = 0,
304   STREAM_ID_LAST_ = 4,
305   STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
306   STREAM_ID_SHIFT_ = 8,
307   STREAM_ID_WIDTH_=  2,
308   STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
309 };
310 
311 } // namespace SendMsg
312 
313 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
314 
315 enum Id { // HwRegCode, (6) [5:0]
316   ID_UNKNOWN_ = -1,
317   ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
318   ID_MODE = 1,
319   ID_STATUS = 2,
320   ID_TRAPSTS = 3,
321   ID_HW_ID = 4,
322   ID_GPR_ALLOC = 5,
323   ID_LDS_ALLOC = 6,
324   ID_IB_STS = 7,
325   ID_MEM_BASES = 15,
326   ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES,
327   ID_TBA_LO = 16,
328   ID_SYMBOLIC_FIRST_GFX10_ = ID_TBA_LO,
329   ID_TBA_HI = 17,
330   ID_TMA_LO = 18,
331   ID_TMA_HI = 19,
332   ID_FLAT_SCR_LO = 20,
333   ID_FLAT_SCR_HI = 21,
334   ID_XNACK_MASK = 22,
335   ID_POPS_PACKER = 25,
336   ID_SHADER_CYCLES = 29,
337   ID_SYMBOLIC_FIRST_GFX1030_ = ID_SHADER_CYCLES,
338   ID_SYMBOLIC_LAST_ = 30,
339   ID_SHIFT_ = 0,
340   ID_WIDTH_ = 6,
341   ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
342 };
343 
344 enum Offset : unsigned { // Offset, (5) [10:6]
345   OFFSET_DEFAULT_ = 0,
346   OFFSET_SHIFT_ = 6,
347   OFFSET_WIDTH_ = 5,
348   OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_),
349 
350   OFFSET_MEM_VIOL = 8,
351 
352   OFFSET_SRC_SHARED_BASE = 16,
353   OFFSET_SRC_PRIVATE_BASE = 0
354 };
355 
356 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11]
357   WIDTH_M1_DEFAULT_ = 31,
358   WIDTH_M1_SHIFT_ = 11,
359   WIDTH_M1_WIDTH_ = 5,
360   WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_),
361 
362   WIDTH_M1_SRC_SHARED_BASE = 15,
363   WIDTH_M1_SRC_PRIVATE_BASE = 15
364 };
365 
366 // Some values from WidthMinusOne mapped into Width domain.
367 enum Width : unsigned {
368   WIDTH_DEFAULT_ = WIDTH_M1_DEFAULT_ + 1,
369 };
370 
371 enum ModeRegisterMasks : uint32_t {
372   FP_ROUND_MASK = 0xf << 0,  // Bits 0..3
373   FP_DENORM_MASK = 0xf << 4, // Bits 4..7
374   DX10_CLAMP_MASK = 1 << 8,
375   IEEE_MODE_MASK = 1 << 9,
376   LOD_CLAMP_MASK = 1 << 10,
377   DEBUG_MASK = 1 << 11,
378 
379   // EXCP_EN fields.
380   EXCP_EN_INVALID_MASK = 1 << 12,
381   EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13,
382   EXCP_EN_FLOAT_DIV0_MASK = 1 << 14,
383   EXCP_EN_OVERFLOW_MASK = 1 << 15,
384   EXCP_EN_UNDERFLOW_MASK = 1 << 16,
385   EXCP_EN_INEXACT_MASK = 1 << 17,
386   EXCP_EN_INT_DIV0_MASK = 1 << 18,
387 
388   GPR_IDX_EN_MASK = 1 << 27,
389   VSKIP_MASK = 1 << 28,
390   CSP_MASK = 0x7u << 29 // Bits 29..31
391 };
392 
393 } // namespace Hwreg
394 
395 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
396 
397 enum Id : unsigned { // id of symbolic names
398   ID_QUAD_PERM = 0,
399   ID_BITMASK_PERM,
400   ID_SWAP,
401   ID_REVERSE,
402   ID_BROADCAST
403 };
404 
405 enum EncBits : unsigned {
406 
407   // swizzle mode encodings
408 
409   QUAD_PERM_ENC         = 0x8000,
410   QUAD_PERM_ENC_MASK    = 0xFF00,
411 
412   BITMASK_PERM_ENC      = 0x0000,
413   BITMASK_PERM_ENC_MASK = 0x8000,
414 
415   // QUAD_PERM encodings
416 
417   LANE_MASK             = 0x3,
418   LANE_MAX              = LANE_MASK,
419   LANE_SHIFT            = 2,
420   LANE_NUM              = 4,
421 
422   // BITMASK_PERM encodings
423 
424   BITMASK_MASK          = 0x1F,
425   BITMASK_MAX           = BITMASK_MASK,
426   BITMASK_WIDTH         = 5,
427 
428   BITMASK_AND_SHIFT     = 0,
429   BITMASK_OR_SHIFT      = 5,
430   BITMASK_XOR_SHIFT     = 10
431 };
432 
433 } // namespace Swizzle
434 
435 namespace SDWA {
436 
437 enum SdwaSel : unsigned {
438   BYTE_0 = 0,
439   BYTE_1 = 1,
440   BYTE_2 = 2,
441   BYTE_3 = 3,
442   WORD_0 = 4,
443   WORD_1 = 5,
444   DWORD = 6,
445 };
446 
447 enum DstUnused : unsigned {
448   UNUSED_PAD = 0,
449   UNUSED_SEXT = 1,
450   UNUSED_PRESERVE = 2,
451 };
452 
453 enum SDWA9EncValues : unsigned {
454   SRC_SGPR_MASK = 0x100,
455   SRC_VGPR_MASK = 0xFF,
456   VOPC_DST_VCC_MASK = 0x80,
457   VOPC_DST_SGPR_MASK = 0x7F,
458 
459   SRC_VGPR_MIN = 0,
460   SRC_VGPR_MAX = 255,
461   SRC_SGPR_MIN = 256,
462   SRC_SGPR_MAX_SI = 357,
463   SRC_SGPR_MAX_GFX10 = 361,
464   SRC_TTMP_MIN = 364,
465   SRC_TTMP_MAX = 379,
466 };
467 
468 } // namespace SDWA
469 
470 namespace DPP {
471 
472 enum DppCtrl : unsigned {
473   QUAD_PERM_FIRST   = 0,
474   QUAD_PERM_ID      = 0xE4, // identity permutation
475   QUAD_PERM_LAST    = 0xFF,
476   DPP_UNUSED1       = 0x100,
477   ROW_SHL0          = 0x100,
478   ROW_SHL_FIRST     = 0x101,
479   ROW_SHL_LAST      = 0x10F,
480   DPP_UNUSED2       = 0x110,
481   ROW_SHR0          = 0x110,
482   ROW_SHR_FIRST     = 0x111,
483   ROW_SHR_LAST      = 0x11F,
484   DPP_UNUSED3       = 0x120,
485   ROW_ROR0          = 0x120,
486   ROW_ROR_FIRST     = 0x121,
487   ROW_ROR_LAST      = 0x12F,
488   WAVE_SHL1         = 0x130,
489   DPP_UNUSED4_FIRST = 0x131,
490   DPP_UNUSED4_LAST  = 0x133,
491   WAVE_ROL1         = 0x134,
492   DPP_UNUSED5_FIRST = 0x135,
493   DPP_UNUSED5_LAST  = 0x137,
494   WAVE_SHR1         = 0x138,
495   DPP_UNUSED6_FIRST = 0x139,
496   DPP_UNUSED6_LAST  = 0x13B,
497   WAVE_ROR1         = 0x13C,
498   DPP_UNUSED7_FIRST = 0x13D,
499   DPP_UNUSED7_LAST  = 0x13F,
500   ROW_MIRROR        = 0x140,
501   ROW_HALF_MIRROR   = 0x141,
502   BCAST15           = 0x142,
503   BCAST31           = 0x143,
504   DPP_UNUSED8_FIRST = 0x144,
505   DPP_UNUSED8_LAST  = 0x14F,
506   ROW_SHARE_FIRST   = 0x150,
507   ROW_SHARE_LAST    = 0x15F,
508   ROW_XMASK_FIRST   = 0x160,
509   ROW_XMASK_LAST    = 0x16F,
510   DPP_LAST          = ROW_XMASK_LAST
511 };
512 
513 enum DppFiMode {
514   DPP_FI_0  = 0,
515   DPP_FI_1  = 1,
516   DPP8_FI_0 = 0xE9,
517   DPP8_FI_1 = 0xEA,
518 };
519 
520 } // namespace DPP
521 } // namespace AMDGPU
522 
523 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS                                0x00B028
524 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS                                0x00B02C
525 #define   S_00B02C_EXTRA_LDS_SIZE(x)                                  (((x) & 0xFF) << 8)
526 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS                                0x00B128
527 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS                                0x00B228
528 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES                                0x00B328
529 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS                                0x00B428
530 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS                                0x00B528
531 #define R_00B848_COMPUTE_PGM_RSRC1                                      0x00B848
532 #define   S_00B028_VGPRS(x)                                           (((x) & 0x3F) << 0)
533 #define   S_00B028_SGPRS(x)                                           (((x) & 0x0F) << 6)
534 
535 #define R_00B84C_COMPUTE_PGM_RSRC2                                      0x00B84C
536 #define   S_00B84C_SCRATCH_EN(x)                                      (((x) & 0x1) << 0)
537 #define   G_00B84C_SCRATCH_EN(x)                                      (((x) >> 0) & 0x1)
538 #define   C_00B84C_SCRATCH_EN                                         0xFFFFFFFE
539 #define   S_00B84C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
540 #define   G_00B84C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
541 #define   C_00B84C_USER_SGPR                                          0xFFFFFFC1
542 #define   S_00B84C_TRAP_HANDLER(x)                                    (((x) & 0x1) << 6)
543 #define   G_00B84C_TRAP_HANDLER(x)                                    (((x) >> 6) & 0x1)
544 #define   C_00B84C_TRAP_HANDLER                                       0xFFFFFFBF
545 #define   S_00B84C_TGID_X_EN(x)                                       (((x) & 0x1) << 7)
546 #define   G_00B84C_TGID_X_EN(x)                                       (((x) >> 7) & 0x1)
547 #define   C_00B84C_TGID_X_EN                                          0xFFFFFF7F
548 #define   S_00B84C_TGID_Y_EN(x)                                       (((x) & 0x1) << 8)
549 #define   G_00B84C_TGID_Y_EN(x)                                       (((x) >> 8) & 0x1)
550 #define   C_00B84C_TGID_Y_EN                                          0xFFFFFEFF
551 #define   S_00B84C_TGID_Z_EN(x)                                       (((x) & 0x1) << 9)
552 #define   G_00B84C_TGID_Z_EN(x)                                       (((x) >> 9) & 0x1)
553 #define   C_00B84C_TGID_Z_EN                                          0xFFFFFDFF
554 #define   S_00B84C_TG_SIZE_EN(x)                                      (((x) & 0x1) << 10)
555 #define   G_00B84C_TG_SIZE_EN(x)                                      (((x) >> 10) & 0x1)
556 #define   C_00B84C_TG_SIZE_EN                                         0xFFFFFBFF
557 #define   S_00B84C_TIDIG_COMP_CNT(x)                                  (((x) & 0x03) << 11)
558 #define   G_00B84C_TIDIG_COMP_CNT(x)                                  (((x) >> 11) & 0x03)
559 #define   C_00B84C_TIDIG_COMP_CNT                                     0xFFFFE7FF
560 /* CIK */
561 #define   S_00B84C_EXCP_EN_MSB(x)                                     (((x) & 0x03) << 13)
562 #define   G_00B84C_EXCP_EN_MSB(x)                                     (((x) >> 13) & 0x03)
563 #define   C_00B84C_EXCP_EN_MSB                                        0xFFFF9FFF
564 /*     */
565 #define   S_00B84C_LDS_SIZE(x)                                        (((x) & 0x1FF) << 15)
566 #define   G_00B84C_LDS_SIZE(x)                                        (((x) >> 15) & 0x1FF)
567 #define   C_00B84C_LDS_SIZE                                           0xFF007FFF
568 #define   S_00B84C_EXCP_EN(x)                                         (((x) & 0x7F) << 24)
569 #define   G_00B84C_EXCP_EN(x)                                         (((x) >> 24) & 0x7F)
570 #define   C_00B84C_EXCP_EN
571 
572 #define R_0286CC_SPI_PS_INPUT_ENA                                       0x0286CC
573 #define R_0286D0_SPI_PS_INPUT_ADDR                                      0x0286D0
574 
575 #define R_00B848_COMPUTE_PGM_RSRC1                                      0x00B848
576 #define   S_00B848_VGPRS(x)                                           (((x) & 0x3F) << 0)
577 #define   G_00B848_VGPRS(x)                                           (((x) >> 0) & 0x3F)
578 #define   C_00B848_VGPRS                                              0xFFFFFFC0
579 #define   S_00B848_SGPRS(x)                                           (((x) & 0x0F) << 6)
580 #define   G_00B848_SGPRS(x)                                           (((x) >> 6) & 0x0F)
581 #define   C_00B848_SGPRS                                              0xFFFFFC3F
582 #define   S_00B848_PRIORITY(x)                                        (((x) & 0x03) << 10)
583 #define   G_00B848_PRIORITY(x)                                        (((x) >> 10) & 0x03)
584 #define   C_00B848_PRIORITY                                           0xFFFFF3FF
585 #define   S_00B848_FLOAT_MODE(x)                                      (((x) & 0xFF) << 12)
586 #define   G_00B848_FLOAT_MODE(x)                                      (((x) >> 12) & 0xFF)
587 #define   C_00B848_FLOAT_MODE                                         0xFFF00FFF
588 #define   S_00B848_PRIV(x)                                            (((x) & 0x1) << 20)
589 #define   G_00B848_PRIV(x)                                            (((x) >> 20) & 0x1)
590 #define   C_00B848_PRIV                                               0xFFEFFFFF
591 #define   S_00B848_DX10_CLAMP(x)                                      (((x) & 0x1) << 21)
592 #define   G_00B848_DX10_CLAMP(x)                                      (((x) >> 21) & 0x1)
593 #define   C_00B848_DX10_CLAMP                                         0xFFDFFFFF
594 #define   S_00B848_DEBUG_MODE(x)                                      (((x) & 0x1) << 22)
595 #define   G_00B848_DEBUG_MODE(x)                                      (((x) >> 22) & 0x1)
596 #define   C_00B848_DEBUG_MODE                                         0xFFBFFFFF
597 #define   S_00B848_IEEE_MODE(x)                                       (((x) & 0x1) << 23)
598 #define   G_00B848_IEEE_MODE(x)                                       (((x) >> 23) & 0x1)
599 #define   C_00B848_IEEE_MODE                                          0xFF7FFFFF
600 #define   S_00B848_WGP_MODE(x)                                        (((x) & 0x1) << 29)
601 #define   G_00B848_WGP_MODE(x)                                        (((x) >> 29) & 0x1)
602 #define   C_00B848_WGP_MODE                                           0xDFFFFFFF
603 #define   S_00B848_MEM_ORDERED(x)                                     (((x) & 0x1) << 30)
604 #define   G_00B848_MEM_ORDERED(x)                                     (((x) >> 30) & 0x1)
605 #define   C_00B848_MEM_ORDERED                                        0xBFFFFFFF
606 #define   S_00B848_FWD_PROGRESS(x)                                    (((x) & 0x1) << 31)
607 #define   G_00B848_FWD_PROGRESS(x)                                    (((x) >> 31) & 0x1)
608 #define   C_00B848_FWD_PROGRESS                                       0x7FFFFFFF
609 
610 
611 // Helpers for setting FLOAT_MODE
612 #define FP_ROUND_ROUND_TO_NEAREST 0
613 #define FP_ROUND_ROUND_TO_INF 1
614 #define FP_ROUND_ROUND_TO_NEGINF 2
615 #define FP_ROUND_ROUND_TO_ZERO 3
616 
617 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
618 // precision.
619 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
620 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
621 
622 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
623 #define FP_DENORM_FLUSH_OUT 1
624 #define FP_DENORM_FLUSH_IN 2
625 #define FP_DENORM_FLUSH_NONE 3
626 
627 
628 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
629 // precision.
630 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
631 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
632 
633 #define R_00B860_COMPUTE_TMPRING_SIZE                                   0x00B860
634 #define   S_00B860_WAVESIZE(x)                                        (((x) & 0x1FFF) << 12)
635 
636 #define R_0286E8_SPI_TMPRING_SIZE                                       0x0286E8
637 #define   S_0286E8_WAVESIZE(x)                                        (((x) & 0x1FFF) << 12)
638 
639 #define R_028B54_VGT_SHADER_STAGES_EN                                 0x028B54
640 #define   S_028B54_HS_W32_EN(x)                                       (((x) & 0x1) << 21)
641 #define   S_028B54_GS_W32_EN(x)                                       (((x) & 0x1) << 22)
642 #define   S_028B54_VS_W32_EN(x)                                       (((x) & 0x1) << 23)
643 #define R_0286D8_SPI_PS_IN_CONTROL                                    0x0286D8
644 #define   S_0286D8_PS_W32_EN(x)                                       (((x) & 0x1) << 15)
645 #define R_00B800_COMPUTE_DISPATCH_INITIATOR                           0x00B800
646 #define   S_00B800_CS_W32_EN(x)                                       (((x) & 0x1) << 15)
647 
648 #define R_SPILLED_SGPRS         0x4
649 #define R_SPILLED_VGPRS         0x8
650 } // End namespace llvm
651 
652 #endif
653