1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 11 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 12 13 #include "llvm/MC/MCInstrDesc.h" 14 15 namespace llvm { 16 17 // This needs to be kept in sync with the field bits in SIRegisterClass. 18 enum SIRCFlags : uint8_t { 19 // For vector registers. 20 HasVGPR = 1 << 0, 21 HasAGPR = 1 << 1, 22 HasSGPR = 1 << 2 23 }; // enum SIRCFlags 24 25 namespace SIInstrFlags { 26 // This needs to be kept in sync with the field bits in InstSI. 27 enum : uint64_t { 28 // Low bits - basic encoding information. 29 SALU = 1 << 0, 30 VALU = 1 << 1, 31 32 // SALU instruction formats. 33 SOP1 = 1 << 2, 34 SOP2 = 1 << 3, 35 SOPC = 1 << 4, 36 SOPK = 1 << 5, 37 SOPP = 1 << 6, 38 39 // VALU instruction formats. 40 VOP1 = 1 << 7, 41 VOP2 = 1 << 8, 42 VOPC = 1 << 9, 43 44 // TODO: Should this be spilt into VOP3 a and b? 45 VOP3 = 1 << 10, 46 VOP3P = 1 << 12, 47 48 VINTRP = 1 << 13, 49 SDWA = 1 << 14, 50 DPP = 1 << 15, 51 TRANS = 1 << 16, 52 53 // Memory instruction formats. 54 MUBUF = 1 << 17, 55 MTBUF = 1 << 18, 56 SMRD = 1 << 19, 57 MIMG = 1 << 20, 58 EXP = 1 << 21, 59 FLAT = 1 << 22, 60 DS = 1 << 23, 61 62 // Pseudo instruction formats. 63 VGPRSpill = 1 << 24, 64 SGPRSpill = 1 << 25, 65 66 // High bits - other information. 67 VM_CNT = UINT64_C(1) << 32, 68 EXP_CNT = UINT64_C(1) << 33, 69 LGKM_CNT = UINT64_C(1) << 34, 70 71 WQM = UINT64_C(1) << 35, 72 DisableWQM = UINT64_C(1) << 36, 73 Gather4 = UINT64_C(1) << 37, 74 SOPK_ZEXT = UINT64_C(1) << 38, 75 SCALAR_STORE = UINT64_C(1) << 39, 76 FIXED_SIZE = UINT64_C(1) << 40, 77 VOPAsmPrefer32Bit = UINT64_C(1) << 41, 78 VOP3_OPSEL = UINT64_C(1) << 42, 79 maybeAtomic = UINT64_C(1) << 43, 80 renamedInGFX9 = UINT64_C(1) << 44, 81 82 // Is a clamp on FP type. 83 FPClamp = UINT64_C(1) << 45, 84 85 // Is an integer clamp 86 IntClamp = UINT64_C(1) << 46, 87 88 // Clamps lo component of register. 89 ClampLo = UINT64_C(1) << 47, 90 91 // Clamps hi component of register. 92 // ClampLo and ClampHi set for packed clamp. 93 ClampHi = UINT64_C(1) << 48, 94 95 // Is a packed VOP3P instruction. 96 IsPacked = UINT64_C(1) << 49, 97 98 // Is a D16 buffer instruction. 99 D16Buf = UINT64_C(1) << 50, 100 101 // FLAT instruction accesses FLAT_GLBL segment. 102 FlatGlobal = UINT64_C(1) << 51, 103 104 // Uses floating point double precision rounding mode 105 FPDPRounding = UINT64_C(1) << 52, 106 107 // Instruction is FP atomic. 108 FPAtomic = UINT64_C(1) << 53, 109 110 // Is a MFMA instruction. 111 IsMAI = UINT64_C(1) << 54, 112 113 // Is a DOT instruction. 114 IsDOT = UINT64_C(1) << 55, 115 116 // FLAT instruction accesses FLAT_SCRATCH segment. 117 FlatScratch = UINT64_C(1) << 56, 118 119 // Atomic without return. 120 IsAtomicNoRet = UINT64_C(1) << 57, 121 122 // Atomic with return. 123 IsAtomicRet = UINT64_C(1) << 58 124 }; 125 126 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 127 // The result is true if any of these tests are true. 128 enum ClassFlags : unsigned { 129 S_NAN = 1 << 0, // Signaling NaN 130 Q_NAN = 1 << 1, // Quiet NaN 131 N_INFINITY = 1 << 2, // Negative infinity 132 N_NORMAL = 1 << 3, // Negative normal 133 N_SUBNORMAL = 1 << 4, // Negative subnormal 134 N_ZERO = 1 << 5, // Negative zero 135 P_ZERO = 1 << 6, // Positive zero 136 P_SUBNORMAL = 1 << 7, // Positive subnormal 137 P_NORMAL = 1 << 8, // Positive normal 138 P_INFINITY = 1 << 9 // Positive infinity 139 }; 140 } 141 142 namespace AMDGPU { 143 enum OperandType : unsigned { 144 /// Operands with register or 32-bit immediate 145 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, 146 OPERAND_REG_IMM_INT64, 147 OPERAND_REG_IMM_INT16, 148 OPERAND_REG_IMM_FP32, 149 OPERAND_REG_IMM_FP64, 150 OPERAND_REG_IMM_FP16, 151 OPERAND_REG_IMM_FP16_DEFERRED, 152 OPERAND_REG_IMM_FP32_DEFERRED, 153 OPERAND_REG_IMM_V2FP16, 154 OPERAND_REG_IMM_V2INT16, 155 OPERAND_REG_IMM_V2INT32, 156 OPERAND_REG_IMM_V2FP32, 157 158 /// Operands with register or inline constant 159 OPERAND_REG_INLINE_C_INT16, 160 OPERAND_REG_INLINE_C_INT32, 161 OPERAND_REG_INLINE_C_INT64, 162 OPERAND_REG_INLINE_C_FP16, 163 OPERAND_REG_INLINE_C_FP32, 164 OPERAND_REG_INLINE_C_FP64, 165 OPERAND_REG_INLINE_C_V2INT16, 166 OPERAND_REG_INLINE_C_V2FP16, 167 OPERAND_REG_INLINE_C_V2INT32, 168 OPERAND_REG_INLINE_C_V2FP32, 169 170 /// Operand with 32-bit immediate that uses the constant bus. 171 OPERAND_KIMM32, 172 OPERAND_KIMM16, 173 174 /// Operands with an AccVGPR register or inline constant 175 OPERAND_REG_INLINE_AC_INT16, 176 OPERAND_REG_INLINE_AC_INT32, 177 OPERAND_REG_INLINE_AC_FP16, 178 OPERAND_REG_INLINE_AC_FP32, 179 OPERAND_REG_INLINE_AC_FP64, 180 OPERAND_REG_INLINE_AC_V2INT16, 181 OPERAND_REG_INLINE_AC_V2FP16, 182 OPERAND_REG_INLINE_AC_V2INT32, 183 OPERAND_REG_INLINE_AC_V2FP32, 184 185 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, 186 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32, 187 188 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, 189 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32, 190 191 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16, 192 OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32, 193 194 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, 195 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, 196 197 // Operand for source modifiers for VOP instructions 198 OPERAND_INPUT_MODS, 199 200 // Operand for SDWA instructions 201 OPERAND_SDWA_VOPC_DST 202 203 }; 204 } 205 206 // Input operand modifiers bit-masks 207 // NEG and SEXT share same bit-mask because they can't be set simultaneously. 208 namespace SISrcMods { 209 enum : unsigned { 210 NEG = 1 << 0, // Floating-point negate modifier 211 ABS = 1 << 1, // Floating-point absolute modifier 212 SEXT = 1 << 0, // Integer sign-extend modifier 213 NEG_HI = ABS, // Floating-point negate high packed component modifier. 214 OP_SEL_0 = 1 << 2, 215 OP_SEL_1 = 1 << 3, 216 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1) 217 }; 218 } 219 220 namespace SIOutMods { 221 enum : unsigned { 222 NONE = 0, 223 MUL2 = 1, 224 MUL4 = 2, 225 DIV2 = 3 226 }; 227 } 228 229 namespace AMDGPU { 230 namespace VGPRIndexMode { 231 232 enum Id : unsigned { // id of symbolic names 233 ID_SRC0 = 0, 234 ID_SRC1, 235 ID_SRC2, 236 ID_DST, 237 238 ID_MIN = ID_SRC0, 239 ID_MAX = ID_DST 240 }; 241 242 enum EncBits : unsigned { 243 OFF = 0, 244 SRC0_ENABLE = 1 << ID_SRC0, 245 SRC1_ENABLE = 1 << ID_SRC1, 246 SRC2_ENABLE = 1 << ID_SRC2, 247 DST_ENABLE = 1 << ID_DST, 248 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE, 249 UNDEF = 0xFFFF 250 }; 251 252 } // namespace VGPRIndexMode 253 } // namespace AMDGPU 254 255 namespace AMDGPUAsmVariants { 256 enum : unsigned { 257 DEFAULT = 0, 258 VOP3 = 1, 259 SDWA = 2, 260 SDWA9 = 3, 261 DPP = 4 262 }; 263 } 264 265 namespace AMDGPU { 266 namespace EncValues { // Encoding values of enum9/8/7 operands 267 268 enum : unsigned { 269 SGPR_MIN = 0, 270 SGPR_MAX_SI = 101, 271 SGPR_MAX_GFX10 = 105, 272 TTMP_VI_MIN = 112, 273 TTMP_VI_MAX = 123, 274 TTMP_GFX9PLUS_MIN = 108, 275 TTMP_GFX9PLUS_MAX = 123, 276 INLINE_INTEGER_C_MIN = 128, 277 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64 278 INLINE_INTEGER_C_MAX = 208, 279 INLINE_FLOATING_C_MIN = 240, 280 INLINE_FLOATING_C_MAX = 248, 281 LITERAL_CONST = 255, 282 VGPR_MIN = 256, 283 VGPR_MAX = 511 284 }; 285 286 } // namespace EncValues 287 } // namespace AMDGPU 288 289 namespace AMDGPU { 290 namespace CPol { 291 292 enum CPol { 293 GLC = 1, 294 SLC = 2, 295 DLC = 4, 296 SCC = 16, 297 ALL = GLC | SLC | DLC | SCC 298 }; 299 300 } // namespace CPol 301 302 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. 303 304 enum Id { // Message ID, width(4) [3:0]. 305 ID_UNKNOWN_ = -1, 306 ID_INTERRUPT = 1, 307 ID_GS = 2, 308 ID_GS_DONE = 3, 309 ID_SAVEWAVE = 4, // added in GFX8 310 ID_STALL_WAVE_GEN = 5, // added in GFX9 311 ID_HALT_WAVES = 6, // added in GFX9 312 ID_ORDERED_PS_DONE = 7, // added in GFX9 313 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10 314 ID_GS_ALLOC_REQ = 9, // added in GFX9 315 ID_GET_DOORBELL = 10, // added in GFX9 316 ID_GET_DDID = 11, // added in GFX10 317 ID_SYSMSG = 15, 318 ID_GAPS_LAST_, // Indicate that sequence has gaps. 319 ID_GAPS_FIRST_ = ID_INTERRUPT, 320 ID_SHIFT_ = 0, 321 ID_WIDTH_ = 4, 322 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 323 }; 324 325 enum Op { // Both GS and SYS operation IDs. 326 OP_UNKNOWN_ = -1, 327 OP_SHIFT_ = 4, 328 OP_NONE_ = 0, 329 // Bits used for operation encoding 330 OP_WIDTH_ = 3, 331 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_), 332 // GS operations are encoded in bits 5:4 333 OP_GS_NOP = 0, 334 OP_GS_CUT = 1, 335 OP_GS_EMIT = 2, 336 OP_GS_EMIT_CUT = 3, 337 OP_GS_LAST_, 338 OP_GS_FIRST_ = OP_GS_NOP, 339 // SYS operations are encoded in bits 6:4 340 OP_SYS_ECC_ERR_INTERRUPT = 1, 341 OP_SYS_REG_RD = 2, 342 OP_SYS_HOST_TRAP_ACK = 3, 343 OP_SYS_TTRACE_PC = 4, 344 OP_SYS_LAST_, 345 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT, 346 }; 347 348 enum StreamId : unsigned { // Stream ID, (2) [9:8]. 349 STREAM_ID_NONE_ = 0, 350 STREAM_ID_DEFAULT_ = 0, 351 STREAM_ID_LAST_ = 4, 352 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_, 353 STREAM_ID_SHIFT_ = 8, 354 STREAM_ID_WIDTH_= 2, 355 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_) 356 }; 357 358 } // namespace SendMsg 359 360 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. 361 362 enum Id { // HwRegCode, (6) [5:0] 363 ID_UNKNOWN_ = -1, 364 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined. 365 ID_MODE = 1, 366 ID_STATUS = 2, 367 ID_TRAPSTS = 3, 368 ID_HW_ID = 4, 369 ID_GPR_ALLOC = 5, 370 ID_LDS_ALLOC = 6, 371 ID_IB_STS = 7, 372 ID_MEM_BASES = 15, 373 ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES, 374 ID_TBA_LO = 16, 375 ID_SYMBOLIC_FIRST_GFX10_ = ID_TBA_LO, 376 ID_TBA_HI = 17, 377 ID_TMA_LO = 18, 378 ID_TMA_HI = 19, 379 ID_FLAT_SCR_LO = 20, 380 ID_FLAT_SCR_HI = 21, 381 ID_XNACK_MASK = 22, 382 ID_HW_ID1 = 23, 383 ID_HW_ID2 = 24, 384 ID_POPS_PACKER = 25, 385 ID_SHADER_CYCLES = 29, 386 ID_SYMBOLIC_FIRST_GFX1030_ = ID_SHADER_CYCLES, 387 ID_SYMBOLIC_LAST_ = 30, 388 ID_SHIFT_ = 0, 389 ID_WIDTH_ = 6, 390 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 391 }; 392 393 enum Offset : unsigned { // Offset, (5) [10:6] 394 OFFSET_DEFAULT_ = 0, 395 OFFSET_SHIFT_ = 6, 396 OFFSET_WIDTH_ = 5, 397 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_), 398 399 OFFSET_MEM_VIOL = 8, 400 401 OFFSET_SRC_SHARED_BASE = 16, 402 OFFSET_SRC_PRIVATE_BASE = 0 403 }; 404 405 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11] 406 WIDTH_M1_DEFAULT_ = 31, 407 WIDTH_M1_SHIFT_ = 11, 408 WIDTH_M1_WIDTH_ = 5, 409 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_), 410 411 WIDTH_M1_SRC_SHARED_BASE = 15, 412 WIDTH_M1_SRC_PRIVATE_BASE = 15 413 }; 414 415 // Some values from WidthMinusOne mapped into Width domain. 416 enum Width : unsigned { 417 WIDTH_DEFAULT_ = WIDTH_M1_DEFAULT_ + 1, 418 }; 419 420 enum ModeRegisterMasks : uint32_t { 421 FP_ROUND_MASK = 0xf << 0, // Bits 0..3 422 FP_DENORM_MASK = 0xf << 4, // Bits 4..7 423 DX10_CLAMP_MASK = 1 << 8, 424 IEEE_MODE_MASK = 1 << 9, 425 LOD_CLAMP_MASK = 1 << 10, 426 DEBUG_MASK = 1 << 11, 427 428 // EXCP_EN fields. 429 EXCP_EN_INVALID_MASK = 1 << 12, 430 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13, 431 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14, 432 EXCP_EN_OVERFLOW_MASK = 1 << 15, 433 EXCP_EN_UNDERFLOW_MASK = 1 << 16, 434 EXCP_EN_INEXACT_MASK = 1 << 17, 435 EXCP_EN_INT_DIV0_MASK = 1 << 18, 436 437 GPR_IDX_EN_MASK = 1 << 27, 438 VSKIP_MASK = 1 << 28, 439 CSP_MASK = 0x7u << 29 // Bits 29..31 440 }; 441 442 } // namespace Hwreg 443 444 namespace MTBUFFormat { 445 446 enum DataFormat : int64_t { 447 DFMT_INVALID = 0, 448 DFMT_8, 449 DFMT_16, 450 DFMT_8_8, 451 DFMT_32, 452 DFMT_16_16, 453 DFMT_10_11_11, 454 DFMT_11_11_10, 455 DFMT_10_10_10_2, 456 DFMT_2_10_10_10, 457 DFMT_8_8_8_8, 458 DFMT_32_32, 459 DFMT_16_16_16_16, 460 DFMT_32_32_32, 461 DFMT_32_32_32_32, 462 DFMT_RESERVED_15, 463 464 DFMT_MIN = DFMT_INVALID, 465 DFMT_MAX = DFMT_RESERVED_15, 466 467 DFMT_UNDEF = -1, 468 DFMT_DEFAULT = DFMT_8, 469 470 DFMT_SHIFT = 0, 471 DFMT_MASK = 0xF 472 }; 473 474 enum NumFormat : int64_t { 475 NFMT_UNORM = 0, 476 NFMT_SNORM, 477 NFMT_USCALED, 478 NFMT_SSCALED, 479 NFMT_UINT, 480 NFMT_SINT, 481 NFMT_RESERVED_6, // VI and GFX9 482 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only 483 NFMT_FLOAT, 484 485 NFMT_MIN = NFMT_UNORM, 486 NFMT_MAX = NFMT_FLOAT, 487 488 NFMT_UNDEF = -1, 489 NFMT_DEFAULT = NFMT_UNORM, 490 491 NFMT_SHIFT = 4, 492 NFMT_MASK = 7 493 }; 494 495 enum MergedFormat : int64_t { 496 DFMT_NFMT_UNDEF = -1, 497 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) | 498 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT), 499 500 501 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT), 502 503 DFMT_NFMT_MAX = DFMT_NFMT_MASK 504 }; 505 506 enum UnifiedFormat : int64_t { 507 UFMT_INVALID = 0, 508 509 UFMT_8_UNORM, 510 UFMT_8_SNORM, 511 UFMT_8_USCALED, 512 UFMT_8_SSCALED, 513 UFMT_8_UINT, 514 UFMT_8_SINT, 515 516 UFMT_16_UNORM, 517 UFMT_16_SNORM, 518 UFMT_16_USCALED, 519 UFMT_16_SSCALED, 520 UFMT_16_UINT, 521 UFMT_16_SINT, 522 UFMT_16_FLOAT, 523 524 UFMT_8_8_UNORM, 525 UFMT_8_8_SNORM, 526 UFMT_8_8_USCALED, 527 UFMT_8_8_SSCALED, 528 UFMT_8_8_UINT, 529 UFMT_8_8_SINT, 530 531 UFMT_32_UINT, 532 UFMT_32_SINT, 533 UFMT_32_FLOAT, 534 535 UFMT_16_16_UNORM, 536 UFMT_16_16_SNORM, 537 UFMT_16_16_USCALED, 538 UFMT_16_16_SSCALED, 539 UFMT_16_16_UINT, 540 UFMT_16_16_SINT, 541 UFMT_16_16_FLOAT, 542 543 UFMT_10_11_11_UNORM, 544 UFMT_10_11_11_SNORM, 545 UFMT_10_11_11_USCALED, 546 UFMT_10_11_11_SSCALED, 547 UFMT_10_11_11_UINT, 548 UFMT_10_11_11_SINT, 549 UFMT_10_11_11_FLOAT, 550 551 UFMT_11_11_10_UNORM, 552 UFMT_11_11_10_SNORM, 553 UFMT_11_11_10_USCALED, 554 UFMT_11_11_10_SSCALED, 555 UFMT_11_11_10_UINT, 556 UFMT_11_11_10_SINT, 557 UFMT_11_11_10_FLOAT, 558 559 UFMT_10_10_10_2_UNORM, 560 UFMT_10_10_10_2_SNORM, 561 UFMT_10_10_10_2_USCALED, 562 UFMT_10_10_10_2_SSCALED, 563 UFMT_10_10_10_2_UINT, 564 UFMT_10_10_10_2_SINT, 565 566 UFMT_2_10_10_10_UNORM, 567 UFMT_2_10_10_10_SNORM, 568 UFMT_2_10_10_10_USCALED, 569 UFMT_2_10_10_10_SSCALED, 570 UFMT_2_10_10_10_UINT, 571 UFMT_2_10_10_10_SINT, 572 573 UFMT_8_8_8_8_UNORM, 574 UFMT_8_8_8_8_SNORM, 575 UFMT_8_8_8_8_USCALED, 576 UFMT_8_8_8_8_SSCALED, 577 UFMT_8_8_8_8_UINT, 578 UFMT_8_8_8_8_SINT, 579 580 UFMT_32_32_UINT, 581 UFMT_32_32_SINT, 582 UFMT_32_32_FLOAT, 583 584 UFMT_16_16_16_16_UNORM, 585 UFMT_16_16_16_16_SNORM, 586 UFMT_16_16_16_16_USCALED, 587 UFMT_16_16_16_16_SSCALED, 588 UFMT_16_16_16_16_UINT, 589 UFMT_16_16_16_16_SINT, 590 UFMT_16_16_16_16_FLOAT, 591 592 UFMT_32_32_32_UINT, 593 UFMT_32_32_32_SINT, 594 UFMT_32_32_32_FLOAT, 595 UFMT_32_32_32_32_UINT, 596 UFMT_32_32_32_32_SINT, 597 UFMT_32_32_32_32_FLOAT, 598 599 UFMT_FIRST = UFMT_INVALID, 600 UFMT_LAST = UFMT_32_32_32_32_FLOAT, 601 602 UFMT_MAX = 127, 603 604 UFMT_UNDEF = -1, 605 UFMT_DEFAULT = UFMT_8_UNORM 606 }; 607 608 } // namespace MTBUFFormat 609 610 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32. 611 612 enum Id : unsigned { // id of symbolic names 613 ID_QUAD_PERM = 0, 614 ID_BITMASK_PERM, 615 ID_SWAP, 616 ID_REVERSE, 617 ID_BROADCAST 618 }; 619 620 enum EncBits : unsigned { 621 622 // swizzle mode encodings 623 624 QUAD_PERM_ENC = 0x8000, 625 QUAD_PERM_ENC_MASK = 0xFF00, 626 627 BITMASK_PERM_ENC = 0x0000, 628 BITMASK_PERM_ENC_MASK = 0x8000, 629 630 // QUAD_PERM encodings 631 632 LANE_MASK = 0x3, 633 LANE_MAX = LANE_MASK, 634 LANE_SHIFT = 2, 635 LANE_NUM = 4, 636 637 // BITMASK_PERM encodings 638 639 BITMASK_MASK = 0x1F, 640 BITMASK_MAX = BITMASK_MASK, 641 BITMASK_WIDTH = 5, 642 643 BITMASK_AND_SHIFT = 0, 644 BITMASK_OR_SHIFT = 5, 645 BITMASK_XOR_SHIFT = 10 646 }; 647 648 } // namespace Swizzle 649 650 namespace SDWA { 651 652 enum SdwaSel : unsigned { 653 BYTE_0 = 0, 654 BYTE_1 = 1, 655 BYTE_2 = 2, 656 BYTE_3 = 3, 657 WORD_0 = 4, 658 WORD_1 = 5, 659 DWORD = 6, 660 }; 661 662 enum DstUnused : unsigned { 663 UNUSED_PAD = 0, 664 UNUSED_SEXT = 1, 665 UNUSED_PRESERVE = 2, 666 }; 667 668 enum SDWA9EncValues : unsigned { 669 SRC_SGPR_MASK = 0x100, 670 SRC_VGPR_MASK = 0xFF, 671 VOPC_DST_VCC_MASK = 0x80, 672 VOPC_DST_SGPR_MASK = 0x7F, 673 674 SRC_VGPR_MIN = 0, 675 SRC_VGPR_MAX = 255, 676 SRC_SGPR_MIN = 256, 677 SRC_SGPR_MAX_SI = 357, 678 SRC_SGPR_MAX_GFX10 = 361, 679 SRC_TTMP_MIN = 364, 680 SRC_TTMP_MAX = 379, 681 }; 682 683 } // namespace SDWA 684 685 namespace DPP { 686 687 // clang-format off 688 enum DppCtrl : unsigned { 689 QUAD_PERM_FIRST = 0, 690 QUAD_PERM_ID = 0xE4, // identity permutation 691 QUAD_PERM_LAST = 0xFF, 692 DPP_UNUSED1 = 0x100, 693 ROW_SHL0 = 0x100, 694 ROW_SHL_FIRST = 0x101, 695 ROW_SHL_LAST = 0x10F, 696 DPP_UNUSED2 = 0x110, 697 ROW_SHR0 = 0x110, 698 ROW_SHR_FIRST = 0x111, 699 ROW_SHR_LAST = 0x11F, 700 DPP_UNUSED3 = 0x120, 701 ROW_ROR0 = 0x120, 702 ROW_ROR_FIRST = 0x121, 703 ROW_ROR_LAST = 0x12F, 704 WAVE_SHL1 = 0x130, 705 DPP_UNUSED4_FIRST = 0x131, 706 DPP_UNUSED4_LAST = 0x133, 707 WAVE_ROL1 = 0x134, 708 DPP_UNUSED5_FIRST = 0x135, 709 DPP_UNUSED5_LAST = 0x137, 710 WAVE_SHR1 = 0x138, 711 DPP_UNUSED6_FIRST = 0x139, 712 DPP_UNUSED6_LAST = 0x13B, 713 WAVE_ROR1 = 0x13C, 714 DPP_UNUSED7_FIRST = 0x13D, 715 DPP_UNUSED7_LAST = 0x13F, 716 ROW_MIRROR = 0x140, 717 ROW_HALF_MIRROR = 0x141, 718 BCAST15 = 0x142, 719 BCAST31 = 0x143, 720 DPP_UNUSED8_FIRST = 0x144, 721 DPP_UNUSED8_LAST = 0x14F, 722 ROW_NEWBCAST_FIRST= 0x150, 723 ROW_NEWBCAST_LAST = 0x15F, 724 ROW_SHARE0 = 0x150, 725 ROW_SHARE_FIRST = 0x150, 726 ROW_SHARE_LAST = 0x15F, 727 ROW_XMASK0 = 0x160, 728 ROW_XMASK_FIRST = 0x160, 729 ROW_XMASK_LAST = 0x16F, 730 DPP_LAST = ROW_XMASK_LAST 731 }; 732 // clang-format on 733 734 enum DppFiMode { 735 DPP_FI_0 = 0, 736 DPP_FI_1 = 1, 737 DPP8_FI_0 = 0xE9, 738 DPP8_FI_1 = 0xEA, 739 }; 740 741 } // namespace DPP 742 743 namespace Exp { 744 745 enum Target : unsigned { 746 ET_MRT0 = 0, 747 ET_MRT7 = 7, 748 ET_MRTZ = 8, 749 ET_NULL = 9, 750 ET_POS0 = 12, 751 ET_POS3 = 15, 752 ET_POS4 = 16, // GFX10+ 753 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget 754 ET_PRIM = 20, // GFX10+ 755 ET_PARAM0 = 32, 756 ET_PARAM31 = 63, 757 758 ET_NULL_MAX_IDX = 0, 759 ET_MRTZ_MAX_IDX = 0, 760 ET_PRIM_MAX_IDX = 0, 761 ET_MRT_MAX_IDX = 7, 762 ET_POS_MAX_IDX = 4, 763 ET_PARAM_MAX_IDX = 31, 764 765 ET_INVALID = 255, 766 }; 767 768 } // namespace Exp 769 770 namespace VOP3PEncoding { 771 772 enum OpSel : uint64_t { 773 OP_SEL_HI_0 = UINT64_C(1) << 59, 774 OP_SEL_HI_1 = UINT64_C(1) << 60, 775 OP_SEL_HI_2 = UINT64_C(1) << 14, 776 }; 777 778 } // namespace VOP3PEncoding 779 780 } // namespace AMDGPU 781 782 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 783 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 784 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 785 #define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25) 786 #define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1) 787 #define C_00B028_MEM_ORDERED 0xFDFFFFFF 788 789 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 790 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 791 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 792 #define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27) 793 #define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1) 794 #define C_00B128_MEM_ORDERED 0xF7FFFFFF 795 796 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 797 #define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27) 798 #define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1) 799 #define C_00B228_WGP_MODE 0xF7FFFFFF 800 #define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25) 801 #define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1) 802 #define C_00B228_MEM_ORDERED 0xFDFFFFFF 803 804 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328 805 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428 806 #define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26) 807 #define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1) 808 #define C_00B428_WGP_MODE 0xFBFFFFFF 809 #define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24) 810 #define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1) 811 #define C_00B428_MEM_ORDERED 0xFEFFFFFF 812 813 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528 814 815 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 816 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 817 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 818 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 819 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 820 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 821 #define C_00B84C_USER_SGPR 0xFFFFFFC1 822 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6) 823 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1) 824 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF 825 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 826 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 827 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 828 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 829 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 830 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 831 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 832 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 833 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 834 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 835 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 836 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 837 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 838 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 839 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 840 /* CIK */ 841 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 842 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 843 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 844 /* */ 845 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 846 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 847 #define C_00B84C_LDS_SIZE 0xFF007FFF 848 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 849 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 850 #define C_00B84C_EXCP_EN 851 852 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 853 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 854 855 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 856 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 857 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 858 #define C_00B848_VGPRS 0xFFFFFFC0 859 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 860 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 861 #define C_00B848_SGPRS 0xFFFFFC3F 862 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 863 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 864 #define C_00B848_PRIORITY 0xFFFFF3FF 865 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 866 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 867 #define C_00B848_FLOAT_MODE 0xFFF00FFF 868 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 869 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 870 #define C_00B848_PRIV 0xFFEFFFFF 871 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 872 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 873 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 874 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 875 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 876 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 877 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 878 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 879 #define C_00B848_IEEE_MODE 0xFF7FFFFF 880 #define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29) 881 #define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1) 882 #define C_00B848_WGP_MODE 0xDFFFFFFF 883 #define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30) 884 #define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1) 885 #define C_00B848_MEM_ORDERED 0xBFFFFFFF 886 #define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31) 887 #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1) 888 #define C_00B848_FWD_PROGRESS 0x7FFFFFFF 889 890 891 // Helpers for setting FLOAT_MODE 892 #define FP_ROUND_ROUND_TO_NEAREST 0 893 #define FP_ROUND_ROUND_TO_INF 1 894 #define FP_ROUND_ROUND_TO_NEGINF 2 895 #define FP_ROUND_ROUND_TO_ZERO 3 896 897 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 898 // precision. 899 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 900 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 901 902 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 903 #define FP_DENORM_FLUSH_OUT 1 904 #define FP_DENORM_FLUSH_IN 2 905 #define FP_DENORM_FLUSH_NONE 3 906 907 908 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 909 // precision. 910 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 911 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 912 913 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 914 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) 915 916 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 917 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) 918 919 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54 920 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21) 921 #define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22) 922 #define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23) 923 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8 924 #define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15) 925 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800 926 #define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15) 927 928 #define R_SPILLED_SGPRS 0x4 929 #define R_SPILLED_VGPRS 0x8 930 } // End namespace llvm 931 932 #endif 933