1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 11 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 12 13 #include "llvm/MC/MCInstrDesc.h" 14 15 namespace llvm { 16 17 // This needs to be kept in sync with the field bits in SIRegisterClass. 18 enum SIRCFlags : uint8_t { 19 // For vector registers. 20 HasVGPR = 1 << 0, 21 HasAGPR = 1 << 1 22 }; // enum SIRCFlags 23 24 namespace SIInstrFlags { 25 // This needs to be kept in sync with the field bits in InstSI. 26 enum : uint64_t { 27 // Low bits - basic encoding information. 28 SALU = 1 << 0, 29 VALU = 1 << 1, 30 31 // SALU instruction formats. 32 SOP1 = 1 << 2, 33 SOP2 = 1 << 3, 34 SOPC = 1 << 4, 35 SOPK = 1 << 5, 36 SOPP = 1 << 6, 37 38 // VALU instruction formats. 39 VOP1 = 1 << 7, 40 VOP2 = 1 << 8, 41 VOPC = 1 << 9, 42 43 // TODO: Should this be spilt into VOP3 a and b? 44 VOP3 = 1 << 10, 45 VOP3P = 1 << 12, 46 47 VINTRP = 1 << 13, 48 SDWA = 1 << 14, 49 DPP = 1 << 15, 50 TRANS = 1 << 16, 51 52 // Memory instruction formats. 53 MUBUF = 1 << 17, 54 MTBUF = 1 << 18, 55 SMRD = 1 << 19, 56 MIMG = 1 << 20, 57 EXP = 1 << 21, 58 FLAT = 1 << 22, 59 DS = 1 << 23, 60 61 // Pseudo instruction formats. 62 VGPRSpill = 1 << 24, 63 SGPRSpill = 1 << 25, 64 65 // High bits - other information. 66 VM_CNT = UINT64_C(1) << 32, 67 EXP_CNT = UINT64_C(1) << 33, 68 LGKM_CNT = UINT64_C(1) << 34, 69 70 WQM = UINT64_C(1) << 35, 71 DisableWQM = UINT64_C(1) << 36, 72 Gather4 = UINT64_C(1) << 37, 73 SOPK_ZEXT = UINT64_C(1) << 38, 74 SCALAR_STORE = UINT64_C(1) << 39, 75 FIXED_SIZE = UINT64_C(1) << 40, 76 VOPAsmPrefer32Bit = UINT64_C(1) << 41, 77 VOP3_OPSEL = UINT64_C(1) << 42, 78 maybeAtomic = UINT64_C(1) << 43, 79 renamedInGFX9 = UINT64_C(1) << 44, 80 81 // Is a clamp on FP type. 82 FPClamp = UINT64_C(1) << 45, 83 84 // Is an integer clamp 85 IntClamp = UINT64_C(1) << 46, 86 87 // Clamps lo component of register. 88 ClampLo = UINT64_C(1) << 47, 89 90 // Clamps hi component of register. 91 // ClampLo and ClampHi set for packed clamp. 92 ClampHi = UINT64_C(1) << 48, 93 94 // Is a packed VOP3P instruction. 95 IsPacked = UINT64_C(1) << 49, 96 97 // Is a D16 buffer instruction. 98 D16Buf = UINT64_C(1) << 50, 99 100 // FLAT instruction accesses FLAT_GLBL segment. 101 FlatGlobal = UINT64_C(1) << 51, 102 103 // Uses floating point double precision rounding mode 104 FPDPRounding = UINT64_C(1) << 52, 105 106 // Instruction is FP atomic. 107 FPAtomic = UINT64_C(1) << 53, 108 109 // Is a MFMA instruction. 110 IsMAI = UINT64_C(1) << 54, 111 112 // Is a DOT instruction. 113 IsDOT = UINT64_C(1) << 55, 114 115 // FLAT instruction accesses FLAT_SCRATCH segment. 116 FlatScratch = UINT64_C(1) << 56, 117 118 // Atomic without return. 119 IsAtomicNoRet = UINT64_C(1) << 57, 120 121 // Atomic with return. 122 IsAtomicRet = UINT64_C(1) << 58 123 }; 124 125 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 126 // The result is true if any of these tests are true. 127 enum ClassFlags : unsigned { 128 S_NAN = 1 << 0, // Signaling NaN 129 Q_NAN = 1 << 1, // Quiet NaN 130 N_INFINITY = 1 << 2, // Negative infinity 131 N_NORMAL = 1 << 3, // Negative normal 132 N_SUBNORMAL = 1 << 4, // Negative subnormal 133 N_ZERO = 1 << 5, // Negative zero 134 P_ZERO = 1 << 6, // Positive zero 135 P_SUBNORMAL = 1 << 7, // Positive subnormal 136 P_NORMAL = 1 << 8, // Positive normal 137 P_INFINITY = 1 << 9 // Positive infinity 138 }; 139 } 140 141 namespace AMDGPU { 142 enum OperandType : unsigned { 143 /// Operands with register or 32-bit immediate 144 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, 145 OPERAND_REG_IMM_INT64, 146 OPERAND_REG_IMM_INT16, 147 OPERAND_REG_IMM_FP32, 148 OPERAND_REG_IMM_FP64, 149 OPERAND_REG_IMM_FP16, 150 OPERAND_REG_IMM_FP16_DEFERRED, 151 OPERAND_REG_IMM_FP32_DEFERRED, 152 OPERAND_REG_IMM_V2FP16, 153 OPERAND_REG_IMM_V2INT16, 154 OPERAND_REG_IMM_V2INT32, 155 OPERAND_REG_IMM_V2FP32, 156 157 /// Operands with register or inline constant 158 OPERAND_REG_INLINE_C_INT16, 159 OPERAND_REG_INLINE_C_INT32, 160 OPERAND_REG_INLINE_C_INT64, 161 OPERAND_REG_INLINE_C_FP16, 162 OPERAND_REG_INLINE_C_FP32, 163 OPERAND_REG_INLINE_C_FP64, 164 OPERAND_REG_INLINE_C_V2INT16, 165 OPERAND_REG_INLINE_C_V2FP16, 166 OPERAND_REG_INLINE_C_V2INT32, 167 OPERAND_REG_INLINE_C_V2FP32, 168 169 /// Operand with 32-bit immediate that uses the constant bus. 170 OPERAND_KIMM32, 171 OPERAND_KIMM16, 172 173 /// Operands with an AccVGPR register or inline constant 174 OPERAND_REG_INLINE_AC_INT16, 175 OPERAND_REG_INLINE_AC_INT32, 176 OPERAND_REG_INLINE_AC_FP16, 177 OPERAND_REG_INLINE_AC_FP32, 178 OPERAND_REG_INLINE_AC_FP64, 179 OPERAND_REG_INLINE_AC_V2INT16, 180 OPERAND_REG_INLINE_AC_V2FP16, 181 OPERAND_REG_INLINE_AC_V2INT32, 182 OPERAND_REG_INLINE_AC_V2FP32, 183 184 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, 185 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32, 186 187 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, 188 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32, 189 190 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16, 191 OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32, 192 193 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, 194 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, 195 196 // Operand for source modifiers for VOP instructions 197 OPERAND_INPUT_MODS, 198 199 // Operand for SDWA instructions 200 OPERAND_SDWA_VOPC_DST 201 202 }; 203 } 204 205 // Input operand modifiers bit-masks 206 // NEG and SEXT share same bit-mask because they can't be set simultaneously. 207 namespace SISrcMods { 208 enum : unsigned { 209 NEG = 1 << 0, // Floating-point negate modifier 210 ABS = 1 << 1, // Floating-point absolute modifier 211 SEXT = 1 << 0, // Integer sign-extend modifier 212 NEG_HI = ABS, // Floating-point negate high packed component modifier. 213 OP_SEL_0 = 1 << 2, 214 OP_SEL_1 = 1 << 3, 215 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1) 216 }; 217 } 218 219 namespace SIOutMods { 220 enum : unsigned { 221 NONE = 0, 222 MUL2 = 1, 223 MUL4 = 2, 224 DIV2 = 3 225 }; 226 } 227 228 namespace AMDGPU { 229 namespace VGPRIndexMode { 230 231 enum Id : unsigned { // id of symbolic names 232 ID_SRC0 = 0, 233 ID_SRC1, 234 ID_SRC2, 235 ID_DST, 236 237 ID_MIN = ID_SRC0, 238 ID_MAX = ID_DST 239 }; 240 241 enum EncBits : unsigned { 242 OFF = 0, 243 SRC0_ENABLE = 1 << ID_SRC0, 244 SRC1_ENABLE = 1 << ID_SRC1, 245 SRC2_ENABLE = 1 << ID_SRC2, 246 DST_ENABLE = 1 << ID_DST, 247 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE, 248 UNDEF = 0xFFFF 249 }; 250 251 } // namespace VGPRIndexMode 252 } // namespace AMDGPU 253 254 namespace AMDGPUAsmVariants { 255 enum : unsigned { 256 DEFAULT = 0, 257 VOP3 = 1, 258 SDWA = 2, 259 SDWA9 = 3, 260 DPP = 4 261 }; 262 } 263 264 namespace AMDGPU { 265 namespace EncValues { // Encoding values of enum9/8/7 operands 266 267 enum : unsigned { 268 SGPR_MIN = 0, 269 SGPR_MAX_SI = 101, 270 SGPR_MAX_GFX10 = 105, 271 TTMP_VI_MIN = 112, 272 TTMP_VI_MAX = 123, 273 TTMP_GFX9PLUS_MIN = 108, 274 TTMP_GFX9PLUS_MAX = 123, 275 INLINE_INTEGER_C_MIN = 128, 276 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64 277 INLINE_INTEGER_C_MAX = 208, 278 INLINE_FLOATING_C_MIN = 240, 279 INLINE_FLOATING_C_MAX = 248, 280 LITERAL_CONST = 255, 281 VGPR_MIN = 256, 282 VGPR_MAX = 511 283 }; 284 285 } // namespace EncValues 286 } // namespace AMDGPU 287 288 namespace AMDGPU { 289 namespace CPol { 290 291 enum CPol { 292 GLC = 1, 293 SLC = 2, 294 DLC = 4, 295 SCC = 16, 296 ALL = GLC | SLC | DLC | SCC 297 }; 298 299 } // namespace CPol 300 301 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. 302 303 enum Id { // Message ID, width(4) [3:0]. 304 ID_UNKNOWN_ = -1, 305 ID_INTERRUPT = 1, 306 ID_GS = 2, 307 ID_GS_DONE = 3, 308 ID_SAVEWAVE = 4, // added in GFX8 309 ID_STALL_WAVE_GEN = 5, // added in GFX9 310 ID_HALT_WAVES = 6, // added in GFX9 311 ID_ORDERED_PS_DONE = 7, // added in GFX9 312 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10 313 ID_GS_ALLOC_REQ = 9, // added in GFX9 314 ID_GET_DOORBELL = 10, // added in GFX9 315 ID_GET_DDID = 11, // added in GFX10 316 ID_SYSMSG = 15, 317 ID_GAPS_LAST_, // Indicate that sequence has gaps. 318 ID_GAPS_FIRST_ = ID_INTERRUPT, 319 ID_SHIFT_ = 0, 320 ID_WIDTH_ = 4, 321 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 322 }; 323 324 enum Op { // Both GS and SYS operation IDs. 325 OP_UNKNOWN_ = -1, 326 OP_SHIFT_ = 4, 327 OP_NONE_ = 0, 328 // Bits used for operation encoding 329 OP_WIDTH_ = 3, 330 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_), 331 // GS operations are encoded in bits 5:4 332 OP_GS_NOP = 0, 333 OP_GS_CUT = 1, 334 OP_GS_EMIT = 2, 335 OP_GS_EMIT_CUT = 3, 336 OP_GS_LAST_, 337 OP_GS_FIRST_ = OP_GS_NOP, 338 // SYS operations are encoded in bits 6:4 339 OP_SYS_ECC_ERR_INTERRUPT = 1, 340 OP_SYS_REG_RD = 2, 341 OP_SYS_HOST_TRAP_ACK = 3, 342 OP_SYS_TTRACE_PC = 4, 343 OP_SYS_LAST_, 344 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT, 345 }; 346 347 enum StreamId : unsigned { // Stream ID, (2) [9:8]. 348 STREAM_ID_NONE_ = 0, 349 STREAM_ID_DEFAULT_ = 0, 350 STREAM_ID_LAST_ = 4, 351 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_, 352 STREAM_ID_SHIFT_ = 8, 353 STREAM_ID_WIDTH_= 2, 354 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_) 355 }; 356 357 } // namespace SendMsg 358 359 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. 360 361 enum Id { // HwRegCode, (6) [5:0] 362 ID_UNKNOWN_ = -1, 363 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined. 364 ID_MODE = 1, 365 ID_STATUS = 2, 366 ID_TRAPSTS = 3, 367 ID_HW_ID = 4, 368 ID_GPR_ALLOC = 5, 369 ID_LDS_ALLOC = 6, 370 ID_IB_STS = 7, 371 ID_MEM_BASES = 15, 372 ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES, 373 ID_TBA_LO = 16, 374 ID_SYMBOLIC_FIRST_GFX10_ = ID_TBA_LO, 375 ID_TBA_HI = 17, 376 ID_TMA_LO = 18, 377 ID_TMA_HI = 19, 378 ID_FLAT_SCR_LO = 20, 379 ID_FLAT_SCR_HI = 21, 380 ID_XNACK_MASK = 22, 381 ID_POPS_PACKER = 25, 382 ID_SHADER_CYCLES = 29, 383 ID_SYMBOLIC_FIRST_GFX1030_ = ID_SHADER_CYCLES, 384 ID_SYMBOLIC_LAST_ = 30, 385 ID_SHIFT_ = 0, 386 ID_WIDTH_ = 6, 387 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 388 }; 389 390 enum Offset : unsigned { // Offset, (5) [10:6] 391 OFFSET_DEFAULT_ = 0, 392 OFFSET_SHIFT_ = 6, 393 OFFSET_WIDTH_ = 5, 394 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_), 395 396 OFFSET_MEM_VIOL = 8, 397 398 OFFSET_SRC_SHARED_BASE = 16, 399 OFFSET_SRC_PRIVATE_BASE = 0 400 }; 401 402 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11] 403 WIDTH_M1_DEFAULT_ = 31, 404 WIDTH_M1_SHIFT_ = 11, 405 WIDTH_M1_WIDTH_ = 5, 406 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_), 407 408 WIDTH_M1_SRC_SHARED_BASE = 15, 409 WIDTH_M1_SRC_PRIVATE_BASE = 15 410 }; 411 412 // Some values from WidthMinusOne mapped into Width domain. 413 enum Width : unsigned { 414 WIDTH_DEFAULT_ = WIDTH_M1_DEFAULT_ + 1, 415 }; 416 417 enum ModeRegisterMasks : uint32_t { 418 FP_ROUND_MASK = 0xf << 0, // Bits 0..3 419 FP_DENORM_MASK = 0xf << 4, // Bits 4..7 420 DX10_CLAMP_MASK = 1 << 8, 421 IEEE_MODE_MASK = 1 << 9, 422 LOD_CLAMP_MASK = 1 << 10, 423 DEBUG_MASK = 1 << 11, 424 425 // EXCP_EN fields. 426 EXCP_EN_INVALID_MASK = 1 << 12, 427 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13, 428 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14, 429 EXCP_EN_OVERFLOW_MASK = 1 << 15, 430 EXCP_EN_UNDERFLOW_MASK = 1 << 16, 431 EXCP_EN_INEXACT_MASK = 1 << 17, 432 EXCP_EN_INT_DIV0_MASK = 1 << 18, 433 434 GPR_IDX_EN_MASK = 1 << 27, 435 VSKIP_MASK = 1 << 28, 436 CSP_MASK = 0x7u << 29 // Bits 29..31 437 }; 438 439 } // namespace Hwreg 440 441 namespace MTBUFFormat { 442 443 enum DataFormat : int64_t { 444 DFMT_INVALID = 0, 445 DFMT_8, 446 DFMT_16, 447 DFMT_8_8, 448 DFMT_32, 449 DFMT_16_16, 450 DFMT_10_11_11, 451 DFMT_11_11_10, 452 DFMT_10_10_10_2, 453 DFMT_2_10_10_10, 454 DFMT_8_8_8_8, 455 DFMT_32_32, 456 DFMT_16_16_16_16, 457 DFMT_32_32_32, 458 DFMT_32_32_32_32, 459 DFMT_RESERVED_15, 460 461 DFMT_MIN = DFMT_INVALID, 462 DFMT_MAX = DFMT_RESERVED_15, 463 464 DFMT_UNDEF = -1, 465 DFMT_DEFAULT = DFMT_8, 466 467 DFMT_SHIFT = 0, 468 DFMT_MASK = 0xF 469 }; 470 471 enum NumFormat : int64_t { 472 NFMT_UNORM = 0, 473 NFMT_SNORM, 474 NFMT_USCALED, 475 NFMT_SSCALED, 476 NFMT_UINT, 477 NFMT_SINT, 478 NFMT_RESERVED_6, // VI and GFX9 479 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only 480 NFMT_FLOAT, 481 482 NFMT_MIN = NFMT_UNORM, 483 NFMT_MAX = NFMT_FLOAT, 484 485 NFMT_UNDEF = -1, 486 NFMT_DEFAULT = NFMT_UNORM, 487 488 NFMT_SHIFT = 4, 489 NFMT_MASK = 7 490 }; 491 492 enum MergedFormat : int64_t { 493 DFMT_NFMT_UNDEF = -1, 494 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) | 495 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT), 496 497 498 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT), 499 500 DFMT_NFMT_MAX = DFMT_NFMT_MASK 501 }; 502 503 enum UnifiedFormat : int64_t { 504 UFMT_INVALID = 0, 505 506 UFMT_8_UNORM, 507 UFMT_8_SNORM, 508 UFMT_8_USCALED, 509 UFMT_8_SSCALED, 510 UFMT_8_UINT, 511 UFMT_8_SINT, 512 513 UFMT_16_UNORM, 514 UFMT_16_SNORM, 515 UFMT_16_USCALED, 516 UFMT_16_SSCALED, 517 UFMT_16_UINT, 518 UFMT_16_SINT, 519 UFMT_16_FLOAT, 520 521 UFMT_8_8_UNORM, 522 UFMT_8_8_SNORM, 523 UFMT_8_8_USCALED, 524 UFMT_8_8_SSCALED, 525 UFMT_8_8_UINT, 526 UFMT_8_8_SINT, 527 528 UFMT_32_UINT, 529 UFMT_32_SINT, 530 UFMT_32_FLOAT, 531 532 UFMT_16_16_UNORM, 533 UFMT_16_16_SNORM, 534 UFMT_16_16_USCALED, 535 UFMT_16_16_SSCALED, 536 UFMT_16_16_UINT, 537 UFMT_16_16_SINT, 538 UFMT_16_16_FLOAT, 539 540 UFMT_10_11_11_UNORM, 541 UFMT_10_11_11_SNORM, 542 UFMT_10_11_11_USCALED, 543 UFMT_10_11_11_SSCALED, 544 UFMT_10_11_11_UINT, 545 UFMT_10_11_11_SINT, 546 UFMT_10_11_11_FLOAT, 547 548 UFMT_11_11_10_UNORM, 549 UFMT_11_11_10_SNORM, 550 UFMT_11_11_10_USCALED, 551 UFMT_11_11_10_SSCALED, 552 UFMT_11_11_10_UINT, 553 UFMT_11_11_10_SINT, 554 UFMT_11_11_10_FLOAT, 555 556 UFMT_10_10_10_2_UNORM, 557 UFMT_10_10_10_2_SNORM, 558 UFMT_10_10_10_2_USCALED, 559 UFMT_10_10_10_2_SSCALED, 560 UFMT_10_10_10_2_UINT, 561 UFMT_10_10_10_2_SINT, 562 563 UFMT_2_10_10_10_UNORM, 564 UFMT_2_10_10_10_SNORM, 565 UFMT_2_10_10_10_USCALED, 566 UFMT_2_10_10_10_SSCALED, 567 UFMT_2_10_10_10_UINT, 568 UFMT_2_10_10_10_SINT, 569 570 UFMT_8_8_8_8_UNORM, 571 UFMT_8_8_8_8_SNORM, 572 UFMT_8_8_8_8_USCALED, 573 UFMT_8_8_8_8_SSCALED, 574 UFMT_8_8_8_8_UINT, 575 UFMT_8_8_8_8_SINT, 576 577 UFMT_32_32_UINT, 578 UFMT_32_32_SINT, 579 UFMT_32_32_FLOAT, 580 581 UFMT_16_16_16_16_UNORM, 582 UFMT_16_16_16_16_SNORM, 583 UFMT_16_16_16_16_USCALED, 584 UFMT_16_16_16_16_SSCALED, 585 UFMT_16_16_16_16_UINT, 586 UFMT_16_16_16_16_SINT, 587 UFMT_16_16_16_16_FLOAT, 588 589 UFMT_32_32_32_UINT, 590 UFMT_32_32_32_SINT, 591 UFMT_32_32_32_FLOAT, 592 UFMT_32_32_32_32_UINT, 593 UFMT_32_32_32_32_SINT, 594 UFMT_32_32_32_32_FLOAT, 595 596 UFMT_FIRST = UFMT_INVALID, 597 UFMT_LAST = UFMT_32_32_32_32_FLOAT, 598 599 UFMT_MAX = 127, 600 601 UFMT_UNDEF = -1, 602 UFMT_DEFAULT = UFMT_8_UNORM 603 }; 604 605 } // namespace MTBUFFormat 606 607 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32. 608 609 enum Id : unsigned { // id of symbolic names 610 ID_QUAD_PERM = 0, 611 ID_BITMASK_PERM, 612 ID_SWAP, 613 ID_REVERSE, 614 ID_BROADCAST 615 }; 616 617 enum EncBits : unsigned { 618 619 // swizzle mode encodings 620 621 QUAD_PERM_ENC = 0x8000, 622 QUAD_PERM_ENC_MASK = 0xFF00, 623 624 BITMASK_PERM_ENC = 0x0000, 625 BITMASK_PERM_ENC_MASK = 0x8000, 626 627 // QUAD_PERM encodings 628 629 LANE_MASK = 0x3, 630 LANE_MAX = LANE_MASK, 631 LANE_SHIFT = 2, 632 LANE_NUM = 4, 633 634 // BITMASK_PERM encodings 635 636 BITMASK_MASK = 0x1F, 637 BITMASK_MAX = BITMASK_MASK, 638 BITMASK_WIDTH = 5, 639 640 BITMASK_AND_SHIFT = 0, 641 BITMASK_OR_SHIFT = 5, 642 BITMASK_XOR_SHIFT = 10 643 }; 644 645 } // namespace Swizzle 646 647 namespace SDWA { 648 649 enum SdwaSel : unsigned { 650 BYTE_0 = 0, 651 BYTE_1 = 1, 652 BYTE_2 = 2, 653 BYTE_3 = 3, 654 WORD_0 = 4, 655 WORD_1 = 5, 656 DWORD = 6, 657 }; 658 659 enum DstUnused : unsigned { 660 UNUSED_PAD = 0, 661 UNUSED_SEXT = 1, 662 UNUSED_PRESERVE = 2, 663 }; 664 665 enum SDWA9EncValues : unsigned { 666 SRC_SGPR_MASK = 0x100, 667 SRC_VGPR_MASK = 0xFF, 668 VOPC_DST_VCC_MASK = 0x80, 669 VOPC_DST_SGPR_MASK = 0x7F, 670 671 SRC_VGPR_MIN = 0, 672 SRC_VGPR_MAX = 255, 673 SRC_SGPR_MIN = 256, 674 SRC_SGPR_MAX_SI = 357, 675 SRC_SGPR_MAX_GFX10 = 361, 676 SRC_TTMP_MIN = 364, 677 SRC_TTMP_MAX = 379, 678 }; 679 680 } // namespace SDWA 681 682 namespace DPP { 683 684 // clang-format off 685 enum DppCtrl : unsigned { 686 QUAD_PERM_FIRST = 0, 687 QUAD_PERM_ID = 0xE4, // identity permutation 688 QUAD_PERM_LAST = 0xFF, 689 DPP_UNUSED1 = 0x100, 690 ROW_SHL0 = 0x100, 691 ROW_SHL_FIRST = 0x101, 692 ROW_SHL_LAST = 0x10F, 693 DPP_UNUSED2 = 0x110, 694 ROW_SHR0 = 0x110, 695 ROW_SHR_FIRST = 0x111, 696 ROW_SHR_LAST = 0x11F, 697 DPP_UNUSED3 = 0x120, 698 ROW_ROR0 = 0x120, 699 ROW_ROR_FIRST = 0x121, 700 ROW_ROR_LAST = 0x12F, 701 WAVE_SHL1 = 0x130, 702 DPP_UNUSED4_FIRST = 0x131, 703 DPP_UNUSED4_LAST = 0x133, 704 WAVE_ROL1 = 0x134, 705 DPP_UNUSED5_FIRST = 0x135, 706 DPP_UNUSED5_LAST = 0x137, 707 WAVE_SHR1 = 0x138, 708 DPP_UNUSED6_FIRST = 0x139, 709 DPP_UNUSED6_LAST = 0x13B, 710 WAVE_ROR1 = 0x13C, 711 DPP_UNUSED7_FIRST = 0x13D, 712 DPP_UNUSED7_LAST = 0x13F, 713 ROW_MIRROR = 0x140, 714 ROW_HALF_MIRROR = 0x141, 715 BCAST15 = 0x142, 716 BCAST31 = 0x143, 717 DPP_UNUSED8_FIRST = 0x144, 718 DPP_UNUSED8_LAST = 0x14F, 719 ROW_NEWBCAST_FIRST= 0x150, 720 ROW_NEWBCAST_LAST = 0x15F, 721 ROW_SHARE0 = 0x150, 722 ROW_SHARE_FIRST = 0x150, 723 ROW_SHARE_LAST = 0x15F, 724 ROW_XMASK0 = 0x160, 725 ROW_XMASK_FIRST = 0x160, 726 ROW_XMASK_LAST = 0x16F, 727 DPP_LAST = ROW_XMASK_LAST 728 }; 729 // clang-format on 730 731 enum DppFiMode { 732 DPP_FI_0 = 0, 733 DPP_FI_1 = 1, 734 DPP8_FI_0 = 0xE9, 735 DPP8_FI_1 = 0xEA, 736 }; 737 738 } // namespace DPP 739 740 namespace Exp { 741 742 enum Target : unsigned { 743 ET_MRT0 = 0, 744 ET_MRT7 = 7, 745 ET_MRTZ = 8, 746 ET_NULL = 9, 747 ET_POS0 = 12, 748 ET_POS3 = 15, 749 ET_POS4 = 16, // GFX10+ 750 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget 751 ET_PRIM = 20, // GFX10+ 752 ET_PARAM0 = 32, 753 ET_PARAM31 = 63, 754 755 ET_NULL_MAX_IDX = 0, 756 ET_MRTZ_MAX_IDX = 0, 757 ET_PRIM_MAX_IDX = 0, 758 ET_MRT_MAX_IDX = 7, 759 ET_POS_MAX_IDX = 4, 760 ET_PARAM_MAX_IDX = 31, 761 762 ET_INVALID = 255, 763 }; 764 765 } // namespace Exp 766 767 namespace VOP3PEncoding { 768 769 enum OpSel : uint64_t { 770 OP_SEL_HI_0 = UINT64_C(1) << 59, 771 OP_SEL_HI_1 = UINT64_C(1) << 60, 772 OP_SEL_HI_2 = UINT64_C(1) << 14, 773 }; 774 775 } // namespace VOP3PEncoding 776 777 } // namespace AMDGPU 778 779 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 780 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 781 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 782 #define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25) 783 #define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1) 784 #define C_00B028_MEM_ORDERED 0xFDFFFFFF 785 786 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 787 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 788 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 789 #define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27) 790 #define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1) 791 #define C_00B128_MEM_ORDERED 0xF7FFFFFF 792 793 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 794 #define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27) 795 #define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1) 796 #define C_00B228_WGP_MODE 0xF7FFFFFF 797 #define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25) 798 #define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1) 799 #define C_00B228_MEM_ORDERED 0xFDFFFFFF 800 801 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328 802 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428 803 #define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26) 804 #define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1) 805 #define C_00B428_WGP_MODE 0xFBFFFFFF 806 #define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24) 807 #define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1) 808 #define C_00B428_MEM_ORDERED 0xFEFFFFFF 809 810 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528 811 812 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 813 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 814 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 815 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 816 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 817 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 818 #define C_00B84C_USER_SGPR 0xFFFFFFC1 819 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6) 820 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1) 821 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF 822 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 823 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 824 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 825 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 826 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 827 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 828 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 829 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 830 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 831 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 832 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 833 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 834 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 835 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 836 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 837 /* CIK */ 838 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 839 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 840 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 841 /* */ 842 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 843 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 844 #define C_00B84C_LDS_SIZE 0xFF007FFF 845 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 846 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 847 #define C_00B84C_EXCP_EN 848 849 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 850 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 851 852 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 853 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 854 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 855 #define C_00B848_VGPRS 0xFFFFFFC0 856 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 857 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 858 #define C_00B848_SGPRS 0xFFFFFC3F 859 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 860 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 861 #define C_00B848_PRIORITY 0xFFFFF3FF 862 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 863 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 864 #define C_00B848_FLOAT_MODE 0xFFF00FFF 865 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 866 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 867 #define C_00B848_PRIV 0xFFEFFFFF 868 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 869 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 870 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 871 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 872 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 873 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 874 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 875 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 876 #define C_00B848_IEEE_MODE 0xFF7FFFFF 877 #define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29) 878 #define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1) 879 #define C_00B848_WGP_MODE 0xDFFFFFFF 880 #define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30) 881 #define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1) 882 #define C_00B848_MEM_ORDERED 0xBFFFFFFF 883 #define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31) 884 #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1) 885 #define C_00B848_FWD_PROGRESS 0x7FFFFFFF 886 887 888 // Helpers for setting FLOAT_MODE 889 #define FP_ROUND_ROUND_TO_NEAREST 0 890 #define FP_ROUND_ROUND_TO_INF 1 891 #define FP_ROUND_ROUND_TO_NEGINF 2 892 #define FP_ROUND_ROUND_TO_ZERO 3 893 894 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 895 // precision. 896 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 897 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 898 899 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 900 #define FP_DENORM_FLUSH_OUT 1 901 #define FP_DENORM_FLUSH_IN 2 902 #define FP_DENORM_FLUSH_NONE 3 903 904 905 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 906 // precision. 907 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 908 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 909 910 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 911 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) 912 913 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 914 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) 915 916 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54 917 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21) 918 #define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22) 919 #define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23) 920 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8 921 #define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15) 922 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800 923 #define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15) 924 925 #define R_SPILLED_SGPRS 0x4 926 #define R_SPILLED_VGPRS 0x8 927 } // End namespace llvm 928 929 #endif 930