1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #include "llvm/MC/MCInstrDesc.h" 11 12 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 13 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 14 15 namespace llvm { 16 17 namespace SIInstrFlags { 18 // This needs to be kept in sync with the field bits in InstSI. 19 enum : uint64_t { 20 // Low bits - basic encoding information. 21 SALU = 1 << 0, 22 VALU = 1 << 1, 23 24 // SALU instruction formats. 25 SOP1 = 1 << 2, 26 SOP2 = 1 << 3, 27 SOPC = 1 << 4, 28 SOPK = 1 << 5, 29 SOPP = 1 << 6, 30 31 // VALU instruction formats. 32 VOP1 = 1 << 7, 33 VOP2 = 1 << 8, 34 VOPC = 1 << 9, 35 36 // TODO: Should this be spilt into VOP3 a and b? 37 VOP3 = 1 << 10, 38 VOP3P = 1 << 12, 39 40 VINTRP = 1 << 13, 41 SDWA = 1 << 14, 42 DPP = 1 << 15, 43 44 // Memory instruction formats. 45 MUBUF = 1 << 16, 46 MTBUF = 1 << 17, 47 SMRD = 1 << 18, 48 MIMG = 1 << 19, 49 EXP = 1 << 20, 50 FLAT = 1 << 21, 51 DS = 1 << 22, 52 53 // Pseudo instruction formats. 54 VGPRSpill = 1 << 23, 55 SGPRSpill = 1 << 24, 56 57 // High bits - other information. 58 VM_CNT = UINT64_C(1) << 32, 59 EXP_CNT = UINT64_C(1) << 33, 60 LGKM_CNT = UINT64_C(1) << 34, 61 62 WQM = UINT64_C(1) << 35, 63 DisableWQM = UINT64_C(1) << 36, 64 Gather4 = UINT64_C(1) << 37, 65 SOPK_ZEXT = UINT64_C(1) << 38, 66 SCALAR_STORE = UINT64_C(1) << 39, 67 FIXED_SIZE = UINT64_C(1) << 40, 68 VOPAsmPrefer32Bit = UINT64_C(1) << 41, 69 VOP3_OPSEL = UINT64_C(1) << 42, 70 maybeAtomic = UINT64_C(1) << 43, 71 renamedInGFX9 = UINT64_C(1) << 44, 72 73 // Is a clamp on FP type. 74 FPClamp = UINT64_C(1) << 45, 75 76 // Is an integer clamp 77 IntClamp = UINT64_C(1) << 46, 78 79 // Clamps lo component of register. 80 ClampLo = UINT64_C(1) << 47, 81 82 // Clamps hi component of register. 83 // ClampLo and ClampHi set for packed clamp. 84 ClampHi = UINT64_C(1) << 48, 85 86 // Is a packed VOP3P instruction. 87 IsPacked = UINT64_C(1) << 49, 88 89 // Is a D16 buffer instruction. 90 D16Buf = UINT64_C(1) << 50, 91 92 // FLAT instruction accesses FLAT_GLBL or FLAT_SCRATCH segment. 93 IsNonFlatSeg = UINT64_C(1) << 51, 94 95 // Uses floating point double precision rounding mode 96 FPDPRounding = UINT64_C(1) << 52, 97 98 // Instruction is FP atomic. 99 FPAtomic = UINT64_C(1) << 53, 100 101 // Is a MFMA instruction. 102 IsMAI = UINT64_C(1) << 54 103 }; 104 105 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 106 // The result is true if any of these tests are true. 107 enum ClassFlags : unsigned { 108 S_NAN = 1 << 0, // Signaling NaN 109 Q_NAN = 1 << 1, // Quiet NaN 110 N_INFINITY = 1 << 2, // Negative infinity 111 N_NORMAL = 1 << 3, // Negative normal 112 N_SUBNORMAL = 1 << 4, // Negative subnormal 113 N_ZERO = 1 << 5, // Negative zero 114 P_ZERO = 1 << 6, // Positive zero 115 P_SUBNORMAL = 1 << 7, // Positive subnormal 116 P_NORMAL = 1 << 8, // Positive normal 117 P_INFINITY = 1 << 9 // Positive infinity 118 }; 119 } 120 121 namespace AMDGPU { 122 enum OperandType : unsigned { 123 /// Operands with register or 32-bit immediate 124 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, 125 OPERAND_REG_IMM_INT64, 126 OPERAND_REG_IMM_INT16, 127 OPERAND_REG_IMM_FP32, 128 OPERAND_REG_IMM_FP64, 129 OPERAND_REG_IMM_FP16, 130 OPERAND_REG_IMM_V2FP16, 131 OPERAND_REG_IMM_V2INT16, 132 133 /// Operands with register or inline constant 134 OPERAND_REG_INLINE_C_INT16, 135 OPERAND_REG_INLINE_C_INT32, 136 OPERAND_REG_INLINE_C_INT64, 137 OPERAND_REG_INLINE_C_FP16, 138 OPERAND_REG_INLINE_C_FP32, 139 OPERAND_REG_INLINE_C_FP64, 140 OPERAND_REG_INLINE_C_V2FP16, 141 OPERAND_REG_INLINE_C_V2INT16, 142 143 /// Operands with an AccVGPR register or inline constant 144 OPERAND_REG_INLINE_AC_INT16, 145 OPERAND_REG_INLINE_AC_INT32, 146 OPERAND_REG_INLINE_AC_FP16, 147 OPERAND_REG_INLINE_AC_FP32, 148 OPERAND_REG_INLINE_AC_V2FP16, 149 OPERAND_REG_INLINE_AC_V2INT16, 150 151 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, 152 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2INT16, 153 154 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, 155 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2INT16, 156 157 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16, 158 OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2INT16, 159 160 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, 161 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, 162 163 // Operand for source modifiers for VOP instructions 164 OPERAND_INPUT_MODS, 165 166 // Operand for SDWA instructions 167 OPERAND_SDWA_VOPC_DST, 168 169 /// Operand with 32-bit immediate that uses the constant bus. 170 OPERAND_KIMM32, 171 OPERAND_KIMM16 172 }; 173 } 174 175 // Input operand modifiers bit-masks 176 // NEG and SEXT share same bit-mask because they can't be set simultaneously. 177 namespace SISrcMods { 178 enum : unsigned { 179 NEG = 1 << 0, // Floating-point negate modifier 180 ABS = 1 << 1, // Floating-point absolute modifier 181 SEXT = 1 << 0, // Integer sign-extend modifier 182 NEG_HI = ABS, // Floating-point negate high packed component modifier. 183 OP_SEL_0 = 1 << 2, 184 OP_SEL_1 = 1 << 3, 185 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1) 186 }; 187 } 188 189 namespace SIOutMods { 190 enum : unsigned { 191 NONE = 0, 192 MUL2 = 1, 193 MUL4 = 2, 194 DIV2 = 3 195 }; 196 } 197 198 namespace AMDGPU { 199 namespace VGPRIndexMode { 200 201 enum Id : unsigned { // id of symbolic names 202 ID_SRC0 = 0, 203 ID_SRC1, 204 ID_SRC2, 205 ID_DST, 206 207 ID_MIN = ID_SRC0, 208 ID_MAX = ID_DST 209 }; 210 211 enum EncBits : unsigned { 212 OFF = 0, 213 SRC0_ENABLE = 1 << ID_SRC0, 214 SRC1_ENABLE = 1 << ID_SRC1, 215 SRC2_ENABLE = 1 << ID_SRC2, 216 DST_ENABLE = 1 << ID_DST, 217 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE 218 }; 219 220 } // namespace VGPRIndexMode 221 } // namespace AMDGPU 222 223 namespace AMDGPUAsmVariants { 224 enum : unsigned { 225 DEFAULT = 0, 226 VOP3 = 1, 227 SDWA = 2, 228 SDWA9 = 3, 229 DPP = 4 230 }; 231 } 232 233 namespace AMDGPU { 234 namespace EncValues { // Encoding values of enum9/8/7 operands 235 236 enum : unsigned { 237 SGPR_MIN = 0, 238 SGPR_MAX_SI = 101, 239 SGPR_MAX_GFX10 = 105, 240 TTMP_VI_MIN = 112, 241 TTMP_VI_MAX = 123, 242 TTMP_GFX9_GFX10_MIN = 108, 243 TTMP_GFX9_GFX10_MAX = 123, 244 INLINE_INTEGER_C_MIN = 128, 245 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64 246 INLINE_INTEGER_C_MAX = 208, 247 INLINE_FLOATING_C_MIN = 240, 248 INLINE_FLOATING_C_MAX = 248, 249 LITERAL_CONST = 255, 250 VGPR_MIN = 256, 251 VGPR_MAX = 511 252 }; 253 254 } // namespace EncValues 255 } // namespace AMDGPU 256 257 namespace AMDGPU { 258 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. 259 260 enum Id { // Message ID, width(4) [3:0]. 261 ID_UNKNOWN_ = -1, 262 ID_INTERRUPT = 1, 263 ID_GS, 264 ID_GS_DONE, 265 ID_GS_ALLOC_REQ = 9, 266 ID_GET_DOORBELL = 10, 267 ID_SYSMSG = 15, 268 ID_GAPS_LAST_, // Indicate that sequence has gaps. 269 ID_GAPS_FIRST_ = ID_INTERRUPT, 270 ID_SHIFT_ = 0, 271 ID_WIDTH_ = 4, 272 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 273 }; 274 275 enum Op { // Both GS and SYS operation IDs. 276 OP_UNKNOWN_ = -1, 277 OP_SHIFT_ = 4, 278 OP_NONE_ = 0, 279 // Bits used for operation encoding 280 OP_WIDTH_ = 3, 281 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_), 282 // GS operations are encoded in bits 5:4 283 OP_GS_NOP = 0, 284 OP_GS_CUT, 285 OP_GS_EMIT, 286 OP_GS_EMIT_CUT, 287 OP_GS_LAST_, 288 OP_GS_FIRST_ = OP_GS_NOP, 289 // SYS operations are encoded in bits 6:4 290 OP_SYS_ECC_ERR_INTERRUPT = 1, 291 OP_SYS_REG_RD, 292 OP_SYS_HOST_TRAP_ACK, 293 OP_SYS_TTRACE_PC, 294 OP_SYS_LAST_, 295 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT, 296 }; 297 298 enum StreamId : unsigned { // Stream ID, (2) [9:8]. 299 STREAM_ID_NONE_ = 0, 300 STREAM_ID_DEFAULT_ = 0, 301 STREAM_ID_LAST_ = 4, 302 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_, 303 STREAM_ID_SHIFT_ = 8, 304 STREAM_ID_WIDTH_= 2, 305 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_) 306 }; 307 308 } // namespace SendMsg 309 310 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. 311 312 enum Id { // HwRegCode, (6) [5:0] 313 ID_UNKNOWN_ = -1, 314 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined. 315 ID_MODE = 1, 316 ID_STATUS = 2, 317 ID_TRAPSTS = 3, 318 ID_HW_ID = 4, 319 ID_GPR_ALLOC = 5, 320 ID_LDS_ALLOC = 6, 321 ID_IB_STS = 7, 322 ID_MEM_BASES = 15, 323 ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES, 324 ID_TBA_LO = 16, 325 ID_SYMBOLIC_FIRST_GFX10_ = ID_TBA_LO, 326 ID_TBA_HI = 17, 327 ID_TMA_LO = 18, 328 ID_TMA_HI = 19, 329 ID_FLAT_SCR_LO = 20, 330 ID_FLAT_SCR_HI = 21, 331 ID_XNACK_MASK = 22, 332 ID_POPS_PACKER = 25, 333 ID_SYMBOLIC_LAST_ = 26, 334 ID_SHIFT_ = 0, 335 ID_WIDTH_ = 6, 336 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 337 }; 338 339 enum Offset : unsigned { // Offset, (5) [10:6] 340 OFFSET_DEFAULT_ = 0, 341 OFFSET_SHIFT_ = 6, 342 OFFSET_WIDTH_ = 5, 343 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_), 344 345 OFFSET_MEM_VIOL = 8, 346 347 OFFSET_SRC_SHARED_BASE = 16, 348 OFFSET_SRC_PRIVATE_BASE = 0 349 }; 350 351 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11] 352 WIDTH_M1_DEFAULT_ = 31, 353 WIDTH_M1_SHIFT_ = 11, 354 WIDTH_M1_WIDTH_ = 5, 355 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_), 356 357 WIDTH_M1_SRC_SHARED_BASE = 15, 358 WIDTH_M1_SRC_PRIVATE_BASE = 15 359 }; 360 361 // Some values from WidthMinusOne mapped into Width domain. 362 enum Width : unsigned { 363 WIDTH_DEFAULT_ = WIDTH_M1_DEFAULT_ + 1, 364 }; 365 366 } // namespace Hwreg 367 368 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32. 369 370 enum Id : unsigned { // id of symbolic names 371 ID_QUAD_PERM = 0, 372 ID_BITMASK_PERM, 373 ID_SWAP, 374 ID_REVERSE, 375 ID_BROADCAST 376 }; 377 378 enum EncBits : unsigned { 379 380 // swizzle mode encodings 381 382 QUAD_PERM_ENC = 0x8000, 383 QUAD_PERM_ENC_MASK = 0xFF00, 384 385 BITMASK_PERM_ENC = 0x0000, 386 BITMASK_PERM_ENC_MASK = 0x8000, 387 388 // QUAD_PERM encodings 389 390 LANE_MASK = 0x3, 391 LANE_MAX = LANE_MASK, 392 LANE_SHIFT = 2, 393 LANE_NUM = 4, 394 395 // BITMASK_PERM encodings 396 397 BITMASK_MASK = 0x1F, 398 BITMASK_MAX = BITMASK_MASK, 399 BITMASK_WIDTH = 5, 400 401 BITMASK_AND_SHIFT = 0, 402 BITMASK_OR_SHIFT = 5, 403 BITMASK_XOR_SHIFT = 10 404 }; 405 406 } // namespace Swizzle 407 408 namespace SDWA { 409 410 enum SdwaSel : unsigned { 411 BYTE_0 = 0, 412 BYTE_1 = 1, 413 BYTE_2 = 2, 414 BYTE_3 = 3, 415 WORD_0 = 4, 416 WORD_1 = 5, 417 DWORD = 6, 418 }; 419 420 enum DstUnused : unsigned { 421 UNUSED_PAD = 0, 422 UNUSED_SEXT = 1, 423 UNUSED_PRESERVE = 2, 424 }; 425 426 enum SDWA9EncValues : unsigned { 427 SRC_SGPR_MASK = 0x100, 428 SRC_VGPR_MASK = 0xFF, 429 VOPC_DST_VCC_MASK = 0x80, 430 VOPC_DST_SGPR_MASK = 0x7F, 431 432 SRC_VGPR_MIN = 0, 433 SRC_VGPR_MAX = 255, 434 SRC_SGPR_MIN = 256, 435 SRC_SGPR_MAX_SI = 357, 436 SRC_SGPR_MAX_GFX10 = 361, 437 SRC_TTMP_MIN = 364, 438 SRC_TTMP_MAX = 379, 439 }; 440 441 } // namespace SDWA 442 443 namespace DPP { 444 445 enum DppCtrl : unsigned { 446 QUAD_PERM_FIRST = 0, 447 QUAD_PERM_LAST = 0xFF, 448 DPP_UNUSED1 = 0x100, 449 ROW_SHL0 = 0x100, 450 ROW_SHL_FIRST = 0x101, 451 ROW_SHL_LAST = 0x10F, 452 DPP_UNUSED2 = 0x110, 453 ROW_SHR0 = 0x110, 454 ROW_SHR_FIRST = 0x111, 455 ROW_SHR_LAST = 0x11F, 456 DPP_UNUSED3 = 0x120, 457 ROW_ROR0 = 0x120, 458 ROW_ROR_FIRST = 0x121, 459 ROW_ROR_LAST = 0x12F, 460 WAVE_SHL1 = 0x130, 461 DPP_UNUSED4_FIRST = 0x131, 462 DPP_UNUSED4_LAST = 0x133, 463 WAVE_ROL1 = 0x134, 464 DPP_UNUSED5_FIRST = 0x135, 465 DPP_UNUSED5_LAST = 0x137, 466 WAVE_SHR1 = 0x138, 467 DPP_UNUSED6_FIRST = 0x139, 468 DPP_UNUSED6_LAST = 0x13B, 469 WAVE_ROR1 = 0x13C, 470 DPP_UNUSED7_FIRST = 0x13D, 471 DPP_UNUSED7_LAST = 0x13F, 472 ROW_MIRROR = 0x140, 473 ROW_HALF_MIRROR = 0x141, 474 BCAST15 = 0x142, 475 BCAST31 = 0x143, 476 DPP_UNUSED8_FIRST = 0x144, 477 DPP_UNUSED8_LAST = 0x14F, 478 ROW_SHARE_FIRST = 0x150, 479 ROW_SHARE_LAST = 0x15F, 480 ROW_XMASK_FIRST = 0x160, 481 ROW_XMASK_LAST = 0x16F, 482 DPP_LAST = ROW_XMASK_LAST 483 }; 484 485 enum DppFiMode { 486 DPP_FI_0 = 0, 487 DPP_FI_1 = 1, 488 DPP8_FI_0 = 0xE9, 489 DPP8_FI_1 = 0xEA, 490 }; 491 492 } // namespace DPP 493 } // namespace AMDGPU 494 495 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 496 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 497 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 498 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 499 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 500 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328 501 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428 502 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528 503 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 504 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 505 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 506 507 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 508 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 509 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 510 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 511 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 512 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 513 #define C_00B84C_USER_SGPR 0xFFFFFFC1 514 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6) 515 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1) 516 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF 517 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 518 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 519 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 520 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 521 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 522 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 523 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 524 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 525 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 526 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 527 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 528 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 529 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 530 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 531 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 532 /* CIK */ 533 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 534 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 535 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 536 /* */ 537 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 538 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 539 #define C_00B84C_LDS_SIZE 0xFF007FFF 540 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 541 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 542 #define C_00B84C_EXCP_EN 543 544 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 545 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 546 547 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 548 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 549 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 550 #define C_00B848_VGPRS 0xFFFFFFC0 551 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 552 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 553 #define C_00B848_SGPRS 0xFFFFFC3F 554 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 555 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 556 #define C_00B848_PRIORITY 0xFFFFF3FF 557 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 558 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 559 #define C_00B848_FLOAT_MODE 0xFFF00FFF 560 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 561 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 562 #define C_00B848_PRIV 0xFFEFFFFF 563 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 564 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 565 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 566 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 567 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 568 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 569 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 570 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 571 #define C_00B848_IEEE_MODE 0xFF7FFFFF 572 #define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29) 573 #define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1) 574 #define C_00B848_WGP_MODE 0xDFFFFFFF 575 #define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30) 576 #define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1) 577 #define C_00B848_MEM_ORDERED 0xBFFFFFFF 578 #define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31) 579 #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1) 580 #define C_00B848_FWD_PROGRESS 0x7FFFFFFF 581 582 583 // Helpers for setting FLOAT_MODE 584 #define FP_ROUND_ROUND_TO_NEAREST 0 585 #define FP_ROUND_ROUND_TO_INF 1 586 #define FP_ROUND_ROUND_TO_NEGINF 2 587 #define FP_ROUND_ROUND_TO_ZERO 3 588 589 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 590 // precision. 591 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 592 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 593 594 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 595 #define FP_DENORM_FLUSH_OUT 1 596 #define FP_DENORM_FLUSH_IN 2 597 #define FP_DENORM_FLUSH_NONE 3 598 599 600 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 601 // precision. 602 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 603 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 604 605 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 606 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) 607 608 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 609 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) 610 611 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54 612 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21) 613 #define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22) 614 #define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23) 615 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8 616 #define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15) 617 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800 618 #define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15) 619 620 #define R_SPILLED_SGPRS 0x4 621 #define R_SPILLED_VGPRS 0x8 622 } // End namespace llvm 623 624 #endif 625