1349cc55cSDimitry Andric //===- R600TargetTransformInfo.h - R600 specific TTI --------*- C++ -*-===// 2349cc55cSDimitry Andric // 3349cc55cSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4349cc55cSDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5349cc55cSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6349cc55cSDimitry Andric // 7349cc55cSDimitry Andric //===----------------------------------------------------------------------===// 8349cc55cSDimitry Andric // 9349cc55cSDimitry Andric /// \file 10349cc55cSDimitry Andric /// This file a TargetTransformInfo::Concept conforming object specific to the 11349cc55cSDimitry Andric /// R600 target machine. It uses the target's detailed information to 12349cc55cSDimitry Andric /// provide more precise answers to certain TTI queries, while letting the 13349cc55cSDimitry Andric /// target independent and default TTI implementations handle the rest. 14349cc55cSDimitry Andric // 15349cc55cSDimitry Andric //===----------------------------------------------------------------------===// 16349cc55cSDimitry Andric 17349cc55cSDimitry Andric #ifndef LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H 18349cc55cSDimitry Andric #define LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H 19349cc55cSDimitry Andric 20349cc55cSDimitry Andric #include "AMDGPUTargetTransformInfo.h" 21349cc55cSDimitry Andric #include "llvm/CodeGen/BasicTTIImpl.h" 22349cc55cSDimitry Andric 23349cc55cSDimitry Andric namespace llvm { 24349cc55cSDimitry Andric 25349cc55cSDimitry Andric class R600Subtarget; 26349cc55cSDimitry Andric class AMDGPUTargetLowering; 27349cc55cSDimitry Andric 28349cc55cSDimitry Andric class R600TTIImpl final : public BasicTTIImplBase<R600TTIImpl> { 29349cc55cSDimitry Andric using BaseT = BasicTTIImplBase<R600TTIImpl>; 30349cc55cSDimitry Andric using TTI = TargetTransformInfo; 31349cc55cSDimitry Andric 32349cc55cSDimitry Andric friend BaseT; 33349cc55cSDimitry Andric 34349cc55cSDimitry Andric const R600Subtarget *ST; 35349cc55cSDimitry Andric const AMDGPUTargetLowering *TLI; 36349cc55cSDimitry Andric AMDGPUTTIImpl CommonTTI; 37349cc55cSDimitry Andric 38349cc55cSDimitry Andric public: 39349cc55cSDimitry Andric explicit R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F); 40349cc55cSDimitry Andric getST()41349cc55cSDimitry Andric const R600Subtarget *getST() const { return ST; } getTLI()42349cc55cSDimitry Andric const AMDGPUTargetLowering *getTLI() const { return TLI; } 43349cc55cSDimitry Andric 44349cc55cSDimitry Andric void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, 45349cc55cSDimitry Andric TTI::UnrollingPreferences &UP, 46349cc55cSDimitry Andric OptimizationRemarkEmitter *ORE); 47349cc55cSDimitry Andric void getPeelingPreferences(Loop *L, ScalarEvolution &SE, 48349cc55cSDimitry Andric TTI::PeelingPreferences &PP); 49349cc55cSDimitry Andric unsigned getHardwareNumberOfRegisters(bool Vec) const; 50349cc55cSDimitry Andric unsigned getNumberOfRegisters(bool Vec) const; 51349cc55cSDimitry Andric TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const; 52349cc55cSDimitry Andric unsigned getMinVectorRegisterBitWidth() const; 53349cc55cSDimitry Andric unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const; 54349cc55cSDimitry Andric bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment, 55349cc55cSDimitry Andric unsigned AddrSpace) const; 56349cc55cSDimitry Andric bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, 57349cc55cSDimitry Andric unsigned AddrSpace) const; 58349cc55cSDimitry Andric bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, 59349cc55cSDimitry Andric unsigned AddrSpace) const; 60*06c3fb27SDimitry Andric unsigned getMaxInterleaveFactor(ElementCount VF); 61349cc55cSDimitry Andric InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, 62349cc55cSDimitry Andric const Instruction *I = nullptr); 63bdd1243dSDimitry Andric using BaseT::getVectorInstrCost; 64349cc55cSDimitry Andric InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, 65bdd1243dSDimitry Andric TTI::TargetCostKind CostKind, 66bdd1243dSDimitry Andric unsigned Index, Value *Op0, Value *Op1); 67349cc55cSDimitry Andric }; 68349cc55cSDimitry Andric 69349cc55cSDimitry Andric } // end namespace llvm 70349cc55cSDimitry Andric 71349cc55cSDimitry Andric #endif // LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H 72