1 //=====-- R600Subtarget.h - Define Subtarget for AMDGPU R600 ----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //==-----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// AMDGPU R600 specific subclass of TargetSubtarget. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H 15 #define LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H 16 17 #include "AMDGPUSubtarget.h" 18 #include "R600FrameLowering.h" 19 #include "R600ISelLowering.h" 20 #include "R600InstrInfo.h" 21 #include "Utils/AMDGPUBaseInfo.h" 22 #include "llvm/CodeGen/SelectionDAGTargetInfo.h" 23 24 namespace llvm { 25 26 class MCInstrInfo; 27 28 } // namespace llvm 29 30 #define GET_SUBTARGETINFO_HEADER 31 #include "R600GenSubtargetInfo.inc" 32 33 namespace llvm { 34 35 class R600Subtarget final : public R600GenSubtargetInfo, 36 public AMDGPUSubtarget { 37 private: 38 R600InstrInfo InstrInfo; 39 R600FrameLowering FrameLowering; 40 bool FMA; 41 bool CaymanISA; 42 bool CFALUBug; 43 bool HasVertexCache; 44 bool R600ALUInst; 45 bool FP64; 46 short TexVTXClauseSize; 47 Generation Gen; 48 R600TargetLowering TLInfo; 49 InstrItineraryData InstrItins; 50 SelectionDAGTargetInfo TSInfo; 51 52 public: 53 R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS, 54 const TargetMachine &TM); 55 56 const R600InstrInfo *getInstrInfo() const override { return &InstrInfo; } 57 58 const R600FrameLowering *getFrameLowering() const override { 59 return &FrameLowering; 60 } 61 62 const R600TargetLowering *getTargetLowering() const override { 63 return &TLInfo; 64 } 65 66 const R600RegisterInfo *getRegisterInfo() const override { 67 return &InstrInfo.getRegisterInfo(); 68 } 69 70 const InstrItineraryData *getInstrItineraryData() const override { 71 return &InstrItins; 72 } 73 74 // Nothing implemented, just prevent crashes on use. 75 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { 76 return &TSInfo; 77 } 78 79 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); 80 81 Generation getGeneration() const { 82 return Gen; 83 } 84 85 Align getStackAlignment() const { return Align(4); } 86 87 R600Subtarget &initializeSubtargetDependencies(const Triple &TT, 88 StringRef GPU, StringRef FS); 89 90 bool hasBFE() const { 91 return (getGeneration() >= EVERGREEN); 92 } 93 94 bool hasBFI() const { 95 return (getGeneration() >= EVERGREEN); 96 } 97 98 bool hasBCNT(unsigned Size) const { 99 if (Size == 32) 100 return (getGeneration() >= EVERGREEN); 101 102 return false; 103 } 104 105 bool hasBORROW() const { 106 return (getGeneration() >= EVERGREEN); 107 } 108 109 bool hasCARRY() const { 110 return (getGeneration() >= EVERGREEN); 111 } 112 113 bool hasCaymanISA() const { 114 return CaymanISA; 115 } 116 117 bool hasFFBL() const { 118 return (getGeneration() >= EVERGREEN); 119 } 120 121 bool hasFFBH() const { 122 return (getGeneration() >= EVERGREEN); 123 } 124 125 bool hasFMA() const { return FMA; } 126 127 bool hasCFAluBug() const { return CFALUBug; } 128 129 bool hasVertexCache() const { return HasVertexCache; } 130 131 short getTexVTXClauseSize() const { return TexVTXClauseSize; } 132 133 bool enableMachineScheduler() const override { 134 return true; 135 } 136 137 bool enableSubRegLiveness() const override { 138 return true; 139 } 140 141 /// \returns Maximum number of work groups per compute unit supported by the 142 /// subtarget and limited by given \p FlatWorkGroupSize. 143 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override { 144 return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(this, FlatWorkGroupSize); 145 } 146 147 /// \returns Minimum flat work group size supported by the subtarget. 148 unsigned getMinFlatWorkGroupSize() const override { 149 return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(this); 150 } 151 152 /// \returns Maximum flat work group size supported by the subtarget. 153 unsigned getMaxFlatWorkGroupSize() const override { 154 return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(this); 155 } 156 157 /// \returns Number of waves per execution unit required to support the given 158 /// \p FlatWorkGroupSize. 159 unsigned 160 getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize) const override { 161 return AMDGPU::IsaInfo::getWavesPerEUForWorkGroup(this, FlatWorkGroupSize); 162 } 163 164 /// \returns Minimum number of waves per execution unit supported by the 165 /// subtarget. 166 unsigned getMinWavesPerEU() const override { 167 return AMDGPU::IsaInfo::getMinWavesPerEU(this); 168 } 169 }; 170 171 } // end namespace llvm 172 173 #endif // LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H 174