1//===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction 10// slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS. For cayman cards, the TRANS 11// slot has been removed. 12// 13//===----------------------------------------------------------------------===// 14 15 16def ALU_X : FuncUnit; 17def ALU_Y : FuncUnit; 18def ALU_Z : FuncUnit; 19def ALU_W : FuncUnit; 20def TRANS : FuncUnit; 21 22def AnyALU : InstrItinClass; 23def VecALU : InstrItinClass; 24def TransALU : InstrItinClass; 25def XALU : InstrItinClass; 26 27def R600_VLIW5_Itin : ProcessorItineraries < 28 [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS, ALU_NULL], 29 [], 30 [ 31 InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS]>]>, 32 InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>, 33 InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>, 34 InstrItinData<XALU, [InstrStage<1, [ALU_X]>]>, 35 InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]> 36 ] 37>; 38 39def R600_VLIW4_Itin : ProcessorItineraries < 40 [ALU_X, ALU_Y, ALU_Z, ALU_W, ALU_NULL], 41 [], 42 [ 43 InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>, 44 InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>, 45 InstrItinData<TransALU, [InstrStage<1, [ALU_NULL]>]>, 46 InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]> 47 ] 48>; 49