10b57cec5SDimitry Andric //===-- R600MachineScheduler.h - R600 Scheduler Interface -*- C++ -*-------===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric /// \file 100b57cec5SDimitry Andric /// R600 Machine Scheduler interface 110b57cec5SDimitry Andric // 120b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H 150b57cec5SDimitry Andric #define LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H 160b57cec5SDimitry Andric 170b57cec5SDimitry Andric #include "llvm/CodeGen/MachineScheduler.h" 180b57cec5SDimitry Andric #include <vector> 190b57cec5SDimitry Andric 200b57cec5SDimitry Andric using namespace llvm; 210b57cec5SDimitry Andric 220b57cec5SDimitry Andric namespace llvm { 230b57cec5SDimitry Andric 240b57cec5SDimitry Andric class R600InstrInfo; 250b57cec5SDimitry Andric struct R600RegisterInfo; 260b57cec5SDimitry Andric 270b57cec5SDimitry Andric class R600SchedStrategy final : public MachineSchedStrategy { 280b57cec5SDimitry Andric const ScheduleDAGMILive *DAG = nullptr; 290b57cec5SDimitry Andric const R600InstrInfo *TII = nullptr; 300b57cec5SDimitry Andric const R600RegisterInfo *TRI = nullptr; 310b57cec5SDimitry Andric MachineRegisterInfo *MRI = nullptr; 320b57cec5SDimitry Andric 330b57cec5SDimitry Andric enum InstKind { 340b57cec5SDimitry Andric IDAlu, 350b57cec5SDimitry Andric IDFetch, 360b57cec5SDimitry Andric IDOther, 370b57cec5SDimitry Andric IDLast 380b57cec5SDimitry Andric }; 390b57cec5SDimitry Andric 400b57cec5SDimitry Andric enum AluKind { 410b57cec5SDimitry Andric AluAny, 420b57cec5SDimitry Andric AluT_X, 430b57cec5SDimitry Andric AluT_Y, 440b57cec5SDimitry Andric AluT_Z, 450b57cec5SDimitry Andric AluT_W, 460b57cec5SDimitry Andric AluT_XYZW, 470b57cec5SDimitry Andric AluPredX, 480b57cec5SDimitry Andric AluTrans, 490b57cec5SDimitry Andric AluDiscarded, // LLVM Instructions that are going to be eliminated 500b57cec5SDimitry Andric AluLast 510b57cec5SDimitry Andric }; 520b57cec5SDimitry Andric 530b57cec5SDimitry Andric std::vector<SUnit *> Available[IDLast], Pending[IDLast]; 540b57cec5SDimitry Andric std::vector<SUnit *> AvailableAlus[AluLast]; 550b57cec5SDimitry Andric std::vector<SUnit *> PhysicalRegCopy; 560b57cec5SDimitry Andric 570b57cec5SDimitry Andric InstKind CurInstKind; 580b57cec5SDimitry Andric int CurEmitted; 590b57cec5SDimitry Andric InstKind NextInstKind; 600b57cec5SDimitry Andric 610b57cec5SDimitry Andric unsigned AluInstCount; 620b57cec5SDimitry Andric unsigned FetchInstCount; 630b57cec5SDimitry Andric 640b57cec5SDimitry Andric int InstKindLimit[IDLast]; 650b57cec5SDimitry Andric 66*349cc55cSDimitry Andric int OccupiedSlotsMask; 670b57cec5SDimitry Andric 680b57cec5SDimitry Andric public: 690b57cec5SDimitry Andric R600SchedStrategy() = default; 700b57cec5SDimitry Andric ~R600SchedStrategy() override = default; 710b57cec5SDimitry Andric 720b57cec5SDimitry Andric void initialize(ScheduleDAGMI *dag) override; 730b57cec5SDimitry Andric SUnit *pickNode(bool &IsTopNode) override; 740b57cec5SDimitry Andric void schedNode(SUnit *SU, bool IsTopNode) override; 750b57cec5SDimitry Andric void releaseTopNode(SUnit *SU) override; 760b57cec5SDimitry Andric void releaseBottomNode(SUnit *SU) override; 770b57cec5SDimitry Andric 780b57cec5SDimitry Andric private: 790b57cec5SDimitry Andric std::vector<MachineInstr *> InstructionsGroupCandidate; 800b57cec5SDimitry Andric bool VLIW5; 810b57cec5SDimitry Andric 820b57cec5SDimitry Andric int getInstKind(SUnit *SU); 83e8d8bef9SDimitry Andric bool regBelongsToClass(Register Reg, const TargetRegisterClass *RC) const; 840b57cec5SDimitry Andric AluKind getAluKind(SUnit *SU) const; 850b57cec5SDimitry Andric void LoadAlu(); 860b57cec5SDimitry Andric unsigned AvailablesAluCount() const; 870b57cec5SDimitry Andric SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu); 880b57cec5SDimitry Andric void PrepareNextSlot(); 890b57cec5SDimitry Andric SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU); 900b57cec5SDimitry Andric 910b57cec5SDimitry Andric void AssignSlot(MachineInstr *MI, unsigned Slot); 920b57cec5SDimitry Andric SUnit* pickAlu(); 930b57cec5SDimitry Andric SUnit* pickOther(int QID); 940b57cec5SDimitry Andric void MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst); 950b57cec5SDimitry Andric }; 960b57cec5SDimitry Andric 970b57cec5SDimitry Andric } // end namespace llvm 980b57cec5SDimitry Andric 990b57cec5SDimitry Andric #endif // LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H 100