1//===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// TableGen definitions for instructions which are available on R600 family 10// GPUs. 11// 12//===----------------------------------------------------------------------===// 13 14include "R600InstrFormats.td" 15 16// FIXME: Should not be arbitrarily split from other R600 inst classes. 17class R600WrapperInst <dag outs, dag ins, string asm = "", list<dag> pattern = []> : 18 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl { 19 let SubtargetPredicate = isR600toCayman; 20 let Namespace = "R600"; 21} 22 23 24class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern = []> : 25 InstR600 <outs, ins, asm, pattern, NullALU> { 26 27} 28 29def MEMxi : Operand<iPTR> { 30 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index); 31 let PrintMethod = "printMemOperand"; 32} 33 34def MEMrr : Operand<iPTR> { 35 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index); 36} 37 38// Operands for non-registers 39 40class InstFlag<string PM = "printOperand", int Default = 0> 41 : OperandWithDefaultOps <i32, (ops (i32 Default))> { 42 let PrintMethod = PM; 43} 44 45// src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers 46def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))>; 47def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> { 48 let PrintMethod = "printBankSwizzle"; 49} 50 51def LITERAL : InstFlag<"printLiteral">; 52 53def WRITE : InstFlag <"printWrite", 1>; 54def OMOD : InstFlag <"printOMOD">; 55def REL : InstFlag <"printRel">; 56def CLAMP : InstFlag <"printClamp">; 57def NEG : InstFlag <"printNeg">; 58def ABS : InstFlag <"printAbs">; 59def UEM : InstFlag <"printUpdateExecMask">; 60def UP : InstFlag <"printUpdatePred">; 61 62// XXX: The r600g finalizer in Mesa expects last to be one in most cases. 63// Once we start using the packetizer in this backend we should have this 64// default to 0. 65def LAST : InstFlag<"printLast", 1>; 66def RSel : Operand<i32> { 67 let PrintMethod = "printRSel"; 68} 69def CT: Operand<i32> { 70 let PrintMethod = "printCT"; 71} 72 73def FRAMEri : Operand<iPTR> { 74 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index); 75} 76 77def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>; 78def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>; 79def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>; 80def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>; 81def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>; 82def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>; 83 84 85def R600_Pred : PredicateOperand<i32, (ops R600_Predicate), 86 (ops PRED_SEL_OFF)>; 87 88let isTerminator = 1, isReturn = 1, hasCtrlDep = 1, 89 usesCustomInserter = 1, Namespace = "R600" in { 90 def RETURN : ILFormat<(outs), (ins variable_ops), 91 "RETURN", [(AMDGPUendpgm)] 92 >; 93} 94 95let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 96 97// Class for instructions with only one source register. 98// If you add new ins to this instruction, make sure they are listed before 99// $literal, because the backend currently assumes that the last operand is 100// a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in 101// R600Defines.h, R600InstrInfo::buildDefaultInstruction(), 102// and R600InstrInfo::getOperandIdx(). 103class R600_1OP <bits<11> inst, string opName, list<dag> pattern, 104 InstrItinClass itin = AnyALU> : 105 InstR600 <(outs R600_Reg32:$dst), 106 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp, 107 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel, 108 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 109 BANK_SWIZZLE:$bank_swizzle), 110 !strconcat(" ", opName, 111 "$clamp $last $dst$write$dst_rel$omod, " 112 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, " 113 "$pred_sel $bank_swizzle"), 114 pattern, 115 itin>, 116 R600ALU_Word0, 117 R600ALU_Word1_OP2 <inst> { 118 119 let src1 = 0; 120 let src1_rel = 0; 121 let src1_neg = 0; 122 let src1_abs = 0; 123 let update_exec_mask = 0; 124 let update_pred = 0; 125 let HasNativeOperands = 1; 126 let Op1 = 1; 127 let ALUInst = 1; 128 let DisableEncoding = "$literal"; 129 let UseNamedOperandTable = 1; 130 131 let Inst{31-0} = Word0; 132 let Inst{63-32} = Word1; 133} 134 135class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node, 136 InstrItinClass itin = AnyALU> : 137 R600_1OP <inst, opName, 138 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))], itin 139>; 140 141// If you add or change the operands for R600_2OP instructions, you must 142// also update the R600Op2OperandIndex::ROI enum in R600Defines.h, 143// R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx(). 144class R600_2OP <bits<11> inst, string opName, list<dag> pattern, 145 InstrItinClass itin = AnyALU> : 146 InstR600 <(outs R600_Reg32:$dst), 147 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write, 148 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp, 149 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel, 150 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel, 151 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 152 BANK_SWIZZLE:$bank_swizzle), 153 !strconcat(" ", opName, 154 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, " 155 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, " 156 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, " 157 "$pred_sel $bank_swizzle"), 158 pattern, 159 itin>, 160 R600ALU_Word0, 161 R600ALU_Word1_OP2 <inst> { 162 163 let HasNativeOperands = 1; 164 let Op2 = 1; 165 let ALUInst = 1; 166 let DisableEncoding = "$literal"; 167 let UseNamedOperandTable = 1; 168 169 let Inst{31-0} = Word0; 170 let Inst{63-32} = Word1; 171} 172 173class R600_2OP_Helper <bits<11> inst, string opName, 174 SDPatternOperator node = null_frag, 175 InstrItinClass itin = AnyALU> : 176 R600_2OP <inst, opName, 177 [(set R600_Reg32:$dst, (node R600_Reg32:$src0, 178 R600_Reg32:$src1))], itin 179>; 180 181// If you add our change the operands for R600_3OP instructions, you must 182// also update the R600Op3OperandIndex::ROI enum in R600Defines.h, 183// R600InstrInfo::buildDefaultInstruction(), and 184// R600InstrInfo::getOperandIdx(). 185class R600_3OP <bits<5> inst, string opName, list<dag> pattern, 186 InstrItinClass itin = AnyALU> : 187 InstR600 <(outs R600_Reg32:$dst), 188 (ins REL:$dst_rel, CLAMP:$clamp, 189 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel, 190 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel, 191 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel, 192 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 193 BANK_SWIZZLE:$bank_swizzle), 194 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, " 195 "$src0_neg$src0$src0_rel, " 196 "$src1_neg$src1$src1_rel, " 197 "$src2_neg$src2$src2_rel, " 198 "$pred_sel" 199 "$bank_swizzle"), 200 pattern, 201 itin>, 202 R600ALU_Word0, 203 R600ALU_Word1_OP3<inst>{ 204 205 let HasNativeOperands = 1; 206 let DisableEncoding = "$literal"; 207 let Op3 = 1; 208 let UseNamedOperandTable = 1; 209 let ALUInst = 1; 210 211 let Inst{31-0} = Word0; 212 let Inst{63-32} = Word1; 213} 214 215class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern, 216 InstrItinClass itin = VecALU> : 217 InstR600 <(outs R600_Reg32:$dst), 218 ins, 219 asm, 220 pattern, 221 itin>; 222 223 224 225} // End mayLoad = 1, mayStore = 0, hasSideEffects = 0 226 227class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask, 228 dag outs, dag ins, string asm, list<dag> pattern> : 229 InstR600ISA <outs, ins, asm, pattern>, 230 CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF { 231 232 let rat_id = ratid; 233 let rat_inst = ratinst; 234 let rim = 0; 235 // XXX: Have a separate instruction for non-indexed writes. 236 let type = 1; 237 let rw_rel = 0; 238 let elem_size = 0; 239 240 let array_size = 0; 241 let comp_mask = mask; 242 let burst_count = 0; 243 let vpm = 0; 244 let cf_inst = cfinst; 245 let mark = 0; 246 let barrier = 1; 247 248 let Inst{31-0} = Word0; 249 let Inst{63-32} = Word1; 250 let IsExport = 1; 251 252} 253 254class VTX_READ <string name, dag outs, list<dag> pattern> 255 : InstR600ISA <outs, (ins MEMxi:$src_gpr, i8imm:$buffer_id), !strconcat(" ", name, ", #$buffer_id"), pattern>, 256 VTX_WORD1_GPR { 257 258 // Static fields 259 let DST_REL = 0; 260 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL, 261 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored, 262 // however, based on my testing if USE_CONST_FIELDS is set, then all 263 // these fields need to be set to 0. 264 let USE_CONST_FIELDS = 0; 265 let NUM_FORMAT_ALL = 1; 266 let FORMAT_COMP_ALL = 0; 267 let SRF_MODE_ALL = 0; 268 269 let Inst{63-32} = Word1; 270 // LLVM can only encode 64-bit instructions, so these fields are manually 271 // encoded in R600CodeEmitter 272 // 273 // bits<16> OFFSET; 274 // bits<2> ENDIAN_SWAP = 0; 275 // bits<1> CONST_BUF_NO_STRIDE = 0; 276 // bits<1> MEGA_FETCH = 0; 277 // bits<1> ALT_CONST = 0; 278 // bits<2> BUFFER_INDEX_MODE = 0; 279 280 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 281 // is done in R600CodeEmitter 282 // 283 // Inst{79-64} = OFFSET; 284 // Inst{81-80} = ENDIAN_SWAP; 285 // Inst{82} = CONST_BUF_NO_STRIDE; 286 // Inst{83} = MEGA_FETCH; 287 // Inst{84} = ALT_CONST; 288 // Inst{86-85} = BUFFER_INDEX_MODE; 289 // Inst{95-86} = 0; Reserved 290 291 // VTX_WORD3 (Padding) 292 // 293 // Inst{127-96} = 0; 294 295 let VTXInst = 1; 296} 297 298// FIXME: Deprecated. 299class LocalLoad <SDPatternOperator op> : LoadFrag <op>, LocalAddress; 300 301class AZExtLoadBase <SDPatternOperator ld_node>: PatFrag<(ops node:$ptr), 302 (ld_node node:$ptr), [{ 303 LoadSDNode *L = cast<LoadSDNode>(N); 304 return L->getExtensionType() == ISD::ZEXTLOAD || 305 L->getExtensionType() == ISD::EXTLOAD; 306}]>; 307 308def az_extload : AZExtLoadBase <unindexedload>; 309 310def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{ 311 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 312}]>; 313 314def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{ 315 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 316}]>; 317 318def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{ 319 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 320}]>; 321 322// FIXME: These are deprecated 323def az_extloadi8_local : LocalLoad <az_extloadi8>; 324def az_extloadi16_local : LocalLoad <az_extloadi16>; 325 326class LoadParamFrag <PatFrag load_type> : PatFrag < 327 (ops node:$ptr), (load_type node:$ptr), 328 [{ return isConstantLoad(cast<LoadSDNode>(N), 0) || 329 (cast<LoadSDNode>(N)->getAddressSpace() == AMDGPUAS::PARAM_I_ADDRESS); }] 330>; 331 332def vtx_id3_az_extloadi8 : LoadParamFrag<az_extloadi8>; 333def vtx_id3_az_extloadi16 : LoadParamFrag<az_extloadi16>; 334def vtx_id3_load : LoadParamFrag<load>; 335 336class LoadVtxId1 <PatFrag load> : PatFrag < 337 (ops node:$ptr), (load node:$ptr), [{ 338 const MemSDNode *LD = cast<MemSDNode>(N); 339 return LD->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS || 340 (LD->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS && 341 !isa<GlobalValue>(GetUnderlyingObject( 342 LD->getMemOperand()->getValue(), CurDAG->getDataLayout()))); 343}]>; 344 345def vtx_id1_az_extloadi8 : LoadVtxId1 <az_extloadi8>; 346def vtx_id1_az_extloadi16 : LoadVtxId1 <az_extloadi16>; 347def vtx_id1_load : LoadVtxId1 <load>; 348 349class LoadVtxId2 <PatFrag load> : PatFrag < 350 (ops node:$ptr), (load node:$ptr), [{ 351 const MemSDNode *LD = cast<MemSDNode>(N); 352 return LD->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS && 353 isa<GlobalValue>(GetUnderlyingObject( 354 LD->getMemOperand()->getValue(), CurDAG->getDataLayout())); 355}]>; 356 357def vtx_id2_az_extloadi8 : LoadVtxId2 <az_extloadi8>; 358def vtx_id2_az_extloadi16 : LoadVtxId2 <az_extloadi16>; 359def vtx_id2_load : LoadVtxId2 <load>; 360 361//===----------------------------------------------------------------------===// 362// R600 SDNodes 363//===----------------------------------------------------------------------===// 364 365let Namespace = "R600" in { 366 367def INTERP_PAIR_XY : AMDGPUShaderInst < 368 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1), 369 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2), 370 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1", 371 []>; 372 373def INTERP_PAIR_ZW : AMDGPUShaderInst < 374 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1), 375 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2), 376 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1", 377 []>; 378 379} 380 381def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS", 382 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>, 383 [SDNPVariadic] 384>; 385 386def DOT4 : SDNode<"AMDGPUISD::DOT4", 387 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>, 388 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>, 389 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>, 390 [] 391>; 392 393def COS_HW : SDNode<"AMDGPUISD::COS_HW", 394 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]> 395>; 396 397def SIN_HW : SDNode<"AMDGPUISD::SIN_HW", 398 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]> 399>; 400 401def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>; 402 403def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>; 404 405multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> { 406def : R600Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR, 407 (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw), 408 (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz), 409 (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z), 410 (i32 imm:$DST_SEL_W), 411 (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID), 412 (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z), 413 (i32 imm:$COORD_TYPE_W)), 414 (inst R600_Reg128:$SRC_GPR, 415 imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw, 416 imm:$offsetx, imm:$offsety, imm:$offsetz, 417 imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z, 418 imm:$DST_SEL_W, 419 imm:$RESOURCE_ID, imm:$SAMPLER_ID, 420 imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z, 421 imm:$COORD_TYPE_W)>; 422} 423 424//===----------------------------------------------------------------------===// 425// Interpolation Instructions 426//===----------------------------------------------------------------------===// 427 428let Namespace = "R600" in { 429 430def INTERP_VEC_LOAD : AMDGPUShaderInst < 431 (outs R600_Reg128:$dst), 432 (ins i32imm:$src0), 433 "INTERP_LOAD $src0 : $dst">; 434 435} 436 437def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> { 438 let bank_swizzle = 5; 439} 440 441def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> { 442 let bank_swizzle = 5; 443} 444 445def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>; 446 447//===----------------------------------------------------------------------===// 448// Export Instructions 449//===----------------------------------------------------------------------===// 450 451class ExportWord0 { 452 field bits<32> Word0; 453 454 bits<13> arraybase; 455 bits<2> type; 456 bits<7> gpr; 457 bits<2> elem_size; 458 459 let Word0{12-0} = arraybase; 460 let Word0{14-13} = type; 461 let Word0{21-15} = gpr; 462 let Word0{22} = 0; // RW_REL 463 let Word0{29-23} = 0; // INDEX_GPR 464 let Word0{31-30} = elem_size; 465} 466 467class ExportSwzWord1 { 468 field bits<32> Word1; 469 470 bits<3> sw_x; 471 bits<3> sw_y; 472 bits<3> sw_z; 473 bits<3> sw_w; 474 bits<1> eop; 475 bits<8> inst; 476 477 let Word1{2-0} = sw_x; 478 let Word1{5-3} = sw_y; 479 let Word1{8-6} = sw_z; 480 let Word1{11-9} = sw_w; 481} 482 483class ExportBufWord1 { 484 field bits<32> Word1; 485 486 bits<12> arraySize; 487 bits<4> compMask; 488 bits<1> eop; 489 bits<8> inst; 490 491 let Word1{11-0} = arraySize; 492 let Word1{15-12} = compMask; 493} 494 495multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> { 496 def : R600Pat<(R600_EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type), 497 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)), 498 (ExportInst R600_Reg128:$src, imm:$type, imm:$base, 499 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0) 500 >; 501 502} 503 504multiclass SteamOutputExportPattern<Instruction ExportInst, 505 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> { 506// Stream0 507 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), 508 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)), 509 (ExportInst R600_Reg128:$src, 0, imm:$arraybase, 510 4095, imm:$mask, buf0inst, 0)>; 511// Stream1 512 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), 513 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)), 514 (ExportInst $src, 0, imm:$arraybase, 515 4095, imm:$mask, buf1inst, 0)>; 516// Stream2 517 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), 518 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)), 519 (ExportInst $src, 0, imm:$arraybase, 520 4095, imm:$mask, buf2inst, 0)>; 521// Stream3 522 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), 523 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)), 524 (ExportInst $src, 0, imm:$arraybase, 525 4095, imm:$mask, buf3inst, 0)>; 526} 527 528// Export Instructions should not be duplicated by TailDuplication pass 529// (which assumes that duplicable instruction are affected by exec mask) 530let usesCustomInserter = 1, isNotDuplicable = 1 in { 531 532class ExportSwzInst : InstR600ISA<( 533 outs), 534 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase, 535 RSel:$sw_x, RSel:$sw_y, RSel:$sw_z, RSel:$sw_w, i32imm:$inst, 536 i32imm:$eop), 537 !strconcat("EXPORT", " $gpr.$sw_x$sw_y$sw_z$sw_w"), 538 []>, ExportWord0, ExportSwzWord1 { 539 let elem_size = 3; 540 let Inst{31-0} = Word0; 541 let Inst{63-32} = Word1; 542 let IsExport = 1; 543} 544 545} // End usesCustomInserter = 1 546 547class ExportBufInst : InstR600ISA<( 548 outs), 549 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase, 550 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop), 551 !strconcat("EXPORT", " $gpr"), 552 []>, ExportWord0, ExportBufWord1 { 553 let elem_size = 0; 554 let Inst{31-0} = Word0; 555 let Inst{63-32} = Word1; 556 let IsExport = 1; 557} 558 559//===----------------------------------------------------------------------===// 560// Control Flow Instructions 561//===----------------------------------------------------------------------===// 562 563 564def KCACHE : InstFlag<"printKCache">; 565 566class ALU_CLAUSE<bits<4> inst, string OpName> : R600WrapperInst <(outs), 567(ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1, 568KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1, 569i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1, 570i32imm:$COUNT, i32imm:$Enabled), 571!strconcat(OpName, " $COUNT, @$ADDR, " 572"KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"), 573[] >, CF_ALU_WORD0, CF_ALU_WORD1 { 574 field bits<64> Inst; 575 576 let CF_INST = inst; 577 let ALT_CONST = 0; 578 let WHOLE_QUAD_MODE = 0; 579 let BARRIER = 1; 580 let isCodeGenOnly = 1; 581 let UseNamedOperandTable = 1; 582 583 let Inst{31-0} = Word0; 584 let Inst{63-32} = Word1; 585} 586 587class CF_WORD0_R600 { 588 field bits<32> Word0; 589 590 bits<32> ADDR; 591 592 let Word0 = ADDR; 593} 594 595class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : R600WrapperInst <(outs), 596ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 { 597 field bits<64> Inst; 598 bits<4> CNT; 599 600 let CF_INST = inst; 601 let BARRIER = 1; 602 let CF_CONST = 0; 603 let VALID_PIXEL_MODE = 0; 604 let COND = 0; 605 let COUNT = CNT{2-0}; 606 let CALL_COUNT = 0; 607 let COUNT_3 = CNT{3}; 608 let END_OF_PROGRAM = 0; 609 let WHOLE_QUAD_MODE = 0; 610 611 let Inst{31-0} = Word0; 612 let Inst{63-32} = Word1; 613} 614 615class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : R600WrapperInst <(outs), 616ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG { 617 field bits<64> Inst; 618 619 let CF_INST = inst; 620 let BARRIER = 1; 621 let JUMPTABLE_SEL = 0; 622 let CF_CONST = 0; 623 let VALID_PIXEL_MODE = 0; 624 let COND = 0; 625 let END_OF_PROGRAM = 0; 626 627 let Inst{31-0} = Word0; 628 let Inst{63-32} = Word1; 629} 630 631def CF_ALU : ALU_CLAUSE<8, "ALU">; 632def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">; 633def CF_ALU_POP_AFTER : ALU_CLAUSE<10, "ALU_POP_AFTER">; 634def CF_ALU_CONTINUE : ALU_CLAUSE<13, "ALU_CONTINUE">; 635def CF_ALU_BREAK : ALU_CLAUSE<14, "ALU_BREAK">; 636def CF_ALU_ELSE_AFTER : ALU_CLAUSE<15, "ALU_ELSE_AFTER">; 637 638def FETCH_CLAUSE : R600WrapperInst <(outs), 639(ins i32imm:$addr), "Fetch clause starting at $addr:", [] > { 640 field bits<8> Inst; 641 bits<8> num; 642 let Inst = num; 643 let isCodeGenOnly = 1; 644} 645 646def ALU_CLAUSE : R600WrapperInst <(outs), 647(ins i32imm:$addr), "ALU clause starting at $addr:", [] > { 648 field bits<8> Inst; 649 bits<8> num; 650 let Inst = num; 651 let isCodeGenOnly = 1; 652} 653 654def LITERALS : R600WrapperInst <(outs), 655(ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > { 656 let isCodeGenOnly = 1; 657 658 field bits<64> Inst; 659 bits<32> literal1; 660 bits<32> literal2; 661 662 let Inst{31-0} = literal1; 663 let Inst{63-32} = literal2; 664} 665 666def PAD : R600WrapperInst <(outs), (ins), "PAD", [] > { 667 field bits<64> Inst; 668} 669 670//===----------------------------------------------------------------------===// 671// Common Instructions R600, R700, Evergreen, Cayman 672//===----------------------------------------------------------------------===// 673 674let isCodeGenOnly = 1, isPseudo = 1 in { 675 676let Namespace = "R600", usesCustomInserter = 1 in { 677 678class FABS <RegisterClass rc> : AMDGPUShaderInst < 679 (outs rc:$dst), 680 (ins rc:$src0), 681 "FABS $dst, $src0", 682 [(set f32:$dst, (fabs f32:$src0))] 683>; 684 685class FNEG <RegisterClass rc> : AMDGPUShaderInst < 686 (outs rc:$dst), 687 (ins rc:$src0), 688 "FNEG $dst, $src0", 689 [(set f32:$dst, (fneg f32:$src0))] 690>; 691 692} // usesCustomInserter = 1 693 694multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass, 695 ComplexPattern addrPat> { 696let UseNamedOperandTable = 1 in { 697 698 def RegisterLoad : AMDGPUShaderInst < 699 (outs dstClass:$dst), 700 (ins addrClass:$addr, i32imm:$chan), 701 "RegisterLoad $dst, $addr", 702 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))] 703 > { 704 let isRegisterLoad = 1; 705 } 706 707 def RegisterStore : AMDGPUShaderInst < 708 (outs), 709 (ins dstClass:$val, addrClass:$addr, i32imm:$chan), 710 "RegisterStore $val, $addr", 711 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))] 712 > { 713 let isRegisterStore = 1; 714 } 715} 716} 717 718} // End isCodeGenOnly = 1, isPseudo = 1 719 720 721def ADD : R600_2OP_Helper <0x0, "ADD", fadd>; 722// Non-IEEE MUL: 0 * anything = 0 723def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE">; 724def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>; 725// TODO: Do these actually match the regular fmin/fmax behavior? 726def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax_legacy>; 727def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin_legacy>; 728// According to https://msdn.microsoft.com/en-us/library/windows/desktop/cc308050%28v=vs.85%29.aspx 729// DX10 min/max returns the other operand if one is NaN, 730// this matches http://llvm.org/docs/LangRef.html#llvm-minnum-intrinsic 731def MAX_DX10 : R600_2OP_Helper <0x5, "MAX_DX10", fmaxnum>; 732def MIN_DX10 : R600_2OP_Helper <0x6, "MIN_DX10", fminnum>; 733 734// For the SET* instructions there is a naming conflict in TargetSelectionDAG.td, 735// so some of the instruction names don't match the asm string. 736// XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics. 737def SETE : R600_2OP < 738 0x08, "SETE", 739 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OEQ))] 740>; 741 742def SGT : R600_2OP < 743 0x09, "SETGT", 744 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGT))] 745>; 746 747def SGE : R600_2OP < 748 0xA, "SETGE", 749 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGE))] 750>; 751 752def SNE : R600_2OP < 753 0xB, "SETNE", 754 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_UNE_NE))] 755>; 756 757def SETE_DX10 : R600_2OP < 758 0xC, "SETE_DX10", 759 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OEQ))] 760>; 761 762def SETGT_DX10 : R600_2OP < 763 0xD, "SETGT_DX10", 764 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGT))] 765>; 766 767def SETGE_DX10 : R600_2OP < 768 0xE, "SETGE_DX10", 769 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGE))] 770>; 771 772// FIXME: This should probably be COND_ONE 773def SETNE_DX10 : R600_2OP < 774 0xF, "SETNE_DX10", 775 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_UNE_NE))] 776>; 777 778// FIXME: Need combine for AMDGPUfract 779def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>; 780def TRUNC : R600_1OP_Helper <0x11, "TRUNC", ftrunc>; 781def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>; 782def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>; 783def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>; 784 785def MOV : R600_1OP <0x19, "MOV", []>; 786 787 788// This is a hack to get rid of DUMMY_CHAIN nodes. 789// Most DUMMY_CHAINs should be eliminated during legalization, but undef 790// values can sneak in some to selection. 791let isPseudo = 1, isCodeGenOnly = 1 in { 792def DUMMY_CHAIN : R600WrapperInst < 793 (outs), 794 (ins), 795 "DUMMY_CHAIN", 796 [(R600dummy_chain)] 797>; 798} // end let isPseudo = 1, isCodeGenOnly = 1 799 800 801let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in { 802 803class MOV_IMM <ValueType vt, Operand immType> : R600WrapperInst < 804 (outs R600_Reg32:$dst), 805 (ins immType:$imm), 806 "", 807 [] 808> { 809 let Namespace = "R600"; 810} 811 812} // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 813 814def MOV_IMM_I32 : MOV_IMM<i32, i32imm>; 815def : R600Pat < 816 (imm:$val), 817 (MOV_IMM_I32 imm:$val) 818>; 819 820def MOV_IMM_GLOBAL_ADDR : MOV_IMM<iPTR, i32imm>; 821def : R600Pat < 822 (AMDGPUconstdata_ptr tglobaladdr:$addr), 823 (MOV_IMM_GLOBAL_ADDR tglobaladdr:$addr) 824>; 825 826 827def MOV_IMM_F32 : MOV_IMM<f32, f32imm>; 828def : R600Pat < 829 (fpimm:$val), 830 (MOV_IMM_F32 fpimm:$val) 831>; 832 833def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>; 834def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>; 835def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>; 836def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>; 837 838let hasSideEffects = 1 in { 839 840def KILLGT : R600_2OP <0x2D, "KILLGT", []>; 841 842} // end hasSideEffects 843 844def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>; 845def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>; 846def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>; 847def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>; 848def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>; 849def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>; 850def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", smax>; 851def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", smin>; 852def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", umax>; 853def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", umin>; 854 855def SETE_INT : R600_2OP < 856 0x3A, "SETE_INT", 857 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))] 858>; 859 860def SETGT_INT : R600_2OP < 861 0x3B, "SETGT_INT", 862 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))] 863>; 864 865def SETGE_INT : R600_2OP < 866 0x3C, "SETGE_INT", 867 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))] 868>; 869 870def SETNE_INT : R600_2OP < 871 0x3D, "SETNE_INT", 872 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))] 873>; 874 875def SETGT_UINT : R600_2OP < 876 0x3E, "SETGT_UINT", 877 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))] 878>; 879 880def SETGE_UINT : R600_2OP < 881 0x3F, "SETGE_UINT", 882 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))] 883>; 884 885def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>; 886def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>; 887def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>; 888def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>; 889 890def CNDE_INT : R600_3OP < 891 0x1C, "CNDE_INT", 892 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))] 893>; 894 895def CNDGE_INT : R600_3OP < 896 0x1E, "CNDGE_INT", 897 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGE))] 898>; 899 900def CNDGT_INT : R600_3OP < 901 0x1D, "CNDGT_INT", 902 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGT))] 903>; 904 905//===----------------------------------------------------------------------===// 906// Texture instructions 907//===----------------------------------------------------------------------===// 908 909let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 910 911class R600_TEX <bits<11> inst, string opName> : 912 InstR600 <(outs R600_Reg128:$DST_GPR), 913 (ins R600_Reg128:$SRC_GPR, 914 RSel:$srcx, RSel:$srcy, RSel:$srcz, RSel:$srcw, 915 i32imm:$offsetx, i32imm:$offsety, i32imm:$offsetz, 916 RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W, 917 i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID, 918 CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z, 919 CT:$COORD_TYPE_W), 920 !strconcat(" ", opName, 921 " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, " 922 "$SRC_GPR.$srcx$srcy$srcz$srcw " 923 "RID:$RESOURCE_ID SID:$SAMPLER_ID " 924 "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"), 925 [], 926 NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 { 927 let Inst{31-0} = Word0; 928 let Inst{63-32} = Word1; 929 930 let TEX_INST = inst{4-0}; 931 let SRC_REL = 0; 932 let DST_REL = 0; 933 let LOD_BIAS = 0; 934 935 let INST_MOD = 0; 936 let FETCH_WHOLE_QUAD = 0; 937 let ALT_CONST = 0; 938 let SAMPLER_INDEX_MODE = 0; 939 let RESOURCE_INDEX_MODE = 0; 940 941 let TEXInst = 1; 942} 943 944} // End mayLoad = 0, mayStore = 0, hasSideEffects = 0 945 946 947 948def TEX_SAMPLE : R600_TEX <0x10, "TEX_SAMPLE">; 949def TEX_SAMPLE_C : R600_TEX <0x18, "TEX_SAMPLE_C">; 950def TEX_SAMPLE_L : R600_TEX <0x11, "TEX_SAMPLE_L">; 951def TEX_SAMPLE_C_L : R600_TEX <0x19, "TEX_SAMPLE_C_L">; 952def TEX_SAMPLE_LB : R600_TEX <0x12, "TEX_SAMPLE_LB">; 953def TEX_SAMPLE_C_LB : R600_TEX <0x1A, "TEX_SAMPLE_C_LB">; 954def TEX_LD : R600_TEX <0x03, "TEX_LD">; 955def TEX_LDPTR : R600_TEX <0x03, "TEX_LDPTR"> { 956 let INST_MOD = 1; 957} 958def TEX_GET_TEXTURE_RESINFO : R600_TEX <0x04, "TEX_GET_TEXTURE_RESINFO">; 959def TEX_GET_GRADIENTS_H : R600_TEX <0x07, "TEX_GET_GRADIENTS_H">; 960def TEX_GET_GRADIENTS_V : R600_TEX <0x08, "TEX_GET_GRADIENTS_V">; 961def TEX_SET_GRADIENTS_H : R600_TEX <0x0B, "TEX_SET_GRADIENTS_H">; 962def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">; 963def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">; 964def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">; 965 966defm : TexPattern<0, TEX_SAMPLE>; 967defm : TexPattern<1, TEX_SAMPLE_C>; 968defm : TexPattern<2, TEX_SAMPLE_L>; 969defm : TexPattern<3, TEX_SAMPLE_C_L>; 970defm : TexPattern<4, TEX_SAMPLE_LB>; 971defm : TexPattern<5, TEX_SAMPLE_C_LB>; 972defm : TexPattern<6, TEX_LD, v4i32>; 973defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>; 974defm : TexPattern<8, TEX_GET_GRADIENTS_H>; 975defm : TexPattern<9, TEX_GET_GRADIENTS_V>; 976defm : TexPattern<10, TEX_LDPTR, v4i32>; 977 978//===----------------------------------------------------------------------===// 979// Helper classes for common instructions 980//===----------------------------------------------------------------------===// 981 982class MUL_LIT_Common <bits<5> inst> : R600_3OP < 983 inst, "MUL_LIT", 984 [] 985>; 986 987class MULADD_Common <bits<5> inst> : R600_3OP < 988 inst, "MULADD", 989 [] 990>; 991 992class MULADD_IEEE_Common <bits<5> inst> : R600_3OP < 993 inst, "MULADD_IEEE", 994 [(set f32:$dst, (fmad f32:$src0, f32:$src1, f32:$src2))] 995>; 996 997class FMA_Common <bits<5> inst> : R600_3OP < 998 inst, "FMA", 999 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))], VecALU 1000> 1001{ 1002 let OtherPredicates = [FMA]; 1003} 1004 1005class CNDE_Common <bits<5> inst> : R600_3OP < 1006 inst, "CNDE", 1007 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OEQ))] 1008>; 1009 1010class CNDGT_Common <bits<5> inst> : R600_3OP < 1011 inst, "CNDGT", 1012 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGT))] 1013> { 1014 let Itinerary = VecALU; 1015} 1016 1017class CNDGE_Common <bits<5> inst> : R600_3OP < 1018 inst, "CNDGE", 1019 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGE))] 1020> { 1021 let Itinerary = VecALU; 1022} 1023 1024 1025let isCodeGenOnly = 1, isPseudo = 1, Namespace = "R600" in { 1026class R600_VEC2OP<list<dag> pattern> : InstR600 <(outs R600_Reg32:$dst), (ins 1027// Slot X 1028 UEM:$update_exec_mask_X, UP:$update_pred_X, WRITE:$write_X, 1029 OMOD:$omod_X, REL:$dst_rel_X, CLAMP:$clamp_X, 1030 R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X, 1031 R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X, 1032 R600_Pred:$pred_sel_X, 1033// Slot Y 1034 UEM:$update_exec_mask_Y, UP:$update_pred_Y, WRITE:$write_Y, 1035 OMOD:$omod_Y, REL:$dst_rel_Y, CLAMP:$clamp_Y, 1036 R600_TReg32_Y:$src0_Y, NEG:$src0_neg_Y, REL:$src0_rel_Y, ABS:$src0_abs_Y, SEL:$src0_sel_Y, 1037 R600_TReg32_Y:$src1_Y, NEG:$src1_neg_Y, REL:$src1_rel_Y, ABS:$src1_abs_Y, SEL:$src1_sel_Y, 1038 R600_Pred:$pred_sel_Y, 1039// Slot Z 1040 UEM:$update_exec_mask_Z, UP:$update_pred_Z, WRITE:$write_Z, 1041 OMOD:$omod_Z, REL:$dst_rel_Z, CLAMP:$clamp_Z, 1042 R600_TReg32_Z:$src0_Z, NEG:$src0_neg_Z, REL:$src0_rel_Z, ABS:$src0_abs_Z, SEL:$src0_sel_Z, 1043 R600_TReg32_Z:$src1_Z, NEG:$src1_neg_Z, REL:$src1_rel_Z, ABS:$src1_abs_Z, SEL:$src1_sel_Z, 1044 R600_Pred:$pred_sel_Z, 1045// Slot W 1046 UEM:$update_exec_mask_W, UP:$update_pred_W, WRITE:$write_W, 1047 OMOD:$omod_W, REL:$dst_rel_W, CLAMP:$clamp_W, 1048 R600_TReg32_W:$src0_W, NEG:$src0_neg_W, REL:$src0_rel_W, ABS:$src0_abs_W, SEL:$src0_sel_W, 1049 R600_TReg32_W:$src1_W, NEG:$src1_neg_W, REL:$src1_rel_W, ABS:$src1_abs_W, SEL:$src1_sel_W, 1050 R600_Pred:$pred_sel_W, 1051 LITERAL:$literal0, LITERAL:$literal1), 1052 "", 1053 pattern, 1054 AnyALU> { 1055 1056 let UseNamedOperandTable = 1; 1057 1058} 1059} 1060 1061def DOT_4 : R600_VEC2OP<[(set R600_Reg32:$dst, (DOT4 1062 R600_TReg32_X:$src0_X, R600_TReg32_X:$src1_X, 1063 R600_TReg32_Y:$src0_Y, R600_TReg32_Y:$src1_Y, 1064 R600_TReg32_Z:$src0_Z, R600_TReg32_Z:$src1_Z, 1065 R600_TReg32_W:$src0_W, R600_TReg32_W:$src1_W))]>; 1066 1067 1068class DOT4_Common <bits<11> inst> : R600_2OP <inst, "DOT4", []>; 1069 1070 1071let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 1072multiclass CUBE_Common <bits<11> inst> { 1073 1074 def _pseudo : InstR600 < 1075 (outs R600_Reg128:$dst), 1076 (ins R600_Reg128:$src0), 1077 "CUBE $dst $src0", 1078 [(set v4f32:$dst, (int_r600_cube v4f32:$src0))], 1079 VecALU 1080 > { 1081 let isPseudo = 1; 1082 let UseNamedOperandTable = 1; 1083 } 1084 1085 def _real : R600_2OP <inst, "CUBE", []>; 1086} 1087} // End mayLoad = 0, mayStore = 0, hasSideEffects = 0 1088 1089class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1090 inst, "EXP_IEEE", fexp2 1091> { 1092 let Itinerary = TransALU; 1093} 1094 1095class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper < 1096 inst, "FLT_TO_INT", fp_to_sint 1097> { 1098 let Itinerary = TransALU; 1099} 1100 1101class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper < 1102 inst, "INT_TO_FLT", sint_to_fp 1103> { 1104 let Itinerary = TransALU; 1105} 1106 1107class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper < 1108 inst, "FLT_TO_UINT", fp_to_uint 1109> { 1110 let Itinerary = TransALU; 1111} 1112 1113class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper < 1114 inst, "UINT_TO_FLT", uint_to_fp 1115> { 1116 let Itinerary = TransALU; 1117} 1118 1119class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP < 1120 inst, "LOG_CLAMPED", [] 1121>; 1122 1123class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1124 inst, "LOG_IEEE", flog2 1125> { 1126 let Itinerary = TransALU; 1127} 1128 1129class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>; 1130class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>; 1131class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>; 1132class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper < 1133 inst, "MULHI_INT", mulhs> { 1134 let Itinerary = TransALU; 1135} 1136 1137class MULHI_INT24_Common <bits<11> inst> : R600_2OP_Helper < 1138 inst, "MULHI_INT24", AMDGPUmulhi_i24> { 1139 let Itinerary = VecALU; 1140} 1141 1142class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper < 1143 inst, "MULHI", mulhu> { 1144 let Itinerary = TransALU; 1145} 1146 1147class MULHI_UINT24_Common <bits<11> inst> : R600_2OP_Helper < 1148 inst, "MULHI_UINT24", AMDGPUmulhi_u24> { 1149 let Itinerary = VecALU; 1150} 1151 1152class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper < 1153 inst, "MULLO_INT", mul> { 1154 let Itinerary = TransALU; 1155} 1156class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> { 1157 let Itinerary = TransALU; 1158} 1159 1160class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP < 1161 inst, "RECIP_CLAMPED", [] 1162> { 1163 let Itinerary = TransALU; 1164} 1165 1166class RECIP_IEEE_Common <bits<11> inst> : R600_1OP < 1167 inst, "RECIP_IEEE", [(set f32:$dst, (AMDGPUrcp f32:$src0))] 1168> { 1169 let Itinerary = TransALU; 1170} 1171 1172class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper < 1173 inst, "RECIP_UINT", AMDGPUurecip 1174> { 1175 let Itinerary = TransALU; 1176} 1177 1178// Clamped to maximum. 1179class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper < 1180 inst, "RECIPSQRT_CLAMPED", AMDGPUrsq_clamp 1181> { 1182 let Itinerary = TransALU; 1183} 1184 1185class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1186 inst, "RECIPSQRT_IEEE", AMDGPUrsq> { 1187 let Itinerary = TransALU; 1188} 1189 1190// TODO: There is also RECIPSQRT_FF which clamps to zero. 1191 1192class SIN_Common <bits<11> inst> : R600_1OP < 1193 inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{ 1194 let Trig = 1; 1195 let Itinerary = TransALU; 1196} 1197 1198class COS_Common <bits<11> inst> : R600_1OP < 1199 inst, "COS", [(set f32:$dst, (COS_HW f32:$src0))]> { 1200 let Trig = 1; 1201 let Itinerary = TransALU; 1202} 1203 1204def FABS_R600 : FABS<R600_Reg32>; 1205def FNEG_R600 : FNEG<R600_Reg32>; 1206 1207//===----------------------------------------------------------------------===// 1208// Helper patterns for complex intrinsics 1209//===----------------------------------------------------------------------===// 1210 1211// FIXME: Should be predicated on unsafe fp math. 1212multiclass DIV_Common <InstR600 recip_ieee> { 1213def : R600Pat< 1214 (fdiv f32:$src0, f32:$src1), 1215 (MUL_IEEE $src0, (recip_ieee $src1)) 1216>; 1217 1218def : RcpPat<recip_ieee, f32>; 1219} 1220 1221//===----------------------------------------------------------------------===// 1222// R600 / R700 Instructions 1223//===----------------------------------------------------------------------===// 1224 1225let Predicates = [isR600] in { 1226 1227 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>; 1228 def MULADD_r600 : MULADD_Common<0x10>; 1229 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>; 1230 def CNDE_r600 : CNDE_Common<0x18>; 1231 def CNDGT_r600 : CNDGT_Common<0x19>; 1232 def CNDGE_r600 : CNDGE_Common<0x1A>; 1233 def DOT4_r600 : DOT4_Common<0x50>; 1234 defm CUBE_r600 : CUBE_Common<0x52>; 1235 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>; 1236 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>; 1237 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>; 1238 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>; 1239 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>; 1240 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>; 1241 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>; 1242 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>; 1243 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>; 1244 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>; 1245 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>; 1246 def SIN_r600 : SIN_Common<0x6E>; 1247 def COS_r600 : COS_Common<0x6F>; 1248 def ASHR_r600 : ASHR_Common<0x70>; 1249 def LSHR_r600 : LSHR_Common<0x71>; 1250 def LSHL_r600 : LSHL_Common<0x72>; 1251 def MULLO_INT_r600 : MULLO_INT_Common<0x73>; 1252 def MULHI_INT_r600 : MULHI_INT_Common<0x74>; 1253 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>; 1254 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>; 1255 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>; 1256 1257 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>; 1258 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>; 1259 1260 def : R600Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>; 1261 def : RsqPat<RECIPSQRT_IEEE_r600, f32>; 1262 1263 def R600_ExportSwz : ExportSwzInst { 1264 let Word1{20-17} = 0; // BURST_COUNT 1265 let Word1{21} = eop; 1266 let Word1{22} = 0; // VALID_PIXEL_MODE 1267 let Word1{30-23} = inst; 1268 let Word1{31} = 1; // BARRIER 1269 } 1270 defm : ExportPattern<R600_ExportSwz, 39>; 1271 1272 def R600_ExportBuf : ExportBufInst { 1273 let Word1{20-17} = 0; // BURST_COUNT 1274 let Word1{21} = eop; 1275 let Word1{22} = 0; // VALID_PIXEL_MODE 1276 let Word1{30-23} = inst; 1277 let Word1{31} = 1; // BARRIER 1278 } 1279 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>; 1280 1281 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$CNT), 1282 "TEX $CNT @$ADDR"> { 1283 let POP_COUNT = 0; 1284 } 1285 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$CNT), 1286 "VTX $CNT @$ADDR"> { 1287 let POP_COUNT = 0; 1288 } 1289 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR), 1290 "LOOP_START_DX10 @$ADDR"> { 1291 let POP_COUNT = 0; 1292 let CNT = 0; 1293 } 1294 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> { 1295 let POP_COUNT = 0; 1296 let CNT = 0; 1297 } 1298 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR), 1299 "LOOP_BREAK @$ADDR"> { 1300 let POP_COUNT = 0; 1301 let CNT = 0; 1302 } 1303 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR), 1304 "CONTINUE @$ADDR"> { 1305 let POP_COUNT = 0; 1306 let CNT = 0; 1307 } 1308 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1309 "JUMP @$ADDR POP:$POP_COUNT"> { 1310 let CNT = 0; 1311 } 1312 def CF_PUSH_ELSE_R600 : CF_CLAUSE_R600<12, (ins i32imm:$ADDR), 1313 "PUSH_ELSE @$ADDR"> { 1314 let CNT = 0; 1315 let POP_COUNT = 0; // FIXME? 1316 } 1317 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1318 "ELSE @$ADDR POP:$POP_COUNT"> { 1319 let CNT = 0; 1320 } 1321 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> { 1322 let ADDR = 0; 1323 let CNT = 0; 1324 let POP_COUNT = 0; 1325 } 1326 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1327 "POP @$ADDR POP:$POP_COUNT"> { 1328 let CNT = 0; 1329 } 1330 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> { 1331 let CNT = 0; 1332 let POP_COUNT = 0; 1333 let ADDR = 0; 1334 let END_OF_PROGRAM = 1; 1335 } 1336 1337} 1338 1339 1340//===----------------------------------------------------------------------===// 1341// Regist loads and stores - for indirect addressing 1342//===----------------------------------------------------------------------===// 1343 1344let Namespace = "R600" in { 1345defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>; 1346} 1347 1348// Hardcode channel to 0 1349// NOTE: LSHR is not available here. LSHR is per family instruction 1350def : R600Pat < 1351 (i32 (load_private ADDRIndirect:$addr) ), 1352 (R600_RegisterLoad FRAMEri:$addr, (i32 0)) 1353>; 1354def : R600Pat < 1355 (store_private i32:$val, ADDRIndirect:$addr), 1356 (R600_RegisterStore i32:$val, FRAMEri:$addr, (i32 0)) 1357>; 1358 1359 1360//===----------------------------------------------------------------------===// 1361// Pseudo instructions 1362//===----------------------------------------------------------------------===// 1363 1364let isPseudo = 1 in { 1365 1366def PRED_X : InstR600 < 1367 (outs R600_Predicate_Bit:$dst), 1368 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags), 1369 "", [], NullALU> { 1370 let FlagOperandIdx = 3; 1371} 1372 1373let isTerminator = 1, isBranch = 1 in { 1374def JUMP_COND : InstR600 < 1375 (outs), 1376 (ins brtarget:$target, R600_Predicate_Bit:$p), 1377 "JUMP $target ($p)", 1378 [], AnyALU 1379 >; 1380 1381def JUMP : InstR600 < 1382 (outs), 1383 (ins brtarget:$target), 1384 "JUMP $target", 1385 [], AnyALU 1386 > 1387{ 1388 let isPredicable = 1; 1389 let isBarrier = 1; 1390} 1391 1392} // End isTerminator = 1, isBranch = 1 1393 1394let usesCustomInserter = 1 in { 1395 1396let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in { 1397 1398def MASK_WRITE : InstR600 < 1399 (outs), 1400 (ins R600_Reg32:$src), 1401 "MASK_WRITE $src", 1402 [], 1403 NullALU 1404>; 1405 1406} // End mayLoad = 0, mayStore = 0, hasSideEffects = 1 1407 1408 1409def TXD: InstR600 < 1410 (outs R600_Reg128:$dst), 1411 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, 1412 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget), 1413 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", [], 1414 NullALU > { 1415 let TEXInst = 1; 1416} 1417 1418def TXD_SHADOW: InstR600 < 1419 (outs R600_Reg128:$dst), 1420 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, 1421 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget), 1422 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", 1423 [], NullALU> { 1424 let TEXInst = 1; 1425} 1426} // End isPseudo = 1 1427} // End usesCustomInserter = 1 1428 1429 1430//===----------------------------------------------------------------------===// 1431// Constant Buffer Addressing Support 1432//===----------------------------------------------------------------------===// 1433 1434let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "R600" in { 1435def CONST_COPY : Instruction { 1436 let OutOperandList = (outs R600_Reg32:$dst); 1437 let InOperandList = (ins i32imm:$src); 1438 let Pattern = 1439 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))]; 1440 let AsmString = "CONST_COPY"; 1441 let hasSideEffects = 0; 1442 let isAsCheapAsAMove = 1; 1443 let Itinerary = NullALU; 1444} 1445} // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" 1446 1447def TEX_VTX_CONSTBUF : 1448 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$buffer_id), "VTX_READ_eg $dst, $ptr", 1449 [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$buffer_id)))]>, 1450 VTX_WORD1_GPR, VTX_WORD0_eg { 1451 1452 let VC_INST = 0; 1453 let FETCH_TYPE = 2; 1454 let FETCH_WHOLE_QUAD = 0; 1455 let SRC_REL = 0; 1456 let SRC_SEL_X = 0; 1457 let DST_REL = 0; 1458 let USE_CONST_FIELDS = 0; 1459 let NUM_FORMAT_ALL = 2; 1460 let FORMAT_COMP_ALL = 1; 1461 let SRF_MODE_ALL = 1; 1462 let MEGA_FETCH_COUNT = 16; 1463 let DST_SEL_X = 0; 1464 let DST_SEL_Y = 1; 1465 let DST_SEL_Z = 2; 1466 let DST_SEL_W = 3; 1467 let DATA_FORMAT = 35; 1468 1469 let Inst{31-0} = Word0; 1470 let Inst{63-32} = Word1; 1471 1472// LLVM can only encode 64-bit instructions, so these fields are manually 1473// encoded in R600CodeEmitter 1474// 1475// bits<16> OFFSET; 1476// bits<2> ENDIAN_SWAP = 0; 1477// bits<1> CONST_BUF_NO_STRIDE = 0; 1478// bits<1> MEGA_FETCH = 0; 1479// bits<1> ALT_CONST = 0; 1480// bits<2> BUFFER_INDEX_MODE = 0; 1481 1482 1483 1484// VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 1485// is done in R600CodeEmitter 1486// 1487// Inst{79-64} = OFFSET; 1488// Inst{81-80} = ENDIAN_SWAP; 1489// Inst{82} = CONST_BUF_NO_STRIDE; 1490// Inst{83} = MEGA_FETCH; 1491// Inst{84} = ALT_CONST; 1492// Inst{86-85} = BUFFER_INDEX_MODE; 1493// Inst{95-86} = 0; Reserved 1494 1495// VTX_WORD3 (Padding) 1496// 1497// Inst{127-96} = 0; 1498 let VTXInst = 1; 1499} 1500 1501def TEX_VTX_TEXBUF: 1502 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$buffer_id), "TEX_VTX_EXPLICIT_READ $dst, $ptr">, 1503VTX_WORD1_GPR, VTX_WORD0_eg { 1504 1505let VC_INST = 0; 1506let FETCH_TYPE = 2; 1507let FETCH_WHOLE_QUAD = 0; 1508let SRC_REL = 0; 1509let SRC_SEL_X = 0; 1510let DST_REL = 0; 1511let USE_CONST_FIELDS = 1; 1512let NUM_FORMAT_ALL = 0; 1513let FORMAT_COMP_ALL = 0; 1514let SRF_MODE_ALL = 1; 1515let MEGA_FETCH_COUNT = 16; 1516let DST_SEL_X = 0; 1517let DST_SEL_Y = 1; 1518let DST_SEL_Z = 2; 1519let DST_SEL_W = 3; 1520let DATA_FORMAT = 0; 1521 1522let Inst{31-0} = Word0; 1523let Inst{63-32} = Word1; 1524 1525// LLVM can only encode 64-bit instructions, so these fields are manually 1526// encoded in R600CodeEmitter 1527// 1528// bits<16> OFFSET; 1529// bits<2> ENDIAN_SWAP = 0; 1530// bits<1> CONST_BUF_NO_STRIDE = 0; 1531// bits<1> MEGA_FETCH = 0; 1532// bits<1> ALT_CONST = 0; 1533// bits<2> BUFFER_INDEX_MODE = 0; 1534 1535 1536 1537// VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 1538// is done in R600CodeEmitter 1539// 1540// Inst{79-64} = OFFSET; 1541// Inst{81-80} = ENDIAN_SWAP; 1542// Inst{82} = CONST_BUF_NO_STRIDE; 1543// Inst{83} = MEGA_FETCH; 1544// Inst{84} = ALT_CONST; 1545// Inst{86-85} = BUFFER_INDEX_MODE; 1546// Inst{95-86} = 0; Reserved 1547 1548// VTX_WORD3 (Padding) 1549// 1550// Inst{127-96} = 0; 1551 let VTXInst = 1; 1552} 1553 1554//===---------------------------------------------------------------------===// 1555// Flow and Program control Instructions 1556//===---------------------------------------------------------------------===// 1557 1558multiclass BranchConditional<SDNode Op, RegisterClass rci, RegisterClass rcf> { 1559 def _i32 : ILFormat<(outs), 1560 (ins brtarget:$target, rci:$src0), 1561 "; i32 Pseudo branch instruction", 1562 [(Op bb:$target, (i32 rci:$src0))]>; 1563 def _f32 : ILFormat<(outs), 1564 (ins brtarget:$target, rcf:$src0), 1565 "; f32 Pseudo branch instruction", 1566 [(Op bb:$target, (f32 rcf:$src0))]>; 1567} 1568 1569// Only scalar types should generate flow control 1570multiclass BranchInstr<string name> { 1571 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src), 1572 !strconcat(name, " $src"), []>; 1573 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src), 1574 !strconcat(name, " $src"), []>; 1575} 1576// Only scalar types should generate flow control 1577multiclass BranchInstr2<string name> { 1578 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1), 1579 !strconcat(name, " $src0, $src1"), []>; 1580 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1), 1581 !strconcat(name, " $src0, $src1"), []>; 1582} 1583 1584//===---------------------------------------------------------------------===// 1585// Custom Inserter for Branches and returns, this eventually will be a 1586// separate pass 1587//===---------------------------------------------------------------------===// 1588let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1, 1589 Namespace = "R600" in { 1590 def BRANCH : ILFormat<(outs), (ins brtarget:$target), 1591 "; Pseudo unconditional branch instruction", 1592 [(br bb:$target)]>; 1593 defm BRANCH_COND : BranchConditional<IL_brcond, R600_Reg32, R600_Reg32>; 1594} 1595 1596//===----------------------------------------------------------------------===// 1597// Branch Instructions 1598//===----------------------------------------------------------------------===// 1599 1600def IF_PREDICATE_SET : ILFormat<(outs), (ins R600_Reg32:$src), 1601 "IF_PREDICATE_SET $src", []>; 1602 1603let isTerminator=1 in { 1604 def BREAK : ILFormat< (outs), (ins), 1605 "BREAK", []>; 1606 def CONTINUE : ILFormat< (outs), (ins), 1607 "CONTINUE", []>; 1608 def DEFAULT : ILFormat< (outs), (ins), 1609 "DEFAULT", []>; 1610 def ELSE : ILFormat< (outs), (ins), 1611 "ELSE", []>; 1612 def ENDSWITCH : ILFormat< (outs), (ins), 1613 "ENDSWITCH", []>; 1614 def ENDMAIN : ILFormat< (outs), (ins), 1615 "ENDMAIN", []>; 1616 def END : ILFormat< (outs), (ins), 1617 "END", []>; 1618 def ENDFUNC : ILFormat< (outs), (ins), 1619 "ENDFUNC", []>; 1620 def ENDIF : ILFormat< (outs), (ins), 1621 "ENDIF", []>; 1622 def WHILELOOP : ILFormat< (outs), (ins), 1623 "WHILE", []>; 1624 def ENDLOOP : ILFormat< (outs), (ins), 1625 "ENDLOOP", []>; 1626 def FUNC : ILFormat< (outs), (ins), 1627 "FUNC", []>; 1628 def RETDYN : ILFormat< (outs), (ins), 1629 "RET_DYN", []>; 1630 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1631 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">; 1632 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1633 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">; 1634 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1635 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">; 1636 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1637 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">; 1638 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1639 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">; 1640 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1641 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">; 1642 defm IFC : BranchInstr2<"IFC">; 1643 defm BREAKC : BranchInstr2<"BREAKC">; 1644 defm CONTINUEC : BranchInstr2<"CONTINUEC">; 1645} 1646 1647//===----------------------------------------------------------------------===// 1648// Indirect addressing pseudo instructions 1649//===----------------------------------------------------------------------===// 1650 1651let isPseudo = 1 in { 1652 1653class ExtractVertical <RegisterClass vec_rc> : InstR600 < 1654 (outs R600_Reg32:$dst), 1655 (ins vec_rc:$vec, R600_Reg32:$index), "", 1656 [], 1657 AnyALU 1658>; 1659 1660let Constraints = "$dst = $vec" in { 1661 1662class InsertVertical <RegisterClass vec_rc> : InstR600 < 1663 (outs vec_rc:$dst), 1664 (ins vec_rc:$vec, R600_Reg32:$value, R600_Reg32:$index), "", 1665 [], 1666 AnyALU 1667>; 1668 1669} // End Constraints = "$dst = $vec" 1670 1671} // End isPseudo = 1 1672 1673def R600_EXTRACT_ELT_V2 : ExtractVertical <R600_Reg64Vertical>; 1674def R600_EXTRACT_ELT_V4 : ExtractVertical <R600_Reg128Vertical>; 1675 1676def R600_INSERT_ELT_V2 : InsertVertical <R600_Reg64Vertical>; 1677def R600_INSERT_ELT_V4 : InsertVertical <R600_Reg128Vertical>; 1678 1679class ExtractVerticalPat <Instruction inst, ValueType vec_ty, 1680 ValueType scalar_ty> : R600Pat < 1681 (scalar_ty (extractelt vec_ty:$vec, i32:$index)), 1682 (inst $vec, $index) 1683>; 1684 1685def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2i32, i32>; 1686def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2f32, f32>; 1687def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4i32, i32>; 1688def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4f32, f32>; 1689 1690class InsertVerticalPat <Instruction inst, ValueType vec_ty, 1691 ValueType scalar_ty> : R600Pat < 1692 (vec_ty (insertelt vec_ty:$vec, scalar_ty:$value, i32:$index)), 1693 (inst $vec, $value, $index) 1694>; 1695 1696def : InsertVerticalPat <R600_INSERT_ELT_V2, v2i32, i32>; 1697def : InsertVerticalPat <R600_INSERT_ELT_V2, v2f32, f32>; 1698def : InsertVerticalPat <R600_INSERT_ELT_V4, v4i32, i32>; 1699def : InsertVerticalPat <R600_INSERT_ELT_V4, v4f32, f32>; 1700 1701//===----------------------------------------------------------------------===// 1702// ISel Patterns 1703//===----------------------------------------------------------------------===// 1704 1705let SubtargetPredicate = isR600toCayman in { 1706 1707// CND*_INT Patterns for f32 True / False values 1708 1709class CND_INT_f32 <InstR600 cnd, CondCode cc> : R600Pat < 1710 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc), 1711 (cnd $src0, $src1, $src2) 1712>; 1713 1714def : CND_INT_f32 <CNDE_INT, SETEQ>; 1715def : CND_INT_f32 <CNDGT_INT, SETGT>; 1716def : CND_INT_f32 <CNDGE_INT, SETGE>; 1717 1718//CNDGE_INT extra pattern 1719def : R600Pat < 1720 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_SGT), 1721 (CNDGE_INT $src0, $src1, $src2) 1722>; 1723 1724// KIL Patterns 1725def KIL : R600Pat < 1726 (int_r600_kill f32:$src0), 1727 (MASK_WRITE (KILLGT (f32 ZERO), $src0)) 1728>; 1729 1730def : Extract_Element <f32, v4f32, 0, sub0>; 1731def : Extract_Element <f32, v4f32, 1, sub1>; 1732def : Extract_Element <f32, v4f32, 2, sub2>; 1733def : Extract_Element <f32, v4f32, 3, sub3>; 1734 1735def : Insert_Element <f32, v4f32, 0, sub0>; 1736def : Insert_Element <f32, v4f32, 1, sub1>; 1737def : Insert_Element <f32, v4f32, 2, sub2>; 1738def : Insert_Element <f32, v4f32, 3, sub3>; 1739 1740def : Extract_Element <i32, v4i32, 0, sub0>; 1741def : Extract_Element <i32, v4i32, 1, sub1>; 1742def : Extract_Element <i32, v4i32, 2, sub2>; 1743def : Extract_Element <i32, v4i32, 3, sub3>; 1744 1745def : Insert_Element <i32, v4i32, 0, sub0>; 1746def : Insert_Element <i32, v4i32, 1, sub1>; 1747def : Insert_Element <i32, v4i32, 2, sub2>; 1748def : Insert_Element <i32, v4i32, 3, sub3>; 1749 1750def : Extract_Element <f32, v2f32, 0, sub0>; 1751def : Extract_Element <f32, v2f32, 1, sub1>; 1752 1753def : Insert_Element <f32, v2f32, 0, sub0>; 1754def : Insert_Element <f32, v2f32, 1, sub1>; 1755 1756def : Extract_Element <i32, v2i32, 0, sub0>; 1757def : Extract_Element <i32, v2i32, 1, sub1>; 1758 1759def : Insert_Element <i32, v2i32, 0, sub0>; 1760def : Insert_Element <i32, v2i32, 1, sub1>; 1761 1762// bitconvert patterns 1763 1764def : BitConvert <i32, f32, R600_Reg32>; 1765def : BitConvert <f32, i32, R600_Reg32>; 1766def : BitConvert <v2f32, v2i32, R600_Reg64>; 1767def : BitConvert <v2i32, v2f32, R600_Reg64>; 1768def : BitConvert <v4f32, v4i32, R600_Reg128>; 1769def : BitConvert <v4i32, v4f32, R600_Reg128>; 1770 1771// DWORDADDR pattern 1772def : DwordAddrPat <i32, R600_Reg32>; 1773 1774} // End SubtargetPredicate = isR600toCayman 1775 1776def getLDSNoRetOp : InstrMapping { 1777 let FilterClass = "R600_LDS_1A1D"; 1778 let RowFields = ["BaseOp"]; 1779 let ColFields = ["DisableEncoding"]; 1780 let KeyCol = ["$dst"]; 1781 let ValueCols = [[""""]]; 1782} 1783