1//===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// TableGen definitions for instructions which are available on R600 family 10// GPUs. 11// 12//===----------------------------------------------------------------------===// 13 14include "R600InstrFormats.td" 15 16// FIXME: Should not be arbitrarily split from other R600 inst classes. 17class R600WrapperInst <dag outs, dag ins, string asm = "", list<dag> pattern = []> : 18 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl { 19 let SubtargetPredicate = isR600toCayman; 20 let Namespace = "R600"; 21} 22 23 24class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern = []> : 25 InstR600 <outs, ins, asm, pattern, NullALU> { 26 27} 28 29def MEMxi : Operand<iPTR> { 30 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index); 31 let PrintMethod = "printMemOperand"; 32} 33 34def MEMrr : Operand<iPTR> { 35 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index); 36} 37 38// Operands for non-registers 39 40class InstFlag<string PM = "printOperand", int Default = 0> 41 : OperandWithDefaultOps <i32, (ops (i32 Default))> { 42 let PrintMethod = PM; 43} 44 45// src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers 46def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))>; 47def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> { 48 let PrintMethod = "printBankSwizzle"; 49} 50 51def LITERAL : InstFlag<"printLiteral">; 52 53def WRITE : InstFlag <"printWrite", 1>; 54def OMOD : InstFlag <"printOMOD">; 55def REL : InstFlag <"printRel">; 56def CLAMP : InstFlag <"printClamp">; 57def NEG : InstFlag <"printNeg">; 58def ABS : InstFlag <"printAbs">; 59def UEM : InstFlag <"printUpdateExecMask">; 60def UP : InstFlag <"printUpdatePred">; 61 62// XXX: The r600g finalizer in Mesa expects last to be one in most cases. 63// Once we start using the packetizer in this backend we should have this 64// default to 0. 65def LAST : InstFlag<"printLast", 1>; 66def RSel : Operand<i32> { 67 let PrintMethod = "printRSel"; 68} 69def CT: Operand<i32> { 70 let PrintMethod = "printCT"; 71} 72 73def FRAMEri : Operand<iPTR> { 74 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index); 75} 76 77def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>; 78def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>; 79def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>; 80def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>; 81def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>; 82def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>; 83 84 85def R600_Pred : PredicateOperand<i32, (ops R600_Predicate), 86 (ops PRED_SEL_OFF)>; 87 88let isTerminator = 1, isReturn = 1, hasCtrlDep = 1, 89 usesCustomInserter = 1, Namespace = "R600" in { 90 def RETURN : ILFormat<(outs), (ins variable_ops), 91 "RETURN", [(AMDGPUendpgm)] 92 >; 93} 94 95let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 96 97// Class for instructions with only one source register. 98// If you add new ins to this instruction, make sure they are listed before 99// $literal, because the backend currently assumes that the last operand is 100// a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in 101// R600Defines.h, R600InstrInfo::buildDefaultInstruction(), 102// and R600InstrInfo::getOperandIdx(). 103class R600_1OP <bits<11> inst, string opName, list<dag> pattern, 104 InstrItinClass itin = AnyALU> : 105 InstR600 <(outs R600_Reg32:$dst), 106 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp, 107 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel, 108 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 109 BANK_SWIZZLE:$bank_swizzle), 110 !strconcat(" ", opName, 111 "$clamp $last $dst$write$dst_rel$omod, " 112 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, " 113 "$pred_sel $bank_swizzle"), 114 pattern, 115 itin>, 116 R600ALU_Word0, 117 R600ALU_Word1_OP2 <inst> { 118 119 let src1 = 0; 120 let src1_rel = 0; 121 let src1_neg = 0; 122 let src1_abs = 0; 123 let update_exec_mask = 0; 124 let update_pred = 0; 125 let HasNativeOperands = 1; 126 let Op1 = 1; 127 let ALUInst = 1; 128 let DisableEncoding = "$literal"; 129 let UseNamedOperandTable = 1; 130 131 let Inst{31-0} = Word0; 132 let Inst{63-32} = Word1; 133} 134 135class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node, 136 InstrItinClass itin = AnyALU> : 137 R600_1OP <inst, opName, 138 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))], itin 139>; 140 141// If you add or change the operands for R600_2OP instructions, you must 142// also update the R600Op2OperandIndex::ROI enum in R600Defines.h, 143// R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx(). 144class R600_2OP <bits<11> inst, string opName, list<dag> pattern, 145 InstrItinClass itin = AnyALU> : 146 InstR600 <(outs R600_Reg32:$dst), 147 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write, 148 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp, 149 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel, 150 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel, 151 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 152 BANK_SWIZZLE:$bank_swizzle), 153 !strconcat(" ", opName, 154 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, " 155 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, " 156 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, " 157 "$pred_sel $bank_swizzle"), 158 pattern, 159 itin>, 160 R600ALU_Word0, 161 R600ALU_Word1_OP2 <inst> { 162 163 let HasNativeOperands = 1; 164 let Op2 = 1; 165 let ALUInst = 1; 166 let DisableEncoding = "$literal"; 167 let UseNamedOperandTable = 1; 168 169 let Inst{31-0} = Word0; 170 let Inst{63-32} = Word1; 171} 172 173class R600_2OP_Helper <bits<11> inst, string opName, 174 SDPatternOperator node = null_frag, 175 InstrItinClass itin = AnyALU> : 176 R600_2OP <inst, opName, 177 [(set R600_Reg32:$dst, (node R600_Reg32:$src0, 178 R600_Reg32:$src1))], itin 179>; 180 181// If you add our change the operands for R600_3OP instructions, you must 182// also update the R600Op3OperandIndex::ROI enum in R600Defines.h, 183// R600InstrInfo::buildDefaultInstruction(), and 184// R600InstrInfo::getOperandIdx(). 185class R600_3OP <bits<5> inst, string opName, list<dag> pattern, 186 InstrItinClass itin = AnyALU> : 187 InstR600 <(outs R600_Reg32:$dst), 188 (ins REL:$dst_rel, CLAMP:$clamp, 189 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel, 190 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel, 191 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel, 192 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 193 BANK_SWIZZLE:$bank_swizzle), 194 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, " 195 "$src0_neg$src0$src0_rel, " 196 "$src1_neg$src1$src1_rel, " 197 "$src2_neg$src2$src2_rel, " 198 "$pred_sel" 199 "$bank_swizzle"), 200 pattern, 201 itin>, 202 R600ALU_Word0, 203 R600ALU_Word1_OP3<inst>{ 204 205 let HasNativeOperands = 1; 206 let DisableEncoding = "$literal"; 207 let Op3 = 1; 208 let UseNamedOperandTable = 1; 209 let ALUInst = 1; 210 211 let Inst{31-0} = Word0; 212 let Inst{63-32} = Word1; 213} 214 215class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern, 216 InstrItinClass itin = VecALU> : 217 InstR600 <(outs R600_Reg32:$dst), 218 ins, 219 asm, 220 pattern, 221 itin>; 222 223 224 225} // End mayLoad = 1, mayStore = 0, hasSideEffects = 0 226 227class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask, 228 dag outs, dag ins, string asm, list<dag> pattern> : 229 InstR600ISA <outs, ins, asm, pattern>, 230 CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF { 231 232 let rat_id = ratid; 233 let rat_inst = ratinst; 234 let rim = 0; 235 // XXX: Have a separate instruction for non-indexed writes. 236 let type = 1; 237 let rw_rel = 0; 238 let elem_size = 0; 239 240 let array_size = 0; 241 let comp_mask = mask; 242 let burst_count = 0; 243 let vpm = 0; 244 let cf_inst = cfinst; 245 let mark = 0; 246 let barrier = 1; 247 248 let Inst{31-0} = Word0; 249 let Inst{63-32} = Word1; 250 let IsExport = 1; 251 252} 253 254class VTX_READ <string name, dag outs, list<dag> pattern> 255 : InstR600ISA <outs, (ins MEMxi:$src_gpr, i8imm:$buffer_id), !strconcat(" ", name, ", #$buffer_id"), pattern>, 256 VTX_WORD1_GPR { 257 258 // Static fields 259 let DST_REL = 0; 260 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL, 261 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored, 262 // however, based on my testing if USE_CONST_FIELDS is set, then all 263 // these fields need to be set to 0. 264 let USE_CONST_FIELDS = 0; 265 let NUM_FORMAT_ALL = 1; 266 let FORMAT_COMP_ALL = 0; 267 let SRF_MODE_ALL = 0; 268 269 let Inst{63-32} = Word1; 270 // LLVM can only encode 64-bit instructions, so these fields are manually 271 // encoded in R600CodeEmitter 272 // 273 // bits<16> OFFSET; 274 // bits<2> ENDIAN_SWAP = 0; 275 // bits<1> CONST_BUF_NO_STRIDE = 0; 276 // bits<1> MEGA_FETCH = 0; 277 // bits<1> ALT_CONST = 0; 278 // bits<2> BUFFER_INDEX_MODE = 0; 279 280 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 281 // is done in R600CodeEmitter 282 // 283 // Inst{79-64} = OFFSET; 284 // Inst{81-80} = ENDIAN_SWAP; 285 // Inst{82} = CONST_BUF_NO_STRIDE; 286 // Inst{83} = MEGA_FETCH; 287 // Inst{84} = ALT_CONST; 288 // Inst{86-85} = BUFFER_INDEX_MODE; 289 // Inst{95-86} = 0; Reserved 290 291 // VTX_WORD3 (Padding) 292 // 293 // Inst{127-96} = 0; 294 295 let VTXInst = 1; 296} 297 298// Legacy. 299def atomic_cmp_swap_global_noret : PatFrag< 300 (ops node:$ptr, node:$cmp, node:$value), 301 (atomic_cmp_swap node:$ptr, node:$cmp, node:$value), 302 [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && (SDValue(N, 0).use_empty());}]>; 303 304def atomic_cmp_swap_global_ret : PatFrag< 305 (ops node:$ptr, node:$cmp, node:$value), 306 (atomic_cmp_swap node:$ptr, node:$cmp, node:$value), 307 [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && (!SDValue(N, 0).use_empty());}]>; 308 309def mskor_global : PatFrag<(ops node:$val, node:$ptr), 310 (AMDGPUstore_mskor node:$val, node:$ptr), [{ 311 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS; 312}]>; 313 314// FIXME: These are deprecated 315class AZExtLoadBase <SDPatternOperator ld_node>: PatFrag<(ops node:$ptr), 316 (ld_node node:$ptr), [{ 317 LoadSDNode *L = cast<LoadSDNode>(N); 318 return L->getExtensionType() == ISD::ZEXTLOAD || 319 L->getExtensionType() == ISD::EXTLOAD; 320}]>; 321 322def az_extload : AZExtLoadBase <unindexedload>; 323 324def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{ 325 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 326}]>; 327 328def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{ 329 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 330}]>; 331 332def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{ 333 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 334}]>; 335 336let AddressSpaces = LoadAddress_local.AddrSpaces in { 337def az_extloadi8_local : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr)>; 338def az_extloadi16_local : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr)>; 339} 340 341class LoadParamFrag <PatFrag load_type> : PatFrag < 342 (ops node:$ptr), (load_type node:$ptr), 343 [{ return isConstantLoad(cast<LoadSDNode>(N), 0) || 344 (cast<LoadSDNode>(N)->getAddressSpace() == AMDGPUAS::PARAM_I_ADDRESS); }] 345>; 346 347def vtx_id3_az_extloadi8 : LoadParamFrag<az_extloadi8>; 348def vtx_id3_az_extloadi16 : LoadParamFrag<az_extloadi16>; 349def vtx_id3_load : LoadParamFrag<load>; 350 351class LoadVtxId1 <PatFrag load> : PatFrag < 352 (ops node:$ptr), (load node:$ptr), [{ 353 const MemSDNode *LD = cast<MemSDNode>(N); 354 return LD->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS || 355 (LD->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS && 356 !isa<GlobalValue>(GetUnderlyingObject( 357 LD->getMemOperand()->getValue(), CurDAG->getDataLayout()))); 358}]>; 359 360def vtx_id1_az_extloadi8 : LoadVtxId1 <az_extloadi8>; 361def vtx_id1_az_extloadi16 : LoadVtxId1 <az_extloadi16>; 362def vtx_id1_load : LoadVtxId1 <load>; 363 364class LoadVtxId2 <PatFrag load> : PatFrag < 365 (ops node:$ptr), (load node:$ptr), [{ 366 const MemSDNode *LD = cast<MemSDNode>(N); 367 return LD->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS && 368 isa<GlobalValue>(GetUnderlyingObject( 369 LD->getMemOperand()->getValue(), CurDAG->getDataLayout())); 370}]>; 371 372def vtx_id2_az_extloadi8 : LoadVtxId2 <az_extloadi8>; 373def vtx_id2_az_extloadi16 : LoadVtxId2 <az_extloadi16>; 374def vtx_id2_load : LoadVtxId2 <load>; 375 376//===----------------------------------------------------------------------===// 377// R600 SDNodes 378//===----------------------------------------------------------------------===// 379 380let Namespace = "R600" in { 381 382def INTERP_PAIR_XY : AMDGPUShaderInst < 383 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1), 384 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2), 385 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1", 386 []>; 387 388def INTERP_PAIR_ZW : AMDGPUShaderInst < 389 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1), 390 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2), 391 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1", 392 []>; 393 394} 395 396def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS", 397 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>, 398 [SDNPVariadic] 399>; 400 401def DOT4 : SDNode<"AMDGPUISD::DOT4", 402 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>, 403 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>, 404 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>, 405 [] 406>; 407 408def COS_HW : SDNode<"AMDGPUISD::COS_HW", 409 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]> 410>; 411 412def SIN_HW : SDNode<"AMDGPUISD::SIN_HW", 413 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]> 414>; 415 416def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>; 417 418def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>; 419 420multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> { 421def : R600Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR, 422 (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw), 423 (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz), 424 (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z), 425 (i32 imm:$DST_SEL_W), 426 (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID), 427 (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z), 428 (i32 imm:$COORD_TYPE_W)), 429 (inst R600_Reg128:$SRC_GPR, 430 imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw, 431 imm:$offsetx, imm:$offsety, imm:$offsetz, 432 imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z, 433 imm:$DST_SEL_W, 434 imm:$RESOURCE_ID, imm:$SAMPLER_ID, 435 imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z, 436 imm:$COORD_TYPE_W)>; 437} 438 439//===----------------------------------------------------------------------===// 440// Interpolation Instructions 441//===----------------------------------------------------------------------===// 442 443let Namespace = "R600" in { 444 445def INTERP_VEC_LOAD : AMDGPUShaderInst < 446 (outs R600_Reg128:$dst), 447 (ins i32imm:$src0), 448 "INTERP_LOAD $src0 : $dst">; 449 450} 451 452def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> { 453 let bank_swizzle = 5; 454} 455 456def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> { 457 let bank_swizzle = 5; 458} 459 460def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>; 461 462//===----------------------------------------------------------------------===// 463// Export Instructions 464//===----------------------------------------------------------------------===// 465 466class ExportWord0 { 467 field bits<32> Word0; 468 469 bits<13> arraybase; 470 bits<2> type; 471 bits<7> gpr; 472 bits<2> elem_size; 473 474 let Word0{12-0} = arraybase; 475 let Word0{14-13} = type; 476 let Word0{21-15} = gpr; 477 let Word0{22} = 0; // RW_REL 478 let Word0{29-23} = 0; // INDEX_GPR 479 let Word0{31-30} = elem_size; 480} 481 482class ExportSwzWord1 { 483 field bits<32> Word1; 484 485 bits<3> sw_x; 486 bits<3> sw_y; 487 bits<3> sw_z; 488 bits<3> sw_w; 489 bits<1> eop; 490 bits<8> inst; 491 492 let Word1{2-0} = sw_x; 493 let Word1{5-3} = sw_y; 494 let Word1{8-6} = sw_z; 495 let Word1{11-9} = sw_w; 496} 497 498class ExportBufWord1 { 499 field bits<32> Word1; 500 501 bits<12> arraySize; 502 bits<4> compMask; 503 bits<1> eop; 504 bits<8> inst; 505 506 let Word1{11-0} = arraySize; 507 let Word1{15-12} = compMask; 508} 509 510multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> { 511 def : R600Pat<(R600_EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type), 512 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)), 513 (ExportInst R600_Reg128:$src, imm:$type, imm:$base, 514 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0) 515 >; 516 517} 518 519multiclass SteamOutputExportPattern<Instruction ExportInst, 520 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> { 521// Stream0 522 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), 523 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)), 524 (ExportInst R600_Reg128:$src, 0, imm:$arraybase, 525 4095, imm:$mask, buf0inst, 0)>; 526// Stream1 527 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), 528 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)), 529 (ExportInst $src, 0, imm:$arraybase, 530 4095, imm:$mask, buf1inst, 0)>; 531// Stream2 532 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), 533 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)), 534 (ExportInst $src, 0, imm:$arraybase, 535 4095, imm:$mask, buf2inst, 0)>; 536// Stream3 537 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), 538 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)), 539 (ExportInst $src, 0, imm:$arraybase, 540 4095, imm:$mask, buf3inst, 0)>; 541} 542 543// Export Instructions should not be duplicated by TailDuplication pass 544// (which assumes that duplicable instruction are affected by exec mask) 545let usesCustomInserter = 1, isNotDuplicable = 1 in { 546 547class ExportSwzInst : InstR600ISA<( 548 outs), 549 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase, 550 RSel:$sw_x, RSel:$sw_y, RSel:$sw_z, RSel:$sw_w, i32imm:$inst, 551 i32imm:$eop), 552 !strconcat("EXPORT", " $gpr.$sw_x$sw_y$sw_z$sw_w"), 553 []>, ExportWord0, ExportSwzWord1 { 554 let elem_size = 3; 555 let Inst{31-0} = Word0; 556 let Inst{63-32} = Word1; 557 let IsExport = 1; 558} 559 560} // End usesCustomInserter = 1 561 562class ExportBufInst : InstR600ISA<( 563 outs), 564 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase, 565 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop), 566 !strconcat("EXPORT", " $gpr"), 567 []>, ExportWord0, ExportBufWord1 { 568 let elem_size = 0; 569 let Inst{31-0} = Word0; 570 let Inst{63-32} = Word1; 571 let IsExport = 1; 572} 573 574//===----------------------------------------------------------------------===// 575// Control Flow Instructions 576//===----------------------------------------------------------------------===// 577 578 579def KCACHE : InstFlag<"printKCache">; 580 581class ALU_CLAUSE<bits<4> inst, string OpName> : R600WrapperInst <(outs), 582(ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1, 583KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1, 584i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1, 585i32imm:$COUNT, i32imm:$Enabled), 586!strconcat(OpName, " $COUNT, @$ADDR, " 587"KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"), 588[] >, CF_ALU_WORD0, CF_ALU_WORD1 { 589 field bits<64> Inst; 590 591 let CF_INST = inst; 592 let ALT_CONST = 0; 593 let WHOLE_QUAD_MODE = 0; 594 let BARRIER = 1; 595 let isCodeGenOnly = 1; 596 let UseNamedOperandTable = 1; 597 598 let Inst{31-0} = Word0; 599 let Inst{63-32} = Word1; 600} 601 602class CF_WORD0_R600 { 603 field bits<32> Word0; 604 605 bits<32> ADDR; 606 607 let Word0 = ADDR; 608} 609 610class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : R600WrapperInst <(outs), 611ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 { 612 field bits<64> Inst; 613 bits<4> CNT; 614 615 let CF_INST = inst; 616 let BARRIER = 1; 617 let CF_CONST = 0; 618 let VALID_PIXEL_MODE = 0; 619 let COND = 0; 620 let COUNT = CNT{2-0}; 621 let CALL_COUNT = 0; 622 let COUNT_3 = CNT{3}; 623 let END_OF_PROGRAM = 0; 624 let WHOLE_QUAD_MODE = 0; 625 626 let Inst{31-0} = Word0; 627 let Inst{63-32} = Word1; 628} 629 630class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : R600WrapperInst <(outs), 631ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG { 632 field bits<64> Inst; 633 634 let CF_INST = inst; 635 let BARRIER = 1; 636 let JUMPTABLE_SEL = 0; 637 let CF_CONST = 0; 638 let VALID_PIXEL_MODE = 0; 639 let COND = 0; 640 let END_OF_PROGRAM = 0; 641 642 let Inst{31-0} = Word0; 643 let Inst{63-32} = Word1; 644} 645 646def CF_ALU : ALU_CLAUSE<8, "ALU">; 647def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">; 648def CF_ALU_POP_AFTER : ALU_CLAUSE<10, "ALU_POP_AFTER">; 649def CF_ALU_CONTINUE : ALU_CLAUSE<13, "ALU_CONTINUE">; 650def CF_ALU_BREAK : ALU_CLAUSE<14, "ALU_BREAK">; 651def CF_ALU_ELSE_AFTER : ALU_CLAUSE<15, "ALU_ELSE_AFTER">; 652 653def FETCH_CLAUSE : R600WrapperInst <(outs), 654(ins i32imm:$addr), "Fetch clause starting at $addr:", [] > { 655 field bits<8> Inst; 656 bits<8> num; 657 let Inst = num; 658 let isCodeGenOnly = 1; 659} 660 661def ALU_CLAUSE : R600WrapperInst <(outs), 662(ins i32imm:$addr), "ALU clause starting at $addr:", [] > { 663 field bits<8> Inst; 664 bits<8> num; 665 let Inst = num; 666 let isCodeGenOnly = 1; 667} 668 669def LITERALS : R600WrapperInst <(outs), 670(ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > { 671 let isCodeGenOnly = 1; 672 673 field bits<64> Inst; 674 bits<32> literal1; 675 bits<32> literal2; 676 677 let Inst{31-0} = literal1; 678 let Inst{63-32} = literal2; 679} 680 681def PAD : R600WrapperInst <(outs), (ins), "PAD", [] > { 682 field bits<64> Inst; 683} 684 685//===----------------------------------------------------------------------===// 686// Common Instructions R600, R700, Evergreen, Cayman 687//===----------------------------------------------------------------------===// 688 689let isCodeGenOnly = 1, isPseudo = 1 in { 690 691let Namespace = "R600", usesCustomInserter = 1 in { 692 693class FABS <RegisterClass rc> : AMDGPUShaderInst < 694 (outs rc:$dst), 695 (ins rc:$src0), 696 "FABS $dst, $src0", 697 [(set f32:$dst, (fabs f32:$src0))] 698>; 699 700class FNEG <RegisterClass rc> : AMDGPUShaderInst < 701 (outs rc:$dst), 702 (ins rc:$src0), 703 "FNEG $dst, $src0", 704 [(set f32:$dst, (fneg f32:$src0))] 705>; 706 707} // usesCustomInserter = 1 708 709multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass, 710 ComplexPattern addrPat> { 711let UseNamedOperandTable = 1 in { 712 713 def RegisterLoad : AMDGPUShaderInst < 714 (outs dstClass:$dst), 715 (ins addrClass:$addr, i32imm:$chan), 716 "RegisterLoad $dst, $addr", 717 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))] 718 > { 719 let isRegisterLoad = 1; 720 } 721 722 def RegisterStore : AMDGPUShaderInst < 723 (outs), 724 (ins dstClass:$val, addrClass:$addr, i32imm:$chan), 725 "RegisterStore $val, $addr", 726 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))] 727 > { 728 let isRegisterStore = 1; 729 } 730} 731} 732 733} // End isCodeGenOnly = 1, isPseudo = 1 734 735 736def ADD : R600_2OP_Helper <0x0, "ADD", fadd>; 737// Non-IEEE MUL: 0 * anything = 0 738def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE">; 739def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>; 740// TODO: Do these actually match the regular fmin/fmax behavior? 741def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax_legacy>; 742def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin_legacy>; 743// According to https://msdn.microsoft.com/en-us/library/windows/desktop/cc308050%28v=vs.85%29.aspx 744// DX10 min/max returns the other operand if one is NaN, 745// this matches http://llvm.org/docs/LangRef.html#llvm-minnum-intrinsic 746def MAX_DX10 : R600_2OP_Helper <0x5, "MAX_DX10", fmaxnum>; 747def MIN_DX10 : R600_2OP_Helper <0x6, "MIN_DX10", fminnum>; 748 749// For the SET* instructions there is a naming conflict in TargetSelectionDAG.td, 750// so some of the instruction names don't match the asm string. 751// XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics. 752def SETE : R600_2OP < 753 0x08, "SETE", 754 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OEQ))] 755>; 756 757def SGT : R600_2OP < 758 0x09, "SETGT", 759 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGT))] 760>; 761 762def SGE : R600_2OP < 763 0xA, "SETGE", 764 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGE))] 765>; 766 767def SNE : R600_2OP < 768 0xB, "SETNE", 769 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_UNE_NE))] 770>; 771 772def SETE_DX10 : R600_2OP < 773 0xC, "SETE_DX10", 774 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OEQ))] 775>; 776 777def SETGT_DX10 : R600_2OP < 778 0xD, "SETGT_DX10", 779 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGT))] 780>; 781 782def SETGE_DX10 : R600_2OP < 783 0xE, "SETGE_DX10", 784 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGE))] 785>; 786 787// FIXME: This should probably be COND_ONE 788def SETNE_DX10 : R600_2OP < 789 0xF, "SETNE_DX10", 790 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_UNE_NE))] 791>; 792 793// FIXME: Need combine for AMDGPUfract 794def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>; 795def TRUNC : R600_1OP_Helper <0x11, "TRUNC", ftrunc>; 796def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>; 797def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>; 798def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>; 799 800def MOV : R600_1OP <0x19, "MOV", []>; 801 802 803// This is a hack to get rid of DUMMY_CHAIN nodes. 804// Most DUMMY_CHAINs should be eliminated during legalization, but undef 805// values can sneak in some to selection. 806let isPseudo = 1, isCodeGenOnly = 1 in { 807def DUMMY_CHAIN : R600WrapperInst < 808 (outs), 809 (ins), 810 "DUMMY_CHAIN", 811 [(R600dummy_chain)] 812>; 813} // end let isPseudo = 1, isCodeGenOnly = 1 814 815 816let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in { 817 818class MOV_IMM <ValueType vt, Operand immType> : R600WrapperInst < 819 (outs R600_Reg32:$dst), 820 (ins immType:$imm), 821 "", 822 [] 823> { 824 let Namespace = "R600"; 825} 826 827} // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 828 829def MOV_IMM_I32 : MOV_IMM<i32, i32imm>; 830def : R600Pat < 831 (imm:$val), 832 (MOV_IMM_I32 imm:$val) 833>; 834 835def MOV_IMM_GLOBAL_ADDR : MOV_IMM<iPTR, i32imm>; 836def : R600Pat < 837 (AMDGPUconstdata_ptr tglobaladdr:$addr), 838 (MOV_IMM_GLOBAL_ADDR tglobaladdr:$addr) 839>; 840 841 842def MOV_IMM_F32 : MOV_IMM<f32, f32imm>; 843def : R600Pat < 844 (fpimm:$val), 845 (MOV_IMM_F32 fpimm:$val) 846>; 847 848def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>; 849def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>; 850def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>; 851def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>; 852 853let hasSideEffects = 1 in { 854 855def KILLGT : R600_2OP <0x2D, "KILLGT", []>; 856 857} // end hasSideEffects 858 859def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>; 860def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>; 861def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>; 862def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>; 863def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>; 864def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>; 865def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", smax>; 866def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", smin>; 867def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", umax>; 868def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", umin>; 869 870def SETE_INT : R600_2OP < 871 0x3A, "SETE_INT", 872 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))] 873>; 874 875def SETGT_INT : R600_2OP < 876 0x3B, "SETGT_INT", 877 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))] 878>; 879 880def SETGE_INT : R600_2OP < 881 0x3C, "SETGE_INT", 882 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))] 883>; 884 885def SETNE_INT : R600_2OP < 886 0x3D, "SETNE_INT", 887 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))] 888>; 889 890def SETGT_UINT : R600_2OP < 891 0x3E, "SETGT_UINT", 892 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))] 893>; 894 895def SETGE_UINT : R600_2OP < 896 0x3F, "SETGE_UINT", 897 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))] 898>; 899 900def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>; 901def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>; 902def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>; 903def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>; 904 905def CNDE_INT : R600_3OP < 906 0x1C, "CNDE_INT", 907 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))] 908>; 909 910def CNDGE_INT : R600_3OP < 911 0x1E, "CNDGE_INT", 912 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGE))] 913>; 914 915def CNDGT_INT : R600_3OP < 916 0x1D, "CNDGT_INT", 917 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGT))] 918>; 919 920//===----------------------------------------------------------------------===// 921// Texture instructions 922//===----------------------------------------------------------------------===// 923 924let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 925 926class R600_TEX <bits<11> inst, string opName> : 927 InstR600 <(outs R600_Reg128:$DST_GPR), 928 (ins R600_Reg128:$SRC_GPR, 929 RSel:$srcx, RSel:$srcy, RSel:$srcz, RSel:$srcw, 930 i32imm:$offsetx, i32imm:$offsety, i32imm:$offsetz, 931 RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W, 932 i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID, 933 CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z, 934 CT:$COORD_TYPE_W), 935 !strconcat(" ", opName, 936 " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, " 937 "$SRC_GPR.$srcx$srcy$srcz$srcw " 938 "RID:$RESOURCE_ID SID:$SAMPLER_ID " 939 "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"), 940 [], 941 NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 { 942 let Inst{31-0} = Word0; 943 let Inst{63-32} = Word1; 944 945 let TEX_INST = inst{4-0}; 946 let SRC_REL = 0; 947 let DST_REL = 0; 948 let LOD_BIAS = 0; 949 950 let INST_MOD = 0; 951 let FETCH_WHOLE_QUAD = 0; 952 let ALT_CONST = 0; 953 let SAMPLER_INDEX_MODE = 0; 954 let RESOURCE_INDEX_MODE = 0; 955 956 let TEXInst = 1; 957} 958 959} // End mayLoad = 0, mayStore = 0, hasSideEffects = 0 960 961 962 963def TEX_SAMPLE : R600_TEX <0x10, "TEX_SAMPLE">; 964def TEX_SAMPLE_C : R600_TEX <0x18, "TEX_SAMPLE_C">; 965def TEX_SAMPLE_L : R600_TEX <0x11, "TEX_SAMPLE_L">; 966def TEX_SAMPLE_C_L : R600_TEX <0x19, "TEX_SAMPLE_C_L">; 967def TEX_SAMPLE_LB : R600_TEX <0x12, "TEX_SAMPLE_LB">; 968def TEX_SAMPLE_C_LB : R600_TEX <0x1A, "TEX_SAMPLE_C_LB">; 969def TEX_LD : R600_TEX <0x03, "TEX_LD">; 970def TEX_LDPTR : R600_TEX <0x03, "TEX_LDPTR"> { 971 let INST_MOD = 1; 972} 973def TEX_GET_TEXTURE_RESINFO : R600_TEX <0x04, "TEX_GET_TEXTURE_RESINFO">; 974def TEX_GET_GRADIENTS_H : R600_TEX <0x07, "TEX_GET_GRADIENTS_H">; 975def TEX_GET_GRADIENTS_V : R600_TEX <0x08, "TEX_GET_GRADIENTS_V">; 976def TEX_SET_GRADIENTS_H : R600_TEX <0x0B, "TEX_SET_GRADIENTS_H">; 977def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">; 978def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">; 979def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">; 980 981defm : TexPattern<0, TEX_SAMPLE>; 982defm : TexPattern<1, TEX_SAMPLE_C>; 983defm : TexPattern<2, TEX_SAMPLE_L>; 984defm : TexPattern<3, TEX_SAMPLE_C_L>; 985defm : TexPattern<4, TEX_SAMPLE_LB>; 986defm : TexPattern<5, TEX_SAMPLE_C_LB>; 987defm : TexPattern<6, TEX_LD, v4i32>; 988defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>; 989defm : TexPattern<8, TEX_GET_GRADIENTS_H>; 990defm : TexPattern<9, TEX_GET_GRADIENTS_V>; 991defm : TexPattern<10, TEX_LDPTR, v4i32>; 992 993//===----------------------------------------------------------------------===// 994// Helper classes for common instructions 995//===----------------------------------------------------------------------===// 996 997class MUL_LIT_Common <bits<5> inst> : R600_3OP < 998 inst, "MUL_LIT", 999 [] 1000>; 1001 1002class MULADD_Common <bits<5> inst> : R600_3OP < 1003 inst, "MULADD", 1004 [] 1005>; 1006 1007class MULADD_IEEE_Common <bits<5> inst> : R600_3OP < 1008 inst, "MULADD_IEEE", 1009 [(set f32:$dst, (any_fmad f32:$src0, f32:$src1, f32:$src2))] 1010>; 1011 1012class FMA_Common <bits<5> inst> : R600_3OP < 1013 inst, "FMA", 1014 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))], VecALU 1015> 1016{ 1017 let OtherPredicates = [FMA]; 1018} 1019 1020class CNDE_Common <bits<5> inst> : R600_3OP < 1021 inst, "CNDE", 1022 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OEQ))] 1023>; 1024 1025class CNDGT_Common <bits<5> inst> : R600_3OP < 1026 inst, "CNDGT", 1027 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGT))] 1028> { 1029 let Itinerary = VecALU; 1030} 1031 1032class CNDGE_Common <bits<5> inst> : R600_3OP < 1033 inst, "CNDGE", 1034 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGE))] 1035> { 1036 let Itinerary = VecALU; 1037} 1038 1039 1040let isCodeGenOnly = 1, isPseudo = 1, Namespace = "R600" in { 1041class R600_VEC2OP<list<dag> pattern> : InstR600 <(outs R600_Reg32:$dst), (ins 1042// Slot X 1043 UEM:$update_exec_mask_X, UP:$update_pred_X, WRITE:$write_X, 1044 OMOD:$omod_X, REL:$dst_rel_X, CLAMP:$clamp_X, 1045 R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X, 1046 R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X, 1047 R600_Pred:$pred_sel_X, 1048// Slot Y 1049 UEM:$update_exec_mask_Y, UP:$update_pred_Y, WRITE:$write_Y, 1050 OMOD:$omod_Y, REL:$dst_rel_Y, CLAMP:$clamp_Y, 1051 R600_TReg32_Y:$src0_Y, NEG:$src0_neg_Y, REL:$src0_rel_Y, ABS:$src0_abs_Y, SEL:$src0_sel_Y, 1052 R600_TReg32_Y:$src1_Y, NEG:$src1_neg_Y, REL:$src1_rel_Y, ABS:$src1_abs_Y, SEL:$src1_sel_Y, 1053 R600_Pred:$pred_sel_Y, 1054// Slot Z 1055 UEM:$update_exec_mask_Z, UP:$update_pred_Z, WRITE:$write_Z, 1056 OMOD:$omod_Z, REL:$dst_rel_Z, CLAMP:$clamp_Z, 1057 R600_TReg32_Z:$src0_Z, NEG:$src0_neg_Z, REL:$src0_rel_Z, ABS:$src0_abs_Z, SEL:$src0_sel_Z, 1058 R600_TReg32_Z:$src1_Z, NEG:$src1_neg_Z, REL:$src1_rel_Z, ABS:$src1_abs_Z, SEL:$src1_sel_Z, 1059 R600_Pred:$pred_sel_Z, 1060// Slot W 1061 UEM:$update_exec_mask_W, UP:$update_pred_W, WRITE:$write_W, 1062 OMOD:$omod_W, REL:$dst_rel_W, CLAMP:$clamp_W, 1063 R600_TReg32_W:$src0_W, NEG:$src0_neg_W, REL:$src0_rel_W, ABS:$src0_abs_W, SEL:$src0_sel_W, 1064 R600_TReg32_W:$src1_W, NEG:$src1_neg_W, REL:$src1_rel_W, ABS:$src1_abs_W, SEL:$src1_sel_W, 1065 R600_Pred:$pred_sel_W, 1066 LITERAL:$literal0, LITERAL:$literal1), 1067 "", 1068 pattern, 1069 AnyALU> { 1070 1071 let UseNamedOperandTable = 1; 1072 1073} 1074} 1075 1076def DOT_4 : R600_VEC2OP<[(set R600_Reg32:$dst, (DOT4 1077 R600_TReg32_X:$src0_X, R600_TReg32_X:$src1_X, 1078 R600_TReg32_Y:$src0_Y, R600_TReg32_Y:$src1_Y, 1079 R600_TReg32_Z:$src0_Z, R600_TReg32_Z:$src1_Z, 1080 R600_TReg32_W:$src0_W, R600_TReg32_W:$src1_W))]>; 1081 1082 1083class DOT4_Common <bits<11> inst> : R600_2OP <inst, "DOT4", []>; 1084 1085 1086let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 1087multiclass CUBE_Common <bits<11> inst> { 1088 1089 def _pseudo : InstR600 < 1090 (outs R600_Reg128:$dst), 1091 (ins R600_Reg128:$src0), 1092 "CUBE $dst $src0", 1093 [(set v4f32:$dst, (int_r600_cube v4f32:$src0))], 1094 VecALU 1095 > { 1096 let isPseudo = 1; 1097 let UseNamedOperandTable = 1; 1098 } 1099 1100 def _real : R600_2OP <inst, "CUBE", []>; 1101} 1102} // End mayLoad = 0, mayStore = 0, hasSideEffects = 0 1103 1104class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1105 inst, "EXP_IEEE", fexp2 1106> { 1107 let Itinerary = TransALU; 1108} 1109 1110class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper < 1111 inst, "FLT_TO_INT", fp_to_sint 1112> { 1113 let Itinerary = TransALU; 1114} 1115 1116class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper < 1117 inst, "INT_TO_FLT", sint_to_fp 1118> { 1119 let Itinerary = TransALU; 1120} 1121 1122class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper < 1123 inst, "FLT_TO_UINT", fp_to_uint 1124> { 1125 let Itinerary = TransALU; 1126} 1127 1128class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper < 1129 inst, "UINT_TO_FLT", uint_to_fp 1130> { 1131 let Itinerary = TransALU; 1132} 1133 1134class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP < 1135 inst, "LOG_CLAMPED", [] 1136>; 1137 1138class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1139 inst, "LOG_IEEE", flog2 1140> { 1141 let Itinerary = TransALU; 1142} 1143 1144class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>; 1145class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>; 1146class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>; 1147class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper < 1148 inst, "MULHI_INT", mulhs> { 1149 let Itinerary = TransALU; 1150} 1151 1152class MULHI_INT24_Common <bits<11> inst> : R600_2OP_Helper < 1153 inst, "MULHI_INT24", AMDGPUmulhi_i24> { 1154 let Itinerary = VecALU; 1155} 1156 1157class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper < 1158 inst, "MULHI", mulhu> { 1159 let Itinerary = TransALU; 1160} 1161 1162class MULHI_UINT24_Common <bits<11> inst> : R600_2OP_Helper < 1163 inst, "MULHI_UINT24", AMDGPUmulhi_u24> { 1164 let Itinerary = VecALU; 1165} 1166 1167class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper < 1168 inst, "MULLO_INT", mul> { 1169 let Itinerary = TransALU; 1170} 1171class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> { 1172 let Itinerary = TransALU; 1173} 1174 1175class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP < 1176 inst, "RECIP_CLAMPED", [] 1177> { 1178 let Itinerary = TransALU; 1179} 1180 1181class RECIP_IEEE_Common <bits<11> inst> : R600_1OP < 1182 inst, "RECIP_IEEE", [(set f32:$dst, (AMDGPUrcp f32:$src0))] 1183> { 1184 let Itinerary = TransALU; 1185} 1186 1187class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper < 1188 inst, "RECIP_UINT", AMDGPUurecip 1189> { 1190 let Itinerary = TransALU; 1191} 1192 1193// Clamped to maximum. 1194class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper < 1195 inst, "RECIPSQRT_CLAMPED", AMDGPUrsq_clamp 1196> { 1197 let Itinerary = TransALU; 1198} 1199 1200class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1201 inst, "RECIPSQRT_IEEE", AMDGPUrsq> { 1202 let Itinerary = TransALU; 1203} 1204 1205// TODO: There is also RECIPSQRT_FF which clamps to zero. 1206 1207class SIN_Common <bits<11> inst> : R600_1OP < 1208 inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{ 1209 let Trig = 1; 1210 let Itinerary = TransALU; 1211} 1212 1213class COS_Common <bits<11> inst> : R600_1OP < 1214 inst, "COS", [(set f32:$dst, (COS_HW f32:$src0))]> { 1215 let Trig = 1; 1216 let Itinerary = TransALU; 1217} 1218 1219def FABS_R600 : FABS<R600_Reg32>; 1220def FNEG_R600 : FNEG<R600_Reg32>; 1221 1222//===----------------------------------------------------------------------===// 1223// Helper patterns for complex intrinsics 1224//===----------------------------------------------------------------------===// 1225 1226// FIXME: Should be predicated on unsafe fp math. 1227multiclass DIV_Common <InstR600 recip_ieee> { 1228def : R600Pat< 1229 (fdiv f32:$src0, f32:$src1), 1230 (MUL_IEEE $src0, (recip_ieee $src1)) 1231>; 1232 1233def : RcpPat<recip_ieee, f32>; 1234} 1235 1236class SqrtPat<Instruction RsqInst, Instruction RecipInst> : R600Pat < 1237 (fsqrt f32:$src), 1238 (RecipInst (RsqInst $src)) 1239>; 1240 1241//===----------------------------------------------------------------------===// 1242// R600 / R700 Instructions 1243//===----------------------------------------------------------------------===// 1244 1245let Predicates = [isR600] in { 1246 1247 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>; 1248 def MULADD_r600 : MULADD_Common<0x10>; 1249 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>; 1250 def CNDE_r600 : CNDE_Common<0x18>; 1251 def CNDGT_r600 : CNDGT_Common<0x19>; 1252 def CNDGE_r600 : CNDGE_Common<0x1A>; 1253 def DOT4_r600 : DOT4_Common<0x50>; 1254 defm CUBE_r600 : CUBE_Common<0x52>; 1255 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>; 1256 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>; 1257 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>; 1258 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>; 1259 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>; 1260 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>; 1261 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>; 1262 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>; 1263 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>; 1264 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>; 1265 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>; 1266 def SIN_r600 : SIN_Common<0x6E>; 1267 def COS_r600 : COS_Common<0x6F>; 1268 def ASHR_r600 : ASHR_Common<0x70>; 1269 def LSHR_r600 : LSHR_Common<0x71>; 1270 def LSHL_r600 : LSHL_Common<0x72>; 1271 def MULLO_INT_r600 : MULLO_INT_Common<0x73>; 1272 def MULHI_INT_r600 : MULHI_INT_Common<0x74>; 1273 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>; 1274 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>; 1275 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>; 1276 1277 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>; 1278 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>; 1279 1280 def : RsqPat<RECIPSQRT_IEEE_r600, f32>; 1281 def : SqrtPat<RECIPSQRT_IEEE_r600, RECIP_IEEE_r600>; 1282 1283 def R600_ExportSwz : ExportSwzInst { 1284 let Word1{20-17} = 0; // BURST_COUNT 1285 let Word1{21} = eop; 1286 let Word1{22} = 0; // VALID_PIXEL_MODE 1287 let Word1{30-23} = inst; 1288 let Word1{31} = 1; // BARRIER 1289 } 1290 defm : ExportPattern<R600_ExportSwz, 39>; 1291 1292 def R600_ExportBuf : ExportBufInst { 1293 let Word1{20-17} = 0; // BURST_COUNT 1294 let Word1{21} = eop; 1295 let Word1{22} = 0; // VALID_PIXEL_MODE 1296 let Word1{30-23} = inst; 1297 let Word1{31} = 1; // BARRIER 1298 } 1299 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>; 1300 1301 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$CNT), 1302 "TEX $CNT @$ADDR"> { 1303 let POP_COUNT = 0; 1304 } 1305 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$CNT), 1306 "VTX $CNT @$ADDR"> { 1307 let POP_COUNT = 0; 1308 } 1309 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR), 1310 "LOOP_START_DX10 @$ADDR"> { 1311 let POP_COUNT = 0; 1312 let CNT = 0; 1313 } 1314 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> { 1315 let POP_COUNT = 0; 1316 let CNT = 0; 1317 } 1318 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR), 1319 "LOOP_BREAK @$ADDR"> { 1320 let POP_COUNT = 0; 1321 let CNT = 0; 1322 } 1323 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR), 1324 "CONTINUE @$ADDR"> { 1325 let POP_COUNT = 0; 1326 let CNT = 0; 1327 } 1328 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1329 "JUMP @$ADDR POP:$POP_COUNT"> { 1330 let CNT = 0; 1331 } 1332 def CF_PUSH_ELSE_R600 : CF_CLAUSE_R600<12, (ins i32imm:$ADDR), 1333 "PUSH_ELSE @$ADDR"> { 1334 let CNT = 0; 1335 let POP_COUNT = 0; // FIXME? 1336 } 1337 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1338 "ELSE @$ADDR POP:$POP_COUNT"> { 1339 let CNT = 0; 1340 } 1341 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> { 1342 let ADDR = 0; 1343 let CNT = 0; 1344 let POP_COUNT = 0; 1345 } 1346 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1347 "POP @$ADDR POP:$POP_COUNT"> { 1348 let CNT = 0; 1349 } 1350 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> { 1351 let CNT = 0; 1352 let POP_COUNT = 0; 1353 let ADDR = 0; 1354 let END_OF_PROGRAM = 1; 1355 } 1356 1357} 1358 1359 1360//===----------------------------------------------------------------------===// 1361// Regist loads and stores - for indirect addressing 1362//===----------------------------------------------------------------------===// 1363 1364let Namespace = "R600" in { 1365defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>; 1366} 1367 1368// Hardcode channel to 0 1369// NOTE: LSHR is not available here. LSHR is per family instruction 1370def : R600Pat < 1371 (i32 (load_private ADDRIndirect:$addr) ), 1372 (R600_RegisterLoad FRAMEri:$addr, (i32 0)) 1373>; 1374def : R600Pat < 1375 (store_private i32:$val, ADDRIndirect:$addr), 1376 (R600_RegisterStore i32:$val, FRAMEri:$addr, (i32 0)) 1377>; 1378 1379 1380//===----------------------------------------------------------------------===// 1381// Pseudo instructions 1382//===----------------------------------------------------------------------===// 1383 1384let isPseudo = 1 in { 1385 1386def PRED_X : InstR600 < 1387 (outs R600_Predicate_Bit:$dst), 1388 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags), 1389 "", [], NullALU> { 1390 let FlagOperandIdx = 3; 1391} 1392 1393let isTerminator = 1, isBranch = 1 in { 1394def JUMP_COND : InstR600 < 1395 (outs), 1396 (ins brtarget:$target, R600_Predicate_Bit:$p), 1397 "JUMP $target ($p)", 1398 [], AnyALU 1399 >; 1400 1401def JUMP : InstR600 < 1402 (outs), 1403 (ins brtarget:$target), 1404 "JUMP $target", 1405 [], AnyALU 1406 > 1407{ 1408 let isPredicable = 1; 1409 let isBarrier = 1; 1410} 1411 1412} // End isTerminator = 1, isBranch = 1 1413 1414let usesCustomInserter = 1 in { 1415 1416let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in { 1417 1418def MASK_WRITE : InstR600 < 1419 (outs), 1420 (ins R600_Reg32:$src), 1421 "MASK_WRITE $src", 1422 [], 1423 NullALU 1424>; 1425 1426} // End mayLoad = 0, mayStore = 0, hasSideEffects = 1 1427 1428 1429def TXD: InstR600 < 1430 (outs R600_Reg128:$dst), 1431 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, 1432 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget), 1433 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", [], 1434 NullALU > { 1435 let TEXInst = 1; 1436} 1437 1438def TXD_SHADOW: InstR600 < 1439 (outs R600_Reg128:$dst), 1440 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, 1441 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget), 1442 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", 1443 [], NullALU> { 1444 let TEXInst = 1; 1445} 1446} // End isPseudo = 1 1447} // End usesCustomInserter = 1 1448 1449 1450//===----------------------------------------------------------------------===// 1451// Constant Buffer Addressing Support 1452//===----------------------------------------------------------------------===// 1453 1454let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "R600" in { 1455def CONST_COPY : Instruction { 1456 let OutOperandList = (outs R600_Reg32:$dst); 1457 let InOperandList = (ins i32imm:$src); 1458 let Pattern = 1459 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))]; 1460 let AsmString = "CONST_COPY"; 1461 let hasSideEffects = 0; 1462 let isAsCheapAsAMove = 1; 1463 let Itinerary = NullALU; 1464} 1465} // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" 1466 1467def TEX_VTX_CONSTBUF : 1468 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$buffer_id), "VTX_READ_eg $dst, $ptr", 1469 [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$buffer_id)))]>, 1470 VTX_WORD1_GPR, VTX_WORD0_eg { 1471 1472 let VC_INST = 0; 1473 let FETCH_TYPE = 2; 1474 let FETCH_WHOLE_QUAD = 0; 1475 let SRC_REL = 0; 1476 let SRC_SEL_X = 0; 1477 let DST_REL = 0; 1478 let USE_CONST_FIELDS = 0; 1479 let NUM_FORMAT_ALL = 2; 1480 let FORMAT_COMP_ALL = 1; 1481 let SRF_MODE_ALL = 1; 1482 let MEGA_FETCH_COUNT = 16; 1483 let DST_SEL_X = 0; 1484 let DST_SEL_Y = 1; 1485 let DST_SEL_Z = 2; 1486 let DST_SEL_W = 3; 1487 let DATA_FORMAT = 35; 1488 1489 let Inst{31-0} = Word0; 1490 let Inst{63-32} = Word1; 1491 1492// LLVM can only encode 64-bit instructions, so these fields are manually 1493// encoded in R600CodeEmitter 1494// 1495// bits<16> OFFSET; 1496// bits<2> ENDIAN_SWAP = 0; 1497// bits<1> CONST_BUF_NO_STRIDE = 0; 1498// bits<1> MEGA_FETCH = 0; 1499// bits<1> ALT_CONST = 0; 1500// bits<2> BUFFER_INDEX_MODE = 0; 1501 1502 1503 1504// VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 1505// is done in R600CodeEmitter 1506// 1507// Inst{79-64} = OFFSET; 1508// Inst{81-80} = ENDIAN_SWAP; 1509// Inst{82} = CONST_BUF_NO_STRIDE; 1510// Inst{83} = MEGA_FETCH; 1511// Inst{84} = ALT_CONST; 1512// Inst{86-85} = BUFFER_INDEX_MODE; 1513// Inst{95-86} = 0; Reserved 1514 1515// VTX_WORD3 (Padding) 1516// 1517// Inst{127-96} = 0; 1518 let VTXInst = 1; 1519} 1520 1521def TEX_VTX_TEXBUF: 1522 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$buffer_id), "TEX_VTX_EXPLICIT_READ $dst, $ptr">, 1523VTX_WORD1_GPR, VTX_WORD0_eg { 1524 1525let VC_INST = 0; 1526let FETCH_TYPE = 2; 1527let FETCH_WHOLE_QUAD = 0; 1528let SRC_REL = 0; 1529let SRC_SEL_X = 0; 1530let DST_REL = 0; 1531let USE_CONST_FIELDS = 1; 1532let NUM_FORMAT_ALL = 0; 1533let FORMAT_COMP_ALL = 0; 1534let SRF_MODE_ALL = 1; 1535let MEGA_FETCH_COUNT = 16; 1536let DST_SEL_X = 0; 1537let DST_SEL_Y = 1; 1538let DST_SEL_Z = 2; 1539let DST_SEL_W = 3; 1540let DATA_FORMAT = 0; 1541 1542let Inst{31-0} = Word0; 1543let Inst{63-32} = Word1; 1544 1545// LLVM can only encode 64-bit instructions, so these fields are manually 1546// encoded in R600CodeEmitter 1547// 1548// bits<16> OFFSET; 1549// bits<2> ENDIAN_SWAP = 0; 1550// bits<1> CONST_BUF_NO_STRIDE = 0; 1551// bits<1> MEGA_FETCH = 0; 1552// bits<1> ALT_CONST = 0; 1553// bits<2> BUFFER_INDEX_MODE = 0; 1554 1555 1556 1557// VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 1558// is done in R600CodeEmitter 1559// 1560// Inst{79-64} = OFFSET; 1561// Inst{81-80} = ENDIAN_SWAP; 1562// Inst{82} = CONST_BUF_NO_STRIDE; 1563// Inst{83} = MEGA_FETCH; 1564// Inst{84} = ALT_CONST; 1565// Inst{86-85} = BUFFER_INDEX_MODE; 1566// Inst{95-86} = 0; Reserved 1567 1568// VTX_WORD3 (Padding) 1569// 1570// Inst{127-96} = 0; 1571 let VTXInst = 1; 1572} 1573 1574//===---------------------------------------------------------------------===// 1575// Flow and Program control Instructions 1576//===---------------------------------------------------------------------===// 1577 1578multiclass BranchConditional<SDNode Op, RegisterClass rci, RegisterClass rcf> { 1579 def _i32 : ILFormat<(outs), 1580 (ins brtarget:$target, rci:$src0), 1581 "; i32 Pseudo branch instruction", 1582 [(Op bb:$target, (i32 rci:$src0))]>; 1583 def _f32 : ILFormat<(outs), 1584 (ins brtarget:$target, rcf:$src0), 1585 "; f32 Pseudo branch instruction", 1586 [(Op bb:$target, (f32 rcf:$src0))]>; 1587} 1588 1589// Only scalar types should generate flow control 1590multiclass BranchInstr<string name> { 1591 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src), 1592 !strconcat(name, " $src"), []>; 1593 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src), 1594 !strconcat(name, " $src"), []>; 1595} 1596// Only scalar types should generate flow control 1597multiclass BranchInstr2<string name> { 1598 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1), 1599 !strconcat(name, " $src0, $src1"), []>; 1600 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1), 1601 !strconcat(name, " $src0, $src1"), []>; 1602} 1603 1604//===---------------------------------------------------------------------===// 1605// Custom Inserter for Branches and returns, this eventually will be a 1606// separate pass 1607//===---------------------------------------------------------------------===// 1608let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1, 1609 Namespace = "R600" in { 1610 def BRANCH : ILFormat<(outs), (ins brtarget:$target), 1611 "; Pseudo unconditional branch instruction", 1612 [(br bb:$target)]>; 1613 defm BRANCH_COND : BranchConditional<IL_brcond, R600_Reg32, R600_Reg32>; 1614} 1615 1616//===----------------------------------------------------------------------===// 1617// Branch Instructions 1618//===----------------------------------------------------------------------===// 1619 1620def IF_PREDICATE_SET : ILFormat<(outs), (ins R600_Reg32:$src), 1621 "IF_PREDICATE_SET $src", []>; 1622 1623let isTerminator=1 in { 1624 def BREAK : ILFormat< (outs), (ins), 1625 "BREAK", []>; 1626 def CONTINUE : ILFormat< (outs), (ins), 1627 "CONTINUE", []>; 1628 def DEFAULT : ILFormat< (outs), (ins), 1629 "DEFAULT", []>; 1630 def ELSE : ILFormat< (outs), (ins), 1631 "ELSE", []>; 1632 def ENDSWITCH : ILFormat< (outs), (ins), 1633 "ENDSWITCH", []>; 1634 def ENDMAIN : ILFormat< (outs), (ins), 1635 "ENDMAIN", []>; 1636 def END : ILFormat< (outs), (ins), 1637 "END", []>; 1638 def ENDFUNC : ILFormat< (outs), (ins), 1639 "ENDFUNC", []>; 1640 def ENDIF : ILFormat< (outs), (ins), 1641 "ENDIF", []>; 1642 def WHILELOOP : ILFormat< (outs), (ins), 1643 "WHILE", []>; 1644 def ENDLOOP : ILFormat< (outs), (ins), 1645 "ENDLOOP", []>; 1646 def FUNC : ILFormat< (outs), (ins), 1647 "FUNC", []>; 1648 def RETDYN : ILFormat< (outs), (ins), 1649 "RET_DYN", []>; 1650 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1651 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">; 1652 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1653 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">; 1654 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1655 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">; 1656 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1657 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">; 1658 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1659 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">; 1660 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1661 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">; 1662 defm IFC : BranchInstr2<"IFC">; 1663 defm BREAKC : BranchInstr2<"BREAKC">; 1664 defm CONTINUEC : BranchInstr2<"CONTINUEC">; 1665} 1666 1667//===----------------------------------------------------------------------===// 1668// Indirect addressing pseudo instructions 1669//===----------------------------------------------------------------------===// 1670 1671let isPseudo = 1 in { 1672 1673class ExtractVertical <RegisterClass vec_rc> : InstR600 < 1674 (outs R600_Reg32:$dst), 1675 (ins vec_rc:$vec, R600_Reg32:$index), "", 1676 [], 1677 AnyALU 1678>; 1679 1680let Constraints = "$dst = $vec" in { 1681 1682class InsertVertical <RegisterClass vec_rc> : InstR600 < 1683 (outs vec_rc:$dst), 1684 (ins vec_rc:$vec, R600_Reg32:$value, R600_Reg32:$index), "", 1685 [], 1686 AnyALU 1687>; 1688 1689} // End Constraints = "$dst = $vec" 1690 1691} // End isPseudo = 1 1692 1693def R600_EXTRACT_ELT_V2 : ExtractVertical <R600_Reg64Vertical>; 1694def R600_EXTRACT_ELT_V4 : ExtractVertical <R600_Reg128Vertical>; 1695 1696def R600_INSERT_ELT_V2 : InsertVertical <R600_Reg64Vertical>; 1697def R600_INSERT_ELT_V4 : InsertVertical <R600_Reg128Vertical>; 1698 1699class ExtractVerticalPat <Instruction inst, ValueType vec_ty, 1700 ValueType scalar_ty> : R600Pat < 1701 (scalar_ty (extractelt vec_ty:$vec, i32:$index)), 1702 (inst $vec, $index) 1703>; 1704 1705def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2i32, i32>; 1706def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2f32, f32>; 1707def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4i32, i32>; 1708def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4f32, f32>; 1709 1710class InsertVerticalPat <Instruction inst, ValueType vec_ty, 1711 ValueType scalar_ty> : R600Pat < 1712 (vec_ty (insertelt vec_ty:$vec, scalar_ty:$value, i32:$index)), 1713 (inst $vec, $value, $index) 1714>; 1715 1716def : InsertVerticalPat <R600_INSERT_ELT_V2, v2i32, i32>; 1717def : InsertVerticalPat <R600_INSERT_ELT_V2, v2f32, f32>; 1718def : InsertVerticalPat <R600_INSERT_ELT_V4, v4i32, i32>; 1719def : InsertVerticalPat <R600_INSERT_ELT_V4, v4f32, f32>; 1720 1721//===----------------------------------------------------------------------===// 1722// ISel Patterns 1723//===----------------------------------------------------------------------===// 1724 1725let SubtargetPredicate = isR600toCayman in { 1726 1727// CND*_INT Patterns for f32 True / False values 1728 1729class CND_INT_f32 <InstR600 cnd, CondCode cc> : R600Pat < 1730 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc), 1731 (cnd $src0, $src1, $src2) 1732>; 1733 1734def : CND_INT_f32 <CNDE_INT, SETEQ>; 1735def : CND_INT_f32 <CNDGT_INT, SETGT>; 1736def : CND_INT_f32 <CNDGE_INT, SETGE>; 1737 1738//CNDGE_INT extra pattern 1739def : R600Pat < 1740 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_SGT), 1741 (CNDGE_INT $src0, $src1, $src2) 1742>; 1743 1744// KIL Patterns 1745def KIL : R600Pat < 1746 (int_r600_kill f32:$src0), 1747 (MASK_WRITE (KILLGT (f32 ZERO), $src0)) 1748>; 1749 1750def : Extract_Element <f32, v4f32, 0, sub0>; 1751def : Extract_Element <f32, v4f32, 1, sub1>; 1752def : Extract_Element <f32, v4f32, 2, sub2>; 1753def : Extract_Element <f32, v4f32, 3, sub3>; 1754 1755def : Insert_Element <f32, v4f32, 0, sub0>; 1756def : Insert_Element <f32, v4f32, 1, sub1>; 1757def : Insert_Element <f32, v4f32, 2, sub2>; 1758def : Insert_Element <f32, v4f32, 3, sub3>; 1759 1760def : Extract_Element <i32, v4i32, 0, sub0>; 1761def : Extract_Element <i32, v4i32, 1, sub1>; 1762def : Extract_Element <i32, v4i32, 2, sub2>; 1763def : Extract_Element <i32, v4i32, 3, sub3>; 1764 1765def : Insert_Element <i32, v4i32, 0, sub0>; 1766def : Insert_Element <i32, v4i32, 1, sub1>; 1767def : Insert_Element <i32, v4i32, 2, sub2>; 1768def : Insert_Element <i32, v4i32, 3, sub3>; 1769 1770def : Extract_Element <f32, v2f32, 0, sub0>; 1771def : Extract_Element <f32, v2f32, 1, sub1>; 1772 1773def : Insert_Element <f32, v2f32, 0, sub0>; 1774def : Insert_Element <f32, v2f32, 1, sub1>; 1775 1776def : Extract_Element <i32, v2i32, 0, sub0>; 1777def : Extract_Element <i32, v2i32, 1, sub1>; 1778 1779def : Insert_Element <i32, v2i32, 0, sub0>; 1780def : Insert_Element <i32, v2i32, 1, sub1>; 1781 1782// bitconvert patterns 1783 1784def : BitConvert <i32, f32, R600_Reg32>; 1785def : BitConvert <f32, i32, R600_Reg32>; 1786def : BitConvert <v2f32, v2i32, R600_Reg64>; 1787def : BitConvert <v2i32, v2f32, R600_Reg64>; 1788def : BitConvert <v4f32, v4i32, R600_Reg128>; 1789def : BitConvert <v4i32, v4f32, R600_Reg128>; 1790 1791// DWORDADDR pattern 1792def : DwordAddrPat <i32, R600_Reg32>; 1793 1794} // End SubtargetPredicate = isR600toCayman 1795 1796def getLDSNoRetOp : InstrMapping { 1797 let FilterClass = "R600_LDS_1A1D"; 1798 let RowFields = ["BaseOp"]; 1799 let ColFields = ["DisableEncoding"]; 1800 let KeyCol = ["$dst"]; 1801 let ValueCols = [[""""]]; 1802} 1803