1//===-- MIMGInstructions.td - MIMG Instruction Definitions ----------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// MIMG-specific encoding families to distinguish between semantically 10// equivalent machine instructions with different encoding. 11// 12// - MIMGEncGfx6: encoding introduced with gfx6 (obsoleted for atomics in gfx8) 13// - MIMGEncGfx8: encoding introduced with gfx8 for atomics 14// - MIMGEncGfx90a: encoding for gfx90a for atomics 15// - MIMGEncGfx10Default: gfx10 default (non-NSA) encoding 16// - MIMGEncGfx10NSA: gfx10 NSA encoding 17// - MIMGEncGfx11Default: gfx11 default (non-NSA) encoding 18// - MIMGEncGfx11NSA: gfx11 NSA encoding 19class MIMGEncoding; 20 21def MIMGEncGfx6 : MIMGEncoding; 22def MIMGEncGfx8 : MIMGEncoding; 23def MIMGEncGfx90a : MIMGEncoding; 24def MIMGEncGfx10Default : MIMGEncoding; 25def MIMGEncGfx10NSA : MIMGEncoding; 26def MIMGEncGfx11Default : MIMGEncoding; 27def MIMGEncGfx11NSA : MIMGEncoding; 28 29def MIMGEncoding : GenericEnum { 30 let FilterClass = "MIMGEncoding"; 31} 32 33// Represent an ISA-level opcode, independent of the encoding and the 34// vdata/vaddr size. 35class MIMGBaseOpcode : PredicateControl { 36 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME); 37 bit Store = 0; 38 bit Atomic = 0; 39 bit AtomicX2 = 0; // (f)cmpswap 40 bit Sampler = 0; 41 bit Gather4 = 0; 42 bits<8> NumExtraArgs = 0; 43 bit Gradients = 0; 44 bit G16 = 0; 45 bit Coordinates = 1; 46 bit LodOrClampOrMip = 0; 47 bit HasD16 = 0; 48 bit IsAtomicRet = 0; 49 bit MSAA = 0; 50 bit BVH = 0; 51} 52 53def MIMGBaseOpcode : GenericEnum { 54 let FilterClass = "MIMGBaseOpcode"; 55} 56 57def MIMGBaseOpcodesTable : GenericTable { 58 let FilterClass = "MIMGBaseOpcode"; 59 let CppTypeName = "MIMGBaseOpcodeInfo"; 60 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler", 61 "Gather4", "NumExtraArgs", "Gradients", "G16", "Coordinates", 62 "LodOrClampOrMip", "HasD16", "MSAA", "BVH"]; 63 string TypeOf_BaseOpcode = "MIMGBaseOpcode"; 64 65 let PrimaryKey = ["BaseOpcode"]; 66 let PrimaryKeyName = "getMIMGBaseOpcodeInfo"; 67} 68 69def MIMGDim : GenericEnum { 70 let FilterClass = "AMDGPUDimProps"; 71} 72 73def MIMGDimInfoTable : GenericTable { 74 let FilterClass = "AMDGPUDimProps"; 75 let CppTypeName = "MIMGDimInfo"; 76 let Fields = ["Dim", "NumCoords", "NumGradients", "MSAA", "DA", "Encoding", "AsmSuffix"]; 77 string TypeOf_Dim = "MIMGDim"; 78 79 let PrimaryKey = ["Dim"]; 80 let PrimaryKeyName = "getMIMGDimInfo"; 81} 82 83def getMIMGDimInfoByEncoding : SearchIndex { 84 let Table = MIMGDimInfoTable; 85 let Key = ["Encoding"]; 86} 87 88def getMIMGDimInfoByAsmSuffix : SearchIndex { 89 let Table = MIMGDimInfoTable; 90 let Key = ["AsmSuffix"]; 91} 92 93def MIMG { 94 int NOP = -1; 95} 96 97class mimgopc <int gfx11, int gfx10m, int vi = gfx10m, int si = gfx10m> { 98 field bits<8> GFX11 = gfx11; 99 field bits<8> GFX10M = gfx10m; // GFX10minus for all but atomics 100 field bits<8> VI = vi; // VI is only used for atomic instructions 101 field bits<8> SI = si; // SI is only used for atomic instructions 102 bit HAS_GFX11 = !ne(gfx11, MIMG.NOP); 103 bit HAS_GFX10M = !ne(gfx10m, MIMG.NOP); 104 bit HAS_VI = !ne(vi, MIMG.NOP); 105 bit HAS_SI = !ne(si, MIMG.NOP); 106} 107 108class MIMGLZMapping<MIMGBaseOpcode l, MIMGBaseOpcode lz> { 109 MIMGBaseOpcode L = l; 110 MIMGBaseOpcode LZ = lz; 111} 112 113def MIMGLZMappingTable : GenericTable { 114 let FilterClass = "MIMGLZMapping"; 115 let CppTypeName = "MIMGLZMappingInfo"; 116 let Fields = ["L", "LZ"]; 117 string TypeOf_L = "MIMGBaseOpcode"; 118 string TypeOf_LZ = "MIMGBaseOpcode"; 119 120 let PrimaryKey = ["L"]; 121 let PrimaryKeyName = "getMIMGLZMappingInfo"; 122} 123 124class MIMGMIPMapping<MIMGBaseOpcode mip, MIMGBaseOpcode nonmip> { 125 MIMGBaseOpcode MIP = mip; 126 MIMGBaseOpcode NONMIP = nonmip; 127} 128 129def MIMGMIPMappingTable : GenericTable { 130 let FilterClass = "MIMGMIPMapping"; 131 let CppTypeName = "MIMGMIPMappingInfo"; 132 let Fields = ["MIP", "NONMIP"]; 133 string TypeOf_MIP = "MIMGBaseOpcode"; 134 string TypeOf_NONMIP = "MIMGBaseOpcode"; 135 136 let PrimaryKey = ["MIP"]; 137 let PrimaryKeyName = "getMIMGMIPMappingInfo"; 138} 139 140class MIMGBiasMapping<MIMGBaseOpcode bias, MIMGBaseOpcode nobias> { 141 MIMGBaseOpcode Bias = bias; 142 MIMGBaseOpcode NoBias = nobias; 143} 144 145def MIMGBiasMappingTable : GenericTable { 146 let FilterClass = "MIMGBiasMapping"; 147 let CppTypeName = "MIMGBiasMappingInfo"; 148 let Fields = ["Bias", "NoBias"]; 149 string TypeOf_Bias = "MIMGBaseOpcode"; 150 string TypeOf_NoBias = "MIMGBaseOpcode"; 151 152 let PrimaryKey = ["Bias"]; 153 let PrimaryKeyName = "getMIMGBiasMappingInfo"; 154} 155 156class MIMGOffsetMapping<MIMGBaseOpcode offset, MIMGBaseOpcode nooffset> { 157 MIMGBaseOpcode Offset = offset; 158 MIMGBaseOpcode NoOffset = nooffset; 159} 160 161def MIMGOffsetMappingTable : GenericTable { 162 let FilterClass = "MIMGOffsetMapping"; 163 let CppTypeName = "MIMGOffsetMappingInfo"; 164 let Fields = ["Offset", "NoOffset"]; 165 string TypeOf_Offset = "MIMGBaseOpcode"; 166 string TypeOf_NoOffset = "MIMGBaseOpcode"; 167 168 let PrimaryKey = ["Offset"]; 169 let PrimaryKeyName = "getMIMGOffsetMappingInfo"; 170} 171 172class MIMGG16Mapping<MIMGBaseOpcode g, MIMGBaseOpcode g16> { 173 MIMGBaseOpcode G = g; 174 MIMGBaseOpcode G16 = g16; 175} 176 177def MIMGG16MappingTable : GenericTable { 178 let FilterClass = "MIMGG16Mapping"; 179 let CppTypeName = "MIMGG16MappingInfo"; 180 let Fields = ["G", "G16"]; 181 string TypeOf_G = "MIMGBaseOpcode"; 182 string TypeOf_G16 = "MIMGBaseOpcode"; 183 184 let PrimaryKey = ["G"]; 185 let PrimaryKeyName = "getMIMGG16MappingInfo"; 186} 187 188class MIMG_Base <dag outs, string dns = ""> 189 : InstSI <outs, (ins), "", []> { 190 191 let VM_CNT = 1; 192 let EXP_CNT = 1; 193 let MIMG = 1; 194 let Uses = [EXEC]; 195 let mayLoad = 1; 196 let mayStore = 0; 197 let SchedRW = [WriteVMEM]; 198 let UseNamedOperandTable = 1; 199 let hasSideEffects = 0; // XXX ???? 200 201 let DecoderNamespace = dns; 202 let isAsmParserOnly = !eq(dns, ""); 203} 204 205class MIMG <dag outs, string dns = ""> 206 : MIMG_Base <outs, dns> { 207 208 let hasPostISelHook = 1; 209 let AsmMatchConverter = "cvtMIMG"; 210 211 Instruction Opcode = !cast<Instruction>(NAME); 212 MIMGBaseOpcode BaseOpcode; 213 MIMGEncoding MIMGEncoding; 214 bits<8> VDataDwords; 215 bits<8> VAddrDwords; 216 217 // If NSA is used this counts number of operands VAddrDwords is split into. 218 bits<8> VAddrOperands; 219} 220 221def MIMGInfoTable : GenericTable { 222 let FilterClass = "MIMG"; 223 let CppTypeName = "MIMGInfo"; 224 let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", 225 "VAddrDwords", "VAddrOperands"]; 226 string TypeOf_BaseOpcode = "MIMGBaseOpcode"; 227 string TypeOf_MIMGEncoding = "MIMGEncoding"; 228 229 let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"]; 230 let PrimaryKeyName = "getMIMGOpcodeHelper"; 231} 232 233def getMIMGInfo : SearchIndex { 234 let Table = MIMGInfoTable; 235 let Key = ["Opcode"]; 236} 237 238// This class used to use !foldl to memoize the AddrAsmNames list. 239// It turned out that that was much slower than using !filter. 240class MIMGNSAHelper<int num_addrs, 241 list<RegisterClass> addr_types=!listsplat(VGPR_32, num_addrs)> { 242 list<string> AddrAsmNames = 243 !foreach(i, !filter(i, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11], 244 !lt(i, num_addrs)), "vaddr" # i); 245 dag AddrIns = !dag(ins, addr_types, AddrAsmNames); 246 string AddrAsm = "[$" # !interleave(AddrAsmNames, ", $") # "]"; 247 248 int NSA = !if(!le(num_addrs, 1), ?, 249 !if(!le(num_addrs, 5), 1, 250 !if(!le(num_addrs, 9), 2, 251 !if(!le(num_addrs, 13), 3, ?)))); 252} 253 254// Base class of all pre-gfx10 MIMG instructions. 255class MIMG_gfx6789<bits<8> op, dag outs, string dns = ""> 256 : MIMG<outs, dns>, MIMGe_gfx6789<op> { 257 let SubtargetPredicate = isGFX6GFX7GFX8GFX9NotGFX90A; 258 let AssemblerPredicate = isGFX6GFX7GFX8GFX9NotGFX90A; 259 260 let MIMGEncoding = MIMGEncGfx6; 261 let VAddrOperands = 1; 262 263 let d16 = !if(BaseOpcode.HasD16, ?, 0); 264} 265 266class MIMG_gfx90a<bits<8> op, dag outs, string dns = ""> 267 : MIMG<outs, dns>, MIMGe_gfx90a<op> { 268 let SubtargetPredicate = isGFX90APlus; 269 let AssemblerPredicate = isGFX90APlus; 270 271 let MIMGEncoding = MIMGEncGfx90a; 272 let VAddrOperands = 1; 273 274 let d16 = !if(BaseOpcode.HasD16, ?, 0); 275} 276 277// Base class of all non-NSA gfx10 MIMG instructions. 278class MIMG_gfx10<int op, dag outs, string dns = ""> 279 : MIMG<outs, dns>, MIMGe_gfx10<op> { 280 let SubtargetPredicate = isGFX10Only; 281 let AssemblerPredicate = isGFX10Only; 282 283 let MIMGEncoding = MIMGEncGfx10Default; 284 let VAddrOperands = 1; 285 286 let d16 = !if(BaseOpcode.HasD16, ?, 0); 287 let nsa = 0; 288} 289 290// Base class for all NSA MIMG instructions. 291// Note that 1-dword addresses always use non-NSA variants. 292class MIMG_nsa_gfx10<int op, dag outs, int num_addrs, string dns=""> 293 : MIMG<outs, dns>, MIMGe_gfx10<op> { 294 let SubtargetPredicate = isGFX10Only; 295 let AssemblerPredicate = isGFX10Only; 296 297 let MIMGEncoding = MIMGEncGfx10NSA; 298 let VAddrOperands = num_addrs; 299 300 MIMGNSAHelper nsah = MIMGNSAHelper<num_addrs>; 301 dag AddrIns = nsah.AddrIns; 302 string AddrAsm = nsah.AddrAsm; 303 304 let d16 = !if(BaseOpcode.HasD16, ?, 0); 305 let nsa = nsah.NSA; 306} 307 308// Base class of all non-NSA gfx11 MIMG instructions. 309class MIMG_gfx11<int op, dag outs, string dns = ""> 310 : MIMG<outs, dns>, MIMGe_gfx11<op> { 311 let SubtargetPredicate = isGFX11Plus; 312 let AssemblerPredicate = isGFX11Plus; 313 314 let MIMGEncoding = MIMGEncGfx11Default; 315 let VAddrOperands = 1; 316 317 let d16 = !if(BaseOpcode.HasD16, ?, 0); 318 let nsa = 0; 319} 320 321// Base class for all NSA MIMG instructions. 322// Note that 1-dword addresses always use non-NSA variants. 323class MIMG_nsa_gfx11<int op, dag outs, int num_addrs, string dns="", 324 list<RegisterClass> addr_types=[]> 325 : MIMG<outs, dns>, MIMGe_gfx11<op> { 326 let SubtargetPredicate = isGFX11Plus; 327 let AssemblerPredicate = isGFX11Plus; 328 329 let MIMGEncoding = MIMGEncGfx11NSA; 330 let VAddrOperands = num_addrs; 331 332 MIMGNSAHelper nsah = !if(!empty(addr_types), 333 MIMGNSAHelper<num_addrs>, 334 MIMGNSAHelper<num_addrs, addr_types>); 335 dag AddrIns = nsah.AddrIns; 336 string AddrAsm = nsah.AddrAsm; 337 338 let d16 = !if(BaseOpcode.HasD16, ?, 0); 339 let nsa = nsah.NSA; 340} 341 342class MIMG_NoSampler_Helper <mimgopc op, string asm, 343 RegisterClass dst_rc, 344 RegisterClass addr_rc, 345 string dns=""> 346 : MIMG_gfx6789 <op.GFX10M, (outs dst_rc:$vdata), dns> { 347 let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc, 348 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 349 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 350 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 351 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da" 352 #!if(BaseOpcode.HasD16, "$d16", ""); 353} 354 355class MIMG_NoSampler_Helper_gfx90a <mimgopc op, string asm, 356 RegisterClass dst_rc, 357 RegisterClass addr_rc, 358 string dns=""> 359 : MIMG_gfx90a <op.GFX10M, (outs getLdStRegisterOperand<dst_rc>.ret:$vdata), dns> { 360 let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc, 361 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 362 R128A16:$r128, LWE:$lwe, DA:$da), 363 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 364 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da" 365 #!if(BaseOpcode.HasD16, "$d16", ""); 366} 367 368class MIMG_NoSampler_gfx10<mimgopc op, string opcode, 369 RegisterClass DataRC, RegisterClass AddrRC, 370 string dns=""> 371 : MIMG_gfx10<op.GFX10M, (outs DataRC:$vdata), dns> { 372 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask, 373 Dim:$dim, UNorm:$unorm, CPol:$cpol, 374 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 375 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 376 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 377 #!if(BaseOpcode.HasD16, "$d16", ""); 378} 379 380class MIMG_NoSampler_nsa_gfx10<mimgopc op, string opcode, 381 RegisterClass DataRC, int num_addrs, 382 string dns=""> 383 : MIMG_nsa_gfx10<op.GFX10M, (outs DataRC:$vdata), num_addrs, dns> { 384 let InOperandList = !con(AddrIns, 385 (ins SReg_256:$srsrc, DMask:$dmask, 386 Dim:$dim, UNorm:$unorm, CPol:$cpol, 387 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 388 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 389 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 390 #!if(BaseOpcode.HasD16, "$d16", ""); 391} 392 393class MIMG_NoSampler_gfx11<mimgopc op, string opcode, 394 RegisterClass DataRC, RegisterClass AddrRC, 395 string dns=""> 396 : MIMG_gfx11<op.GFX11, (outs DataRC:$vdata), dns> { 397 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask, 398 Dim:$dim, UNorm:$unorm, CPol:$cpol, 399 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 400 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 401 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 402 #!if(BaseOpcode.HasD16, "$d16", ""); 403} 404 405class MIMG_NoSampler_nsa_gfx11<mimgopc op, string opcode, 406 RegisterClass DataRC, int num_addrs, 407 string dns=""> 408 : MIMG_nsa_gfx11<op.GFX11, (outs DataRC:$vdata), num_addrs, dns> { 409 let InOperandList = !con(AddrIns, 410 (ins SReg_256:$srsrc, DMask:$dmask, 411 Dim:$dim, UNorm:$unorm, CPol:$cpol, 412 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 413 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 414 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 415 #!if(BaseOpcode.HasD16, "$d16", ""); 416} 417 418multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm, 419 RegisterClass dst_rc, 420 bit enableDisasm, 421 bit ExtendedImageInst = 1> { 422 let ssamp = 0 in { 423 let VAddrDwords = 1 in { 424 if op.HAS_GFX10M then { 425 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32, 426 !if(enableDisasm, "AMDGPU", "")>; 427 if !not(ExtendedImageInst) then 428 def _V1_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPR_32, 429 !if(enableDisasm, "GFX90A", "")>; 430 def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPR_32, 431 !if(enableDisasm, "AMDGPU", "")>; 432 } 433 if op.HAS_GFX11 then { 434 def _V1_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VGPR_32, 435 !if(enableDisasm, "AMDGPU", "")>; 436 } 437 } 438 439 let VAddrDwords = 2 in { 440 if op.HAS_GFX10M then { 441 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>; 442 if !not(ExtendedImageInst) then 443 def _V2_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_64>; 444 def _V2_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_64>; 445 def _V2_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 2>; 446 } 447 if op.HAS_GFX11 then { 448 def _V2_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VReg_64>; 449 def _V2_nsa_gfx11 : MIMG_NoSampler_nsa_gfx11<op, asm, dst_rc, 2>; 450 } 451 } 452 453 let VAddrDwords = 3 in { 454 if op.HAS_GFX10M then { 455 def _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96>; 456 if !not(ExtendedImageInst) then 457 def _V3_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_96>; 458 def _V3_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_96>; 459 def _V3_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 3>; 460 } 461 if op.HAS_GFX11 then { 462 def _V3_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VReg_96>; 463 def _V3_nsa_gfx11 : MIMG_NoSampler_nsa_gfx11<op, asm, dst_rc, 3>; 464 } 465 } 466 467 let VAddrDwords = 4 in { 468 if op.HAS_GFX10M then { 469 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>; 470 if !not(ExtendedImageInst) then 471 def _V4_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_128>; 472 def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_128>; 473 def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 4, 474 !if(enableDisasm, "AMDGPU", "")>; 475 } 476 if op.HAS_GFX11 then { 477 def _V4_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VReg_128>; 478 def _V4_nsa_gfx11 : MIMG_NoSampler_nsa_gfx11<op, asm, dst_rc, 4, 479 !if(enableDisasm, "AMDGPU", "")>; 480 } 481 } 482 } 483} 484 485multiclass MIMG_NoSampler <mimgopc op, string asm, bit has_d16, bit mip = 0, 486 bit isResInfo = 0, 487 bit msaa = 0> { 488 def "" : MIMGBaseOpcode { 489 let Coordinates = !not(isResInfo); 490 let LodOrClampOrMip = mip; 491 let HasD16 = has_d16; 492 let MSAA = msaa; 493 } 494 495 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), 496 mayLoad = !not(isResInfo) in { 497 let VDataDwords = 1 in 498 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1, msaa>; 499 let VDataDwords = 2 in 500 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 0, msaa>; 501 let VDataDwords = 3 in 502 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 0, msaa>; 503 let VDataDwords = 4 in 504 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 0, msaa>; 505 let VDataDwords = 5 in 506 defm _V5 : MIMG_NoSampler_Src_Helper <op, asm, VReg_160, 0, msaa>; 507 } 508} 509 510class MIMG_Store_Helper <mimgopc op, string asm, 511 RegisterClass data_rc, 512 RegisterClass addr_rc, 513 string dns = ""> 514 : MIMG_gfx6789<op.GFX10M, (outs), dns> { 515 let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 516 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 517 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 518 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 519 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da" 520 #!if(BaseOpcode.HasD16, "$d16", ""); 521} 522 523class MIMG_Store_Helper_gfx90a <mimgopc op, string asm, 524 RegisterClass data_rc, 525 RegisterClass addr_rc, 526 string dns = ""> 527 : MIMG_gfx90a<op.GFX10M, (outs), dns> { 528 let InOperandList = !con((ins getLdStRegisterOperand<data_rc>.ret:$vdata, 529 addr_rc:$vaddr, SReg_256:$srsrc, 530 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 531 R128A16:$r128, LWE:$lwe, DA:$da), 532 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 533 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da" 534 #!if(BaseOpcode.HasD16, "$d16", ""); 535} 536 537class MIMG_Store_gfx10<mimgopc op, string opcode, 538 RegisterClass DataRC, RegisterClass AddrRC, 539 string dns=""> 540 : MIMG_gfx10<op.GFX10M, (outs), dns> { 541 let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc, 542 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol, 543 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 544 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 545 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 546 #!if(BaseOpcode.HasD16, "$d16", ""); 547} 548 549class MIMG_Store_nsa_gfx10<mimgopc op, string opcode, 550 RegisterClass DataRC, int num_addrs, 551 string dns=""> 552 : MIMG_nsa_gfx10<op.GFX10M, (outs), num_addrs, dns> { 553 let InOperandList = !con((ins DataRC:$vdata), 554 AddrIns, 555 (ins SReg_256:$srsrc, DMask:$dmask, 556 Dim:$dim, UNorm:$unorm, CPol:$cpol, 557 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 558 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 559 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 560 #!if(BaseOpcode.HasD16, "$d16", ""); 561} 562 563class MIMG_Store_gfx11<mimgopc op, string opcode, 564 RegisterClass DataRC, RegisterClass AddrRC, 565 string dns=""> 566 : MIMG_gfx11<op.GFX11, (outs), dns> { 567 let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc, 568 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol, 569 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 570 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 571 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 572 #!if(BaseOpcode.HasD16, "$d16", ""); 573} 574 575class MIMG_Store_nsa_gfx11<mimgopc op, string opcode, 576 RegisterClass DataRC, int num_addrs, 577 string dns=""> 578 : MIMG_nsa_gfx11<op.GFX11, (outs), num_addrs, dns> { 579 let InOperandList = !con((ins DataRC:$vdata), 580 AddrIns, 581 (ins SReg_256:$srsrc, DMask:$dmask, 582 Dim:$dim, UNorm:$unorm, CPol:$cpol, 583 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 584 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 585 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 586 #!if(BaseOpcode.HasD16, "$d16", ""); 587} 588 589multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm, 590 RegisterClass data_rc, 591 bit enableDisasm> { 592 let mayLoad = 0, mayStore = 1, hasSideEffects = 0, hasPostISelHook = 0, 593 DisableWQM = 1, ssamp = 0 in { 594 let VAddrDwords = 1 in { 595 if op.HAS_GFX10M then { 596 def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32, 597 !if(enableDisasm, "AMDGPU", "")>; 598 let hasPostISelHook = 1 in 599 def _V1_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VGPR_32, 600 !if(enableDisasm, "GFX90A", "")>; 601 def _V1_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VGPR_32, 602 !if(enableDisasm, "AMDGPU", "")>; 603 } 604 if op.HAS_GFX11 then { 605 def _V1_gfx11 : MIMG_Store_gfx11 <op, asm, data_rc, VGPR_32, 606 !if(enableDisasm, "AMDGPU", "")>; 607 } 608 } 609 let VAddrDwords = 2 in { 610 if op.HAS_GFX10M then { 611 def _V2 : MIMG_Store_Helper <op, asm, data_rc, VReg_64>; 612 def _V2_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_64>; 613 def _V2_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_64>; 614 def _V2_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 2>; 615 } 616 if op.HAS_GFX11 then { 617 def _V2_gfx11 : MIMG_Store_gfx11 <op, asm, data_rc, VReg_64>; 618 def _V2_nsa_gfx11 : MIMG_Store_nsa_gfx11 <op, asm, data_rc, 2>; 619 } 620 } 621 let VAddrDwords = 3 in { 622 if op.HAS_GFX10M then { 623 def _V3 : MIMG_Store_Helper <op, asm, data_rc, VReg_96>; 624 def _V3_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_96>; 625 def _V3_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_96>; 626 def _V3_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 3>; 627 } 628 if op.HAS_GFX11 then { 629 def _V3_gfx11 : MIMG_Store_gfx11 <op, asm, data_rc, VReg_96>; 630 def _V3_nsa_gfx11 : MIMG_Store_nsa_gfx11 <op, asm, data_rc, 3>; 631 } 632 } 633 let VAddrDwords = 4 in { 634 if op.HAS_GFX10M then { 635 def _V4 : MIMG_Store_Helper <op, asm, data_rc, VReg_128>; 636 def _V4_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_128>; 637 def _V4_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_128>; 638 def _V4_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 4, 639 !if(enableDisasm, "AMDGPU", "")>; 640 } 641 if op.HAS_GFX11 then { 642 def _V4_gfx11 : MIMG_Store_gfx11 <op, asm, data_rc, VReg_128>; 643 def _V4_nsa_gfx11 : MIMG_Store_nsa_gfx11 <op, asm, data_rc, 4, 644 !if(enableDisasm, "AMDGPU", "")>; 645 } 646 } 647 } 648} 649 650multiclass MIMG_Store <mimgopc op, string asm, bit has_d16, bit mip = 0> { 651 def "" : MIMGBaseOpcode { 652 let Store = 1; 653 let LodOrClampOrMip = mip; 654 let HasD16 = has_d16; 655 } 656 657 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in { 658 let VDataDwords = 1 in 659 defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>; 660 let VDataDwords = 2 in 661 defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 0>; 662 let VDataDwords = 3 in 663 defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 0>; 664 let VDataDwords = 4 in 665 defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 0>; 666 let VDataDwords = 5 in 667 defm _V5 : MIMG_Store_Addr_Helper <op, asm, VReg_160, 0>; 668 } 669} 670 671class MIMG_Atomic_gfx6789_base <bits<8> op, string asm, RegisterClass data_rc, 672 RegisterClass addr_rc, string dns=""> 673 : MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> { 674 let Constraints = "$vdst = $vdata"; 675 let AsmMatchConverter = "cvtMIMGAtomic"; 676 677 let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 678 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 679 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da); 680 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da"; 681} 682 683class MIMG_Atomic_gfx90a_base <bits<8> op, string asm, RegisterClass data_rc, 684 RegisterClass addr_rc, string dns=""> 685 : MIMG_gfx90a <op, (outs getLdStRegisterOperand<data_rc>.ret:$vdst), dns> { 686 let Constraints = "$vdst = $vdata"; 687 let AsmMatchConverter = "cvtMIMGAtomic"; 688 689 let InOperandList = (ins getLdStRegisterOperand<data_rc>.ret:$vdata, 690 addr_rc:$vaddr, SReg_256:$srsrc, 691 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 692 R128A16:$r128, LWE:$lwe, DA:$da); 693 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da"; 694} 695 696class MIMG_Atomic_si<mimgopc op, string asm, RegisterClass data_rc, 697 RegisterClass addr_rc, bit enableDasm = 0> 698 : MIMG_Atomic_gfx6789_base<op.SI, asm, data_rc, addr_rc, 699 !if(enableDasm, "GFX6GFX7", "")> { 700 let AssemblerPredicate = isGFX6GFX7; 701} 702 703class MIMG_Atomic_vi<mimgopc op, string asm, RegisterClass data_rc, 704 RegisterClass addr_rc, bit enableDasm = 0> 705 : MIMG_Atomic_gfx6789_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX8", "")> { 706 let AssemblerPredicate = isGFX8GFX9NotGFX90A; 707 let MIMGEncoding = MIMGEncGfx8; 708} 709 710class MIMG_Atomic_gfx90a<mimgopc op, string asm, RegisterClass data_rc, 711 RegisterClass addr_rc, bit enableDasm = 0> 712 : MIMG_Atomic_gfx90a_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX90A", "")> { 713 let AssemblerPredicate = isGFX90APlus; 714 let MIMGEncoding = MIMGEncGfx90a; 715} 716 717class MIMG_Atomic_gfx10<mimgopc op, string opcode, 718 RegisterClass DataRC, RegisterClass AddrRC, 719 bit enableDisasm = 0> 720 : MIMG_gfx10<!cast<int>(op.GFX10M), (outs DataRC:$vdst), 721 !if(enableDisasm, "AMDGPU", "")> { 722 let Constraints = "$vdst = $vdata"; 723 let AsmMatchConverter = "cvtMIMGAtomic"; 724 725 let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc, 726 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol, 727 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe); 728 let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"; 729} 730 731class MIMG_Atomic_nsa_gfx10<mimgopc op, string opcode, 732 RegisterClass DataRC, int num_addrs, 733 bit enableDisasm = 0> 734 : MIMG_nsa_gfx10<!cast<int>(op.GFX10M), (outs DataRC:$vdst), num_addrs, 735 !if(enableDisasm, "AMDGPU", "")> { 736 let Constraints = "$vdst = $vdata"; 737 let AsmMatchConverter = "cvtMIMGAtomic"; 738 739 let InOperandList = !con((ins DataRC:$vdata), 740 AddrIns, 741 (ins SReg_256:$srsrc, DMask:$dmask, 742 Dim:$dim, UNorm:$unorm, CPol:$cpol, 743 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe)); 744 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"; 745} 746 747class MIMG_Atomic_gfx11<mimgopc op, string opcode, 748 RegisterClass DataRC, RegisterClass AddrRC, 749 bit enableDisasm = 0> 750 : MIMG_gfx11<!cast<int>(op.GFX11), (outs DataRC:$vdst), 751 !if(enableDisasm, "AMDGPU", "")> { 752 let Constraints = "$vdst = $vdata"; 753 let AsmMatchConverter = "cvtMIMGAtomic"; 754 755 let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc, 756 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol, 757 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe); 758 let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"; 759} 760 761class MIMG_Atomic_nsa_gfx11<mimgopc op, string opcode, 762 RegisterClass DataRC, int num_addrs, 763 bit enableDisasm = 0> 764 : MIMG_nsa_gfx11<!cast<int>(op.GFX11), (outs DataRC:$vdst), num_addrs, 765 !if(enableDisasm, "AMDGPU", "")> { 766 let Constraints = "$vdst = $vdata"; 767 let AsmMatchConverter = "cvtMIMGAtomic"; 768 769 let InOperandList = !con((ins DataRC:$vdata), 770 AddrIns, 771 (ins SReg_256:$srsrc, DMask:$dmask, 772 Dim:$dim, UNorm:$unorm, CPol:$cpol, 773 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe)); 774 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"; 775} 776 777multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm, 778 RegisterClass data_rc, 779 bit enableDasm = 0, 780 bit isFP = 0> { 781 let hasSideEffects = 1, // FIXME: remove this 782 mayLoad = 1, mayStore = 1, hasPostISelHook = 0, DisableWQM = 1, 783 ssamp = 0, FPAtomic = isFP in { 784 let VAddrDwords = 1 in { 785 if op.HAS_SI then { 786 def _V1_si : MIMG_Atomic_si <op, asm, data_rc, VGPR_32, enableDasm>; 787 } 788 if op.HAS_VI then { 789 def _V1_vi : MIMG_Atomic_vi <op, asm, data_rc, VGPR_32, enableDasm>; 790 let hasPostISelHook = 1 in 791 def _V1_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VGPR_32, enableDasm>; 792 } 793 if op.HAS_GFX10M then { 794 def _V1_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VGPR_32, enableDasm>; 795 } 796 if op.HAS_GFX11 then { 797 def _V1_gfx11 : MIMG_Atomic_gfx11 <op, asm, data_rc, VGPR_32, enableDasm>; 798 } 799 } 800 let VAddrDwords = 2 in { 801 if op.HAS_SI then { 802 def _V2_si : MIMG_Atomic_si <op, asm, data_rc, VReg_64, 0>; 803 } 804 if op.HAS_VI then { 805 def _V2_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_64, 0>; 806 def _V2_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_64, 0>; 807 } 808 if op.HAS_GFX10M then { 809 def _V2_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_64, 0>; 810 def _V2_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 2, 0>; 811 } 812 if op.HAS_GFX11 then { 813 def _V2_gfx11 : MIMG_Atomic_gfx11 <op, asm, data_rc, VReg_64, 0>; 814 def _V2_nsa_gfx11 : MIMG_Atomic_nsa_gfx11 <op, asm, data_rc, 2, 0>; 815 } 816 } 817 let VAddrDwords = 3 in { 818 if op.HAS_SI then { 819 def _V3_si : MIMG_Atomic_si <op, asm, data_rc, VReg_96, 0>; 820 } 821 if op.HAS_VI then { 822 def _V3_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_96, 0>; 823 def _V3_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_96, 0>; 824 } 825 if op.HAS_GFX10M then { 826 def _V3_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_96, 0>; 827 def _V3_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 3, 0>; 828 } 829 if op.HAS_GFX11 then { 830 def _V3_gfx11 : MIMG_Atomic_gfx11 <op, asm, data_rc, VReg_96, 0>; 831 def _V3_nsa_gfx11 : MIMG_Atomic_nsa_gfx11 <op, asm, data_rc, 3, 0>; 832 } 833 } 834 let VAddrDwords = 4 in { 835 if op.HAS_SI then { 836 def _V4_si : MIMG_Atomic_si <op, asm, data_rc, VReg_128, 0>; 837 } 838 if op.HAS_VI then { 839 def _V4_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_128, 0>; 840 def _V4_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_128, 0>; 841 } 842 if op.HAS_GFX10M then { 843 def _V4_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_128, 0>; 844 def _V4_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 4, enableDasm>; 845 } 846 if op.HAS_GFX11 then { 847 def _V4_gfx11 : MIMG_Atomic_gfx11 <op, asm, data_rc, VReg_128, 0>; 848 def _V4_nsa_gfx11 : MIMG_Atomic_nsa_gfx11 <op, asm, data_rc, 4, enableDasm>; 849 } 850 } 851 } 852} 853 854multiclass MIMG_Atomic <mimgopc op, string asm, bit isCmpSwap = 0, bit isFP = 0> { // 64-bit atomics 855 let IsAtomicRet = 1 in { 856 def "" : MIMGBaseOpcode { 857 let Atomic = 1; 858 let AtomicX2 = isCmpSwap; 859 } 860 861 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in { 862 // _V* variants have different dst size, but the size is encoded implicitly, 863 // using dmask and tfe. Only 32-bit variant is registered with disassembler. 864 // Other variants are reconstructed by disassembler using dmask and tfe. 865 let VDataDwords = !if(isCmpSwap, 2, 1) in 866 defm _V1 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_64, VGPR_32), 1, isFP>; 867 let VDataDwords = !if(isCmpSwap, 4, 2) in 868 defm _V2 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_128, VReg_64), 0, isFP>; 869 } 870 } // End IsAtomicRet = 1 871} 872 873class MIMG_Sampler_Helper <mimgopc op, string asm, RegisterClass dst_rc, 874 RegisterClass src_rc, string dns=""> 875 : MIMG_gfx6789 <op.GFX10M, (outs dst_rc:$vdata), dns> { 876 let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, 877 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 878 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 879 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 880 let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$cpol$r128$tfe$lwe$da" 881 #!if(BaseOpcode.HasD16, "$d16", ""); 882} 883 884class MIMG_Sampler_gfx90a<mimgopc op, string asm, RegisterClass dst_rc, 885 RegisterClass src_rc, string dns=""> 886 : MIMG_gfx90a<op.GFX10M, (outs getLdStRegisterOperand<dst_rc>.ret:$vdata), dns> { 887 let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, 888 DMask:$dmask, UNorm:$unorm, CPol:$cpol, 889 R128A16:$r128, LWE:$lwe, DA:$da), 890 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 891 let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$cpol$r128$lwe$da" 892 #!if(BaseOpcode.HasD16, "$d16", ""); 893} 894 895class MIMG_Sampler_gfx10<mimgopc op, string opcode, 896 RegisterClass DataRC, RegisterClass AddrRC, 897 string dns=""> 898 : MIMG_gfx10<op.GFX10M, (outs DataRC:$vdata), dns> { 899 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, SReg_128:$ssamp, 900 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol, 901 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 902 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 903 let AsmString = opcode#" $vdata, $vaddr0, $srsrc, $ssamp$dmask$dim$unorm" 904 #"$cpol$r128$a16$tfe$lwe" 905 #!if(BaseOpcode.HasD16, "$d16", ""); 906} 907 908class MIMG_Sampler_nsa_gfx10<mimgopc op, string opcode, 909 RegisterClass DataRC, int num_addrs, 910 string dns=""> 911 : MIMG_nsa_gfx10<op.GFX10M, (outs DataRC:$vdata), num_addrs, dns> { 912 let InOperandList = !con(AddrIns, 913 (ins SReg_256:$srsrc, SReg_128:$ssamp, DMask:$dmask, 914 Dim:$dim, UNorm:$unorm, CPol:$cpol, 915 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 916 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 917 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc, $ssamp$dmask$dim$unorm" 918 #"$cpol$r128$a16$tfe$lwe" 919 #!if(BaseOpcode.HasD16, "$d16", ""); 920} 921 922class MIMG_Sampler_gfx11<mimgopc op, string opcode, 923 RegisterClass DataRC, RegisterClass AddrRC, 924 string dns=""> 925 : MIMG_gfx11<op.GFX11, (outs DataRC:$vdata), dns> { 926 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, SReg_128:$ssamp, 927 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol, 928 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 929 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 930 let AsmString = opcode#" $vdata, $vaddr0, $srsrc, $ssamp$dmask$dim$unorm" 931 #"$cpol$r128$a16$tfe$lwe" 932 #!if(BaseOpcode.HasD16, "$d16", ""); 933} 934 935class MIMG_Sampler_nsa_gfx11<mimgopc op, string opcode, 936 RegisterClass DataRC, int num_addrs, 937 string dns=""> 938 : MIMG_nsa_gfx11<op.GFX11, (outs DataRC:$vdata), num_addrs, dns> { 939 let InOperandList = !con(AddrIns, 940 (ins SReg_256:$srsrc, SReg_128:$ssamp, DMask:$dmask, 941 Dim:$dim, UNorm:$unorm, CPol:$cpol, 942 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 943 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 944 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc, $ssamp$dmask$dim$unorm" 945 #"$cpol$r128$a16$tfe$lwe" 946 #!if(BaseOpcode.HasD16, "$d16", ""); 947} 948 949class MIMGAddrSize<int dw, bit enable_disasm> { 950 int NumWords = dw; 951 952 RegisterClass RegClass = !if(!le(NumWords, 0), ?, 953 !if(!eq(NumWords, 1), VGPR_32, 954 !if(!eq(NumWords, 2), VReg_64, 955 !if(!eq(NumWords, 3), VReg_96, 956 !if(!eq(NumWords, 4), VReg_128, 957 !if(!eq(NumWords, 5), VReg_160, 958 !if(!eq(NumWords, 6), VReg_192, 959 !if(!eq(NumWords, 7), VReg_224, 960 !if(!le(NumWords, 8), VReg_256, 961 !if(!le(NumWords, 16), VReg_512, ?)))))))))); 962 963 // Whether the instruction variant with this vaddr size should be enabled for 964 // the auto-generated disassembler. 965 bit Disassemble = enable_disasm; 966} 967 968// Return whether x is in lst. 969class isIntInList<int x, list<int> lst> { 970 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !eq(x, y))); 971} 972 973// Return whether a value inside the range [min, max] (endpoints inclusive) 974// is in the given list. 975class isRangeInList<int min, int max, list<int> lst> { 976 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !and(!le(min, y), !le(y, max)))); 977} 978 979class MIMGAddrSizes_dw_range<list<int> range> { 980 int Min = !head(range); 981 int Max = !if(!empty(!tail(range)), Min, !head(!tail(range))); 982} 983 984class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> { 985 // List of all possible numbers of address words, taking all combinations of 986 // A16 and image dimension into account (note: no MSAA, since this is for 987 // sample/gather ops). 988 list<int> AllNumAddrWords = 989 !foreach(dw, !if(sample.Gradients, 990 !if(!eq(sample.LodOrClamp, ""), 991 [2, 3, 4, 5, 6, 7, 8, 9], 992 [2, 3, 4, 5, 6, 7, 8, 9, 10]), 993 !if(!eq(sample.LodOrClamp, ""), 994 [1, 2, 3], 995 [1, 2, 3, 4])), 996 !add(dw, !size(sample.ExtraAddrArgs))); 997 998 // Generate machine instructions based on possible register classes for the 999 // required numbers of address words. The disassembler defaults to the 1000 // smallest register class. 1001 list<MIMGAddrSize> MachineInstrs = 1002 !foldl([]<MIMGAddrSize>, 1003 !foreach(range, 1004 // V4 is generated for V3 and V4 1005 // V8 is generated for V5 through V8 1006 // V16 is generated for V9 through V16 1007 [[1],[2],[3],[3,4],[5],[6],[7],[5,8],[9,16]], 1008 MIMGAddrSizes_dw_range<range>), 1009 lhs, dw, 1010 !if(isRangeInList<dw.Min, dw.Max, AllNumAddrWords>.ret, 1011 !listconcat(lhs, [MIMGAddrSize<dw.Max, !empty(lhs)>]), 1012 lhs)); 1013 1014 // For NSA, generate machine instructions for all possible numbers of words 1015 // except 1 (which is already covered by the non-NSA case). 1016 // The disassembler defaults to the largest number of arguments among the 1017 // variants with the same number of NSA words, and custom code then derives 1018 // the exact variant based on the sample variant and the image dimension. 1019 list<MIMGAddrSize> NSAInstrs = 1020 !foldl([]<MIMGAddrSize>, [[12, 11, 10], [9, 8, 7, 6], [5, 4, 3, 2]], prev, nsa_group, 1021 !listconcat(prev, 1022 !foldl([]<MIMGAddrSize>, nsa_group, lhs, dw, 1023 !if(isIntInList<dw, AllNumAddrWords>.ret, 1024 !listconcat(lhs, [MIMGAddrSize<dw, !empty(lhs)>]), 1025 lhs)))); 1026} 1027 1028multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm, 1029 AMDGPUSampleVariant sample, RegisterClass dst_rc, 1030 bit enableDisasm = 0, 1031 bit ExtendedImageInst = 1> { 1032 foreach addr = MIMG_Sampler_AddrSizes<sample>.MachineInstrs in { 1033 let VAddrDwords = addr.NumWords in { 1034 if op.HAS_GFX10M then { 1035 def _V # addr.NumWords 1036 : MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass, 1037 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 1038 if !not(ExtendedImageInst) then 1039 def _V # addr.NumWords # _gfx90a 1040 : MIMG_Sampler_gfx90a <op, asm, dst_rc, addr.RegClass, 1041 !if(!and(enableDisasm, addr.Disassemble), "GFX90A", "")>; 1042 def _V # addr.NumWords # _gfx10 1043 : MIMG_Sampler_gfx10 <op, asm, dst_rc, addr.RegClass, 1044 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 1045 } 1046 if op.HAS_GFX11 then { 1047 def _V # addr.NumWords # _gfx11 1048 : MIMG_Sampler_gfx11 <op, asm, dst_rc, addr.RegClass, 1049 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 1050 } 1051 } 1052 } 1053 1054 foreach addr = MIMG_Sampler_AddrSizes<sample>.NSAInstrs in { 1055 let VAddrDwords = addr.NumWords in { 1056 if op.HAS_GFX10M then { 1057 def _V # addr.NumWords # _nsa_gfx10 1058 : MIMG_Sampler_nsa_gfx10<op, asm, dst_rc, addr.NumWords, 1059 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 1060 } 1061 if !and(op.HAS_GFX11, !le(addr.NumWords, 5)) then { 1062 def _V # addr.NumWords # _nsa_gfx11 1063 : MIMG_Sampler_nsa_gfx11<op, asm, dst_rc, addr.NumWords, 1064 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 1065 } 1066 } 1067 } 1068} 1069 1070class MIMG_Sampler_BaseOpcode<AMDGPUSampleVariant sample> 1071 : MIMGBaseOpcode { 1072 let Sampler = 1; 1073 let NumExtraArgs = !size(sample.ExtraAddrArgs); 1074 let Gradients = sample.Gradients; 1075 let LodOrClampOrMip = !ne(sample.LodOrClamp, ""); 1076} 1077 1078multiclass MIMG_Sampler <mimgopc op, AMDGPUSampleVariant sample, bit wqm = 0, 1079 bit isG16 = 0, bit isGetLod = 0, 1080 string asm = "image_sample"#sample.LowerCaseMod#!if(isG16, "_g16", ""), 1081 bit ExtendedImageInst = !ne(sample.LowerCaseMod, "")> { 1082 def "" : MIMG_Sampler_BaseOpcode<sample> { 1083 let HasD16 = !not(isGetLod); 1084 let G16 = isG16; 1085 } 1086 1087 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm, 1088 mayLoad = !not(isGetLod) in { 1089 let VDataDwords = 1 in 1090 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, sample, VGPR_32, 1, ExtendedImageInst>; 1091 let VDataDwords = 2 in 1092 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64, 0, ExtendedImageInst>; 1093 let VDataDwords = 3 in 1094 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_96, 0, ExtendedImageInst>; 1095 let VDataDwords = 4 in 1096 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 0, ExtendedImageInst>; 1097 let VDataDwords = 5 in 1098 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160, 0, ExtendedImageInst>; 1099 } 1100} 1101 1102multiclass MIMG_Sampler_WQM <mimgopc op, AMDGPUSampleVariant sample> 1103 : MIMG_Sampler<op, sample, 1>; 1104 1105multiclass MIMG_Gather <mimgopc op, AMDGPUSampleVariant sample, bit wqm = 0, 1106 string asm = "image_gather4"#sample.LowerCaseMod> { 1107 def "" : MIMG_Sampler_BaseOpcode<sample> { 1108 let HasD16 = 1; 1109 let Gather4 = 1; 1110 } 1111 1112 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm, 1113 Gather4 = 1 in { 1114 let VDataDwords = 2 in 1115 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>; /* for packed D16 only */ 1116 let VDataDwords = 4 in 1117 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 1>; 1118 let VDataDwords = 5 in 1119 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160>; 1120 } 1121} 1122 1123multiclass MIMG_Gather_WQM <mimgopc op, AMDGPUSampleVariant sample> 1124 : MIMG_Gather<op, sample, 1>; 1125 1126class MIMG_IntersectRay_Helper<bit Is64, bit A16> { 1127 int num_addrs = !if(Is64, !if(A16, 9, 12), !if(A16, 8, 11)); 1128 // TODO: MIMGAddrSize will choose VReg_512 which is a 16 register tuple, 1129 // when we only need 9, 11 or 12 depending on A16 field and ptr size. 1130 RegisterClass RegClass = MIMGAddrSize<num_addrs, 0>.RegClass; 1131 int VAddrDwords = !srl(RegClass.Size, 5); 1132 1133 int gfx11_nsa_addrs = !if(A16, 4, 5); 1134 RegisterClass node_ptr_type = !if(Is64, VReg_64, VGPR_32); 1135 list<RegisterClass> gfx11_addr_types = 1136 !if(A16, 1137 [node_ptr_type, VGPR_32, VReg_96, VReg_96], 1138 [node_ptr_type, VGPR_32, VReg_96, VReg_96, VReg_96]); 1139} 1140 1141class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterClass AddrRC, bit A16> 1142 : MIMG_gfx10<op.GFX10M, (outs VReg_128:$vdata), "AMDGPU"> { 1143 1144 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_128:$srsrc), 1145 !if(A16, (ins GFX10A16:$a16), (ins))); 1146 let AsmString = opcode#" $vdata, $vaddr0, $srsrc"#!if(A16, "$a16", ""); 1147 1148 let nsa = 0; 1149} 1150 1151class MIMG_IntersectRay_nsa_gfx10<mimgopc op, string opcode, int num_addrs, bit A16> 1152 : MIMG_nsa_gfx10<op.GFX10M, (outs VReg_128:$vdata), num_addrs, "AMDGPU"> { 1153 let InOperandList = !con(nsah.AddrIns, 1154 (ins SReg_128:$srsrc), 1155 !if(A16, (ins GFX10A16:$a16), (ins))); 1156 let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc"#!if(A16, "$a16", ""); 1157} 1158 1159class MIMG_IntersectRay_gfx11<mimgopc op, string opcode, RegisterClass AddrRC, bit A16> 1160 : MIMG_gfx11<op.GFX11, (outs VReg_128:$vdata), "AMDGPU"> { 1161 1162 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_128:$srsrc), 1163 !if(A16, (ins GFX10A16:$a16), (ins))); 1164 let AsmString = opcode#" $vdata, $vaddr0, $srsrc"#!if(A16, "$a16", ""); 1165 1166 let nsa = 0; 1167} 1168 1169class MIMG_IntersectRay_nsa_gfx11<mimgopc op, string opcode, int num_addrs, 1170 bit A16, list<RegisterClass> addr_types> 1171 : MIMG_nsa_gfx11<op.GFX11, (outs VReg_128:$vdata), num_addrs, "AMDGPU", 1172 addr_types> { 1173 let InOperandList = !con(nsah.AddrIns, 1174 (ins SReg_128:$srsrc), 1175 !if(A16, (ins GFX10A16:$a16), (ins))); 1176 let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc"#!if(A16, "$a16", ""); 1177} 1178 1179multiclass MIMG_IntersectRay<mimgopc op, string opcode, bit Is64, bit A16> { 1180 defvar info = MIMG_IntersectRay_Helper<Is64, A16>; 1181 def "" : MIMGBaseOpcode { 1182 let BVH = 1; 1183 } 1184 let AsmMatchConverter = !if(A16, "cvtIntersectRay", ""), 1185 dmask = 0xf, 1186 unorm = 1, 1187 d16 = 0, 1188 cpol = 0, 1189 tfe = 0, 1190 lwe = 0, 1191 r128 = 1, 1192 ssamp = 0, 1193 dim = {0, 0, 0}, 1194 a16 = A16, 1195 d16 = 0, 1196 BaseOpcode = !cast<MIMGBaseOpcode>(NAME), 1197 VDataDwords = 4 in { 1198 def _sa_gfx10 : MIMG_IntersectRay_gfx10<op, opcode, info.RegClass, A16> { 1199 let VAddrDwords = info.VAddrDwords; 1200 } 1201 def _sa_gfx11 : MIMG_IntersectRay_gfx11<op, opcode, info.RegClass, A16> { 1202 let VAddrDwords = info.VAddrDwords; 1203 } 1204 def _nsa_gfx10 : MIMG_IntersectRay_nsa_gfx10<op, opcode, info.num_addrs, A16> { 1205 let VAddrDwords = info.num_addrs; 1206 } 1207 def _nsa_gfx11 : MIMG_IntersectRay_nsa_gfx11<op, opcode, 1208 info.gfx11_nsa_addrs, A16, 1209 info.gfx11_addr_types> { 1210 let VAddrDwords = info.num_addrs; 1211 } 1212 } 1213} 1214 1215multiclass MIMG_MSAA_Load <mimgopc op, string asm> { 1216 def "" : MIMGBaseOpcode { 1217 let HasD16 = 1; 1218 let Gather4 = 1; /* for appropriate dmask handling */ 1219 let MSAA = 1; 1220 } 1221 1222 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), 1223 Gather4 = 1, hasPostISelHook = 0, mayLoad = 1 in { 1224 let VDataDwords = 2 in 1225 defm _V2 : MIMG_NoSampler_Src_Helper<op, asm, VReg_64, 0>; /* packed D16 */ 1226 let VDataDwords = 3 in 1227 defm _V3 : MIMG_NoSampler_Src_Helper<op, asm, VReg_96, 0>; /* packed D16 + tfe */ 1228 let VDataDwords = 4 in 1229 defm _V4 : MIMG_NoSampler_Src_Helper<op, asm, VReg_128, 1>; 1230 let VDataDwords = 5 in 1231 defm _V5 : MIMG_NoSampler_Src_Helper<op, asm, VReg_160, 0>; 1232 } 1233} 1234 1235//===----------------------------------------------------------------------===// 1236// MIMG Instructions 1237//===----------------------------------------------------------------------===// 1238let OtherPredicates = [HasImageInsts] in { 1239 1240defm IMAGE_LOAD : MIMG_NoSampler <mimgopc<0x00, 0x00>, "image_load", 1>; 1241defm IMAGE_LOAD_MIP : MIMG_NoSampler <mimgopc<0x01, 0x01>, "image_load_mip", 1, 1>; 1242defm IMAGE_LOAD_PCK : MIMG_NoSampler <mimgopc<0x02, 0x02>, "image_load_pck", 0>; 1243defm IMAGE_LOAD_PCK_SGN : MIMG_NoSampler <mimgopc<0x03, 0x03>, "image_load_pck_sgn", 0>; 1244defm IMAGE_LOAD_MIP_PCK : MIMG_NoSampler <mimgopc<0x04, 0x04>, "image_load_mip_pck", 0, 1>; 1245defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoSampler <mimgopc<0x05, 0x05>, "image_load_mip_pck_sgn", 0, 1>; 1246defm IMAGE_STORE : MIMG_Store <mimgopc<0x06, 0x08>, "image_store", 1>; 1247defm IMAGE_STORE_MIP : MIMG_Store <mimgopc<0x07, 0x09>, "image_store_mip", 1, 1>; 1248defm IMAGE_STORE_PCK : MIMG_Store <mimgopc<0x08, 0x0a>, "image_store_pck", 0>; 1249defm IMAGE_STORE_MIP_PCK : MIMG_Store <mimgopc<0x09, 0x0b>, "image_store_mip_pck", 0, 1>; 1250 1251defm IMAGE_GET_RESINFO : MIMG_NoSampler <mimgopc<0x17, 0x0e>, "image_get_resinfo", 0, 1, 1>; 1252 1253defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimgopc<0x0a, 0x0f, 0x10, 0x0f>, "image_atomic_swap">; 1254defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimgopc<0x0b, 0x10, 0x11, 0x10>, "image_atomic_cmpswap", 1>; 1255defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimgopc<0x0c, 0x11, 0x12, 0x11>, "image_atomic_add">; 1256defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimgopc<0x0d, 0x12, 0x13, 0x12>, "image_atomic_sub">; 1257defm IMAGE_ATOMIC_RSUB : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x13>, "image_atomic_rsub">; 1258defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimgopc<0x0e, 0x14>, "image_atomic_smin">; 1259defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimgopc<0x0f, 0x15>, "image_atomic_umin">; 1260defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimgopc<0x10, 0x16>, "image_atomic_smax">; 1261defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimgopc<0x11, 0x17>, "image_atomic_umax">; 1262defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimgopc<0x12, 0x18>, "image_atomic_and">; 1263defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimgopc<0x13, 0x19>, "image_atomic_or">; 1264defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimgopc<0x14, 0x1a>, "image_atomic_xor">; 1265defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimgopc<0x15, 0x1b>, "image_atomic_inc">; 1266defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimgopc<0x16, 0x1c>, "image_atomic_dec">; 1267defm IMAGE_ATOMIC_FCMPSWAP : MIMG_Atomic <mimgopc<MIMG.NOP, 0x1d, MIMG.NOP>, "image_atomic_fcmpswap", 1, 1>; 1268defm IMAGE_ATOMIC_FMIN : MIMG_Atomic <mimgopc<MIMG.NOP, 0x1e, MIMG.NOP>, "image_atomic_fmin", 0, 1>; 1269defm IMAGE_ATOMIC_FMAX : MIMG_Atomic <mimgopc<MIMG.NOP, 0x1f, MIMG.NOP>, "image_atomic_fmax", 0, 1>; 1270 1271defm IMAGE_SAMPLE : MIMG_Sampler_WQM <mimgopc<0x1b, 0x20>, AMDGPUSample>; 1272let OtherPredicates = [HasExtendedImageInsts] in { 1273defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <mimgopc<0x40, 0x21>, AMDGPUSample_cl>; 1274defm IMAGE_SAMPLE_D : MIMG_Sampler <mimgopc<0x1c, 0x22>, AMDGPUSample_d>; 1275defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <mimgopc<0x41, 0x23>, AMDGPUSample_d_cl>; 1276defm IMAGE_SAMPLE_L : MIMG_Sampler <mimgopc<0x1d, 0x24>, AMDGPUSample_l>; 1277defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <mimgopc<0x1e, 0x25>, AMDGPUSample_b>; 1278defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <mimgopc<0x42, 0x26>, AMDGPUSample_b_cl>; 1279defm IMAGE_SAMPLE_LZ : MIMG_Sampler <mimgopc<0x1f, 0x27>, AMDGPUSample_lz>; 1280defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <mimgopc<0x20, 0x28>, AMDGPUSample_c>; 1281defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <mimgopc<0x43, 0x29>, AMDGPUSample_c_cl>; 1282defm IMAGE_SAMPLE_C_D : MIMG_Sampler <mimgopc<0x21, 0x2a>, AMDGPUSample_c_d>; 1283defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <mimgopc<0x44, 0x2b>, AMDGPUSample_c_d_cl>; 1284defm IMAGE_SAMPLE_C_L : MIMG_Sampler <mimgopc<0x22, 0x2c>, AMDGPUSample_c_l>; 1285defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <mimgopc<0x23, 0x2d>, AMDGPUSample_c_b>; 1286defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <mimgopc<0x45, 0x2e>, AMDGPUSample_c_b_cl>; 1287defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <mimgopc<0x24, 0x2f>, AMDGPUSample_c_lz>; 1288defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <mimgopc<0x25, 0x30>, AMDGPUSample_o>; 1289defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <mimgopc<0x46, 0x31>, AMDGPUSample_cl_o>; 1290defm IMAGE_SAMPLE_D_O : MIMG_Sampler <mimgopc<0x26, 0x32>, AMDGPUSample_d_o>; 1291defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <mimgopc<0x47, 0x33>, AMDGPUSample_d_cl_o>; 1292defm IMAGE_SAMPLE_L_O : MIMG_Sampler <mimgopc<0x27, 0x34>, AMDGPUSample_l_o>; 1293defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <mimgopc<0x28, 0x35>, AMDGPUSample_b_o>; 1294defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <mimgopc<0x48, 0x36>, AMDGPUSample_b_cl_o>; 1295defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <mimgopc<0x29, 0x37>, AMDGPUSample_lz_o>; 1296defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <mimgopc<0x2a, 0x38>, AMDGPUSample_c_o>; 1297defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <mimgopc<0x49, 0x39>, AMDGPUSample_c_cl_o>; 1298defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <mimgopc<0x2b, 0x3a>, AMDGPUSample_c_d_o>; 1299defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <mimgopc<0x4a, 0x3b>, AMDGPUSample_c_d_cl_o>; 1300defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <mimgopc<0x2c, 0x3c>, AMDGPUSample_c_l_o>; 1301defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <mimgopc<0x4b, 0x3e>, AMDGPUSample_c_b_cl_o>; 1302defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <mimgopc<0x2d, 0x3d>, AMDGPUSample_c_b_o>; 1303defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <mimgopc<0x2e, 0x3f>, AMDGPUSample_c_lz_o>; 1304defm IMAGE_GATHER4 : MIMG_Gather_WQM <mimgopc<0x2f, 0x40>, AMDGPUSample>; 1305defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <mimgopc<0x60, 0x41>, AMDGPUSample_cl>; 1306defm IMAGE_GATHER4_L : MIMG_Gather <mimgopc<0x30, 0x44>, AMDGPUSample_l>; 1307defm IMAGE_GATHER4_B : MIMG_Gather_WQM <mimgopc<0x31, 0x45>, AMDGPUSample_b>; 1308defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <mimgopc<0x61, 0x46>, AMDGPUSample_b_cl>; 1309defm IMAGE_GATHER4_LZ : MIMG_Gather <mimgopc<0x32, 0x47>, AMDGPUSample_lz>; 1310defm IMAGE_GATHER4_C : MIMG_Gather_WQM <mimgopc<0x33, 0x48>, AMDGPUSample_c>; 1311defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <mimgopc<0x62, 0x49>, AMDGPUSample_c_cl>; 1312defm IMAGE_GATHER4_C_L : MIMG_Gather <mimgopc<0x63, 0x4c>, AMDGPUSample_c_l>; 1313defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <mimgopc<0x64, 0x4d>, AMDGPUSample_c_b>; 1314defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <mimgopc<0x65, 0x4e>, AMDGPUSample_c_b_cl>; 1315defm IMAGE_GATHER4_C_LZ : MIMG_Gather <mimgopc<0x34, 0x4f>, AMDGPUSample_c_lz>; 1316defm IMAGE_GATHER4_O : MIMG_Gather_WQM <mimgopc<0x35, 0x50>, AMDGPUSample_o>; 1317defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, 0x51>, AMDGPUSample_cl_o>; 1318defm IMAGE_GATHER4_L_O : MIMG_Gather <mimgopc<MIMG.NOP, 0x54>, AMDGPUSample_l_o>; 1319defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, 0x55>, AMDGPUSample_b_o>; 1320defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <mimgopc<MIMG.NOP, 0x56>, AMDGPUSample_b_cl_o>; 1321defm IMAGE_GATHER4_LZ_O : MIMG_Gather <mimgopc<0x36, 0x57>, AMDGPUSample_lz_o>; 1322defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, 0x58>, AMDGPUSample_c_o>; 1323defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, 0x59>, AMDGPUSample_c_cl_o>; 1324defm IMAGE_GATHER4_C_L_O : MIMG_Gather <mimgopc<MIMG.NOP, 0x5c>, AMDGPUSample_c_l_o>; 1325defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, 0x5d>, AMDGPUSample_c_b_o>; 1326defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <mimgopc<MIMG.NOP, 0x5e>, AMDGPUSample_c_b_cl_o>; 1327defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <mimgopc<0x37, 0x5f>, AMDGPUSample_c_lz_o>; 1328//defm IMAGE_GATHER4H : MIMG_Gather_WQM <mimgopc<0x90, 0x61>, ?>; 1329 1330defm IMAGE_GET_LOD : MIMG_Sampler <mimgopc<0x38, 0x60>, AMDGPUSample, 1, 0, 1, "image_get_lod">; 1331 1332defm IMAGE_SAMPLE_CD : MIMG_Sampler <mimgopc<MIMG.NOP, 0x68>, AMDGPUSample_cd>; 1333defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <mimgopc<MIMG.NOP, 0x69>, AMDGPUSample_cd_cl>; 1334defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <mimgopc<MIMG.NOP, 0x6a>, AMDGPUSample_c_cd>; 1335defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <mimgopc<MIMG.NOP, 0x6b>, AMDGPUSample_c_cd_cl>; 1336defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <mimgopc<MIMG.NOP, 0x6c>, AMDGPUSample_cd_o>; 1337defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <mimgopc<MIMG.NOP, 0x6d>, AMDGPUSample_cd_cl_o>; 1338defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <mimgopc<MIMG.NOP, 0x6e>, AMDGPUSample_c_cd_o>; 1339defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <mimgopc<MIMG.NOP, 0x6f>, AMDGPUSample_c_cd_cl_o>; 1340} // End OtherPredicates = [HasExtendedImageInsts] 1341 1342let OtherPredicates = [HasExtendedImageInsts,HasG16] in { 1343defm IMAGE_SAMPLE_D_G16 : MIMG_Sampler <mimgopc<0x39, 0xa2>, AMDGPUSample_d, 0, 1>; 1344defm IMAGE_SAMPLE_D_CL_G16 : MIMG_Sampler <mimgopc<0x5f, 0xa3>, AMDGPUSample_d_cl, 0, 1>; 1345defm IMAGE_SAMPLE_C_D_G16 : MIMG_Sampler <mimgopc<0x3a, 0xaa>, AMDGPUSample_c_d, 0, 1>; 1346defm IMAGE_SAMPLE_C_D_CL_G16 : MIMG_Sampler <mimgopc<0x54, 0xab>, AMDGPUSample_c_d_cl, 0, 1>; 1347defm IMAGE_SAMPLE_D_O_G16 : MIMG_Sampler <mimgopc<0x3b, 0xb2>, AMDGPUSample_d_o, 0, 1>; 1348defm IMAGE_SAMPLE_D_CL_O_G16 : MIMG_Sampler <mimgopc<0x55, 0xb3>, AMDGPUSample_d_cl_o, 0, 1>; 1349defm IMAGE_SAMPLE_C_D_O_G16 : MIMG_Sampler <mimgopc<0x3c, 0xba>, AMDGPUSample_c_d_o, 0, 1>; 1350defm IMAGE_SAMPLE_C_D_CL_O_G16 : MIMG_Sampler <mimgopc<0x56, 0xbb>, AMDGPUSample_c_d_cl_o, 0, 1>; 1351defm IMAGE_SAMPLE_CD_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, 0xe8>, AMDGPUSample_cd, 0, 1>; 1352defm IMAGE_SAMPLE_CD_CL_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, 0xe9>, AMDGPUSample_cd_cl, 0, 1>; 1353defm IMAGE_SAMPLE_C_CD_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, 0xea>, AMDGPUSample_c_cd, 0, 1>; 1354defm IMAGE_SAMPLE_C_CD_CL_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, 0xeb>, AMDGPUSample_c_cd_cl, 0, 1>; 1355defm IMAGE_SAMPLE_CD_O_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, 0xec>, AMDGPUSample_cd_o, 0, 1>; 1356defm IMAGE_SAMPLE_CD_CL_O_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, 0xed>, AMDGPUSample_cd_cl_o, 0, 1>; 1357defm IMAGE_SAMPLE_C_CD_O_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, 0xee>, AMDGPUSample_c_cd_o, 0, 1>; 1358defm IMAGE_SAMPLE_C_CD_CL_O_G16 : MIMG_Sampler <mimgopc<MIMG.NOP, 0xef>, AMDGPUSample_c_cd_cl_o, 0, 1>; 1359} // End OtherPredicates = [HasExtendedImageInsts,HasG16] 1360 1361//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", mimgopc<0x7e>>; 1362//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", mimgopc<0x7f>>; 1363 1364let SubtargetPredicate = isGFX10Only, OtherPredicates = [HasGFX10_AEncoding] in 1365defm IMAGE_MSAA_LOAD_X : MIMG_NoSampler <mimgopc<MIMG.NOP, 0x80>, "image_msaa_load", 1, 0, 0, 1>; 1366 1367let OtherPredicates = [HasGFX10_AEncoding] in 1368defm IMAGE_MSAA_LOAD : MIMG_MSAA_Load <mimgopc<0x18, MIMG.NOP>, "image_msaa_load">; 1369 1370let OtherPredicates = [HasGFX10_AEncoding] in { 1371defm IMAGE_BVH_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0x19, 0xe6>, "image_bvh_intersect_ray", 0, 0>; 1372defm IMAGE_BVH_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<0x19, 0xe6>, "image_bvh_intersect_ray", 0, 1>; 1373defm IMAGE_BVH64_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0x1a, 0xe7>, "image_bvh64_intersect_ray", 1, 0>; 1374defm IMAGE_BVH64_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<0x1a, 0xe7>, "image_bvh64_intersect_ray", 1, 1>; 1375} // End OtherPredicates = [HasGFX10_AEncoding] 1376 1377} // End let OtherPredicates = [HasImageInsts] 1378 1379/********** ========================================= **********/ 1380/********** Table of dimension-aware image intrinsics **********/ 1381/********** ========================================= **********/ 1382 1383class ImageDimIntrinsicInfo<AMDGPUImageDimIntrinsic I> { 1384 Intrinsic Intr = I; 1385 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(!strconcat("IMAGE_", I.P.OpMod)); 1386 AMDGPUDimProps Dim = I.P.Dim; 1387 AMDGPUImageDimIntrinsicEval DimEval = AMDGPUImageDimIntrinsicEval<I.P>; 1388 1389 bits<8> NumOffsetArgs = DimEval.NumOffsetArgs; 1390 bits<8> NumBiasArgs = DimEval.NumBiasArgs; 1391 bits<8> NumZCompareArgs = DimEval.NumZCompareArgs; 1392 bits<8> NumGradients = DimEval.NumGradientArgs; 1393 bits<8> NumDmask = DimEval.NumDmaskArgs; 1394 bits<8> NumData = DimEval.NumDataArgs; 1395 bits<8> NumVAddrs = DimEval.NumVAddrArgs; 1396 bits<8> NumArgs = !add(DimEval.CachePolicyArgIndex, 1); 1397 1398 bits<8> DMaskIndex = DimEval.DmaskArgIndex; 1399 bits<8> VAddrStart = DimEval.VAddrArgIndex; 1400 bits<8> OffsetIndex = DimEval.OffsetArgIndex; 1401 bits<8> BiasIndex = DimEval.BiasArgIndex; 1402 bits<8> ZCompareIndex = DimEval.ZCompareArgIndex; 1403 bits<8> GradientStart = DimEval.GradientArgIndex; 1404 bits<8> CoordStart = DimEval.CoordArgIndex; 1405 bits<8> LodIndex = DimEval.LodArgIndex; 1406 bits<8> MipIndex = DimEval.MipArgIndex; 1407 bits<8> VAddrEnd = !add(DimEval.VAddrArgIndex, DimEval.NumVAddrArgs); 1408 bits<8> RsrcIndex = DimEval.RsrcArgIndex; 1409 bits<8> SampIndex = DimEval.SampArgIndex; 1410 bits<8> UnormIndex = DimEval.UnormArgIndex; 1411 bits<8> TexFailCtrlIndex = DimEval.TexFailCtrlArgIndex; 1412 bits<8> CachePolicyIndex = DimEval.CachePolicyArgIndex; 1413 1414 bits<8> BiasTyArg = !add(I.P.NumRetAndDataAnyTypes, 1415 !if(!eq(NumOffsetArgs, 0), 0, I.P.ExtraAddrArgs[0].Type.isAny)); 1416 bits<8> GradientTyArg = !add(I.P.NumRetAndDataAnyTypes, 1417 !foldl(0, I.P.ExtraAddrArgs, cnt, arg, !add(cnt, arg.Type.isAny))); 1418 bits<8> CoordTyArg = !add(GradientTyArg, !if(I.P.Gradients, 1, 0)); 1419} 1420 1421def ImageDimIntrinsicTable : GenericTable { 1422 let FilterClass = "ImageDimIntrinsicInfo"; 1423 let Fields = ["Intr", "BaseOpcode", "Dim", "NumOffsetArgs", "NumBiasArgs", "NumZCompareArgs", "NumGradients", "NumDmask", "NumData", "NumVAddrs", "NumArgs", 1424 "DMaskIndex", "VAddrStart", "OffsetIndex", "BiasIndex", "ZCompareIndex", "GradientStart", "CoordStart", "LodIndex", "MipIndex", "VAddrEnd", 1425 "RsrcIndex", "SampIndex", "UnormIndex", "TexFailCtrlIndex", "CachePolicyIndex", 1426 "BiasTyArg", "GradientTyArg", "CoordTyArg"]; 1427 string TypeOf_BaseOpcode = "MIMGBaseOpcode"; 1428 string TypeOf_Dim = "MIMGDim"; 1429 1430 let PrimaryKey = ["Intr"]; 1431 let PrimaryKeyName = "getImageDimIntrinsicInfo"; 1432 let PrimaryKeyEarlyOut = 1; 1433} 1434 1435def getImageDimIntrinsicByBaseOpcode : SearchIndex { 1436 let Table = ImageDimIntrinsicTable; 1437 let Key = ["BaseOpcode", "Dim"]; 1438} 1439 1440foreach intr = !listconcat(AMDGPUImageDimIntrinsics, 1441 AMDGPUImageDimAtomicIntrinsics) in { 1442 def : ImageDimIntrinsicInfo<intr>; 1443} 1444 1445// L to LZ Optimization Mapping 1446def : MIMGLZMapping<IMAGE_SAMPLE_L, IMAGE_SAMPLE_LZ>; 1447def : MIMGLZMapping<IMAGE_SAMPLE_C_L, IMAGE_SAMPLE_C_LZ>; 1448def : MIMGLZMapping<IMAGE_SAMPLE_L_O, IMAGE_SAMPLE_LZ_O>; 1449def : MIMGLZMapping<IMAGE_SAMPLE_C_L_O, IMAGE_SAMPLE_C_LZ_O>; 1450def : MIMGLZMapping<IMAGE_GATHER4_L, IMAGE_GATHER4_LZ>; 1451def : MIMGLZMapping<IMAGE_GATHER4_C_L, IMAGE_GATHER4_C_LZ>; 1452def : MIMGLZMapping<IMAGE_GATHER4_L_O, IMAGE_GATHER4_LZ_O>; 1453def : MIMGLZMapping<IMAGE_GATHER4_C_L_O, IMAGE_GATHER4_C_LZ_O>; 1454 1455// MIP to NONMIP Optimization Mapping 1456def : MIMGMIPMapping<IMAGE_LOAD_MIP, IMAGE_LOAD>; 1457def : MIMGMIPMapping<IMAGE_STORE_MIP, IMAGE_STORE>; 1458 1459// Bias to NoBias Optimization Mapping 1460def : MIMGBiasMapping<IMAGE_SAMPLE_B, IMAGE_SAMPLE>; 1461def : MIMGBiasMapping<IMAGE_SAMPLE_B_CL, IMAGE_SAMPLE_CL>; 1462def : MIMGBiasMapping<IMAGE_SAMPLE_C_B, IMAGE_SAMPLE_C>; 1463def : MIMGBiasMapping<IMAGE_SAMPLE_C_B_CL, IMAGE_SAMPLE_C_CL>; 1464def : MIMGBiasMapping<IMAGE_SAMPLE_B_O, IMAGE_SAMPLE_O>; 1465def : MIMGBiasMapping<IMAGE_SAMPLE_B_CL_O, IMAGE_SAMPLE_CL_O>; 1466def : MIMGBiasMapping<IMAGE_SAMPLE_C_B_O, IMAGE_SAMPLE_C_O>; 1467def : MIMGBiasMapping<IMAGE_SAMPLE_C_B_CL_O, IMAGE_SAMPLE_C_CL_O>; 1468def : MIMGBiasMapping<IMAGE_GATHER4_B, IMAGE_GATHER4>; 1469def : MIMGBiasMapping<IMAGE_GATHER4_B_CL, IMAGE_GATHER4_CL>; 1470def : MIMGBiasMapping<IMAGE_GATHER4_C_B, IMAGE_GATHER4_C>; 1471def : MIMGBiasMapping<IMAGE_GATHER4_C_B_CL, IMAGE_GATHER4_C_CL>; 1472def : MIMGBiasMapping<IMAGE_GATHER4_B_O, IMAGE_GATHER4_O>; 1473def : MIMGBiasMapping<IMAGE_GATHER4_B_CL_O, IMAGE_GATHER4_CL_O>; 1474def : MIMGBiasMapping<IMAGE_GATHER4_C_B_O, IMAGE_GATHER4_C_O>; 1475def : MIMGBiasMapping<IMAGE_GATHER4_C_B_CL_O, IMAGE_GATHER4_C_CL_O>; 1476 1477// Offset to NoOffset Optimization Mapping 1478def : MIMGOffsetMapping<IMAGE_SAMPLE_O, IMAGE_SAMPLE>; 1479def : MIMGOffsetMapping<IMAGE_SAMPLE_CL_O, IMAGE_SAMPLE_CL>; 1480def : MIMGOffsetMapping<IMAGE_SAMPLE_D_O, IMAGE_SAMPLE_D>; 1481def : MIMGOffsetMapping<IMAGE_SAMPLE_D_CL_O, IMAGE_SAMPLE_D_CL>; 1482def : MIMGOffsetMapping<IMAGE_SAMPLE_D_O_G16, IMAGE_SAMPLE_D_G16>; 1483def : MIMGOffsetMapping<IMAGE_SAMPLE_D_CL_O_G16, IMAGE_SAMPLE_D_CL_G16>; 1484def : MIMGOffsetMapping<IMAGE_SAMPLE_L_O, IMAGE_SAMPLE_L>; 1485def : MIMGOffsetMapping<IMAGE_SAMPLE_B_O, IMAGE_SAMPLE_B>; 1486def : MIMGOffsetMapping<IMAGE_SAMPLE_B_CL_O, IMAGE_SAMPLE_B_CL>; 1487def : MIMGOffsetMapping<IMAGE_SAMPLE_LZ_O, IMAGE_SAMPLE_LZ>; 1488def : MIMGOffsetMapping<IMAGE_SAMPLE_C_O, IMAGE_SAMPLE_C>; 1489def : MIMGOffsetMapping<IMAGE_SAMPLE_C_CL_O, IMAGE_SAMPLE_C_CL>; 1490def : MIMGOffsetMapping<IMAGE_SAMPLE_C_D_O, IMAGE_SAMPLE_C_D>; 1491def : MIMGOffsetMapping<IMAGE_SAMPLE_C_D_CL_O, IMAGE_SAMPLE_C_D_CL>; 1492def : MIMGOffsetMapping<IMAGE_SAMPLE_C_D_O_G16, IMAGE_SAMPLE_C_D_G16>; 1493def : MIMGOffsetMapping<IMAGE_SAMPLE_C_D_CL_O_G16, IMAGE_SAMPLE_C_D_CL_G16>; 1494def : MIMGOffsetMapping<IMAGE_SAMPLE_C_L_O, IMAGE_SAMPLE_C_L>; 1495def : MIMGOffsetMapping<IMAGE_SAMPLE_C_B_CL_O, IMAGE_SAMPLE_C_B_CL>; 1496def : MIMGOffsetMapping<IMAGE_SAMPLE_C_B_O, IMAGE_SAMPLE_C_B>; 1497def : MIMGOffsetMapping<IMAGE_SAMPLE_C_LZ_O, IMAGE_SAMPLE_C_LZ>; 1498def : MIMGOffsetMapping<IMAGE_GATHER4_O, IMAGE_GATHER4>; 1499def : MIMGOffsetMapping<IMAGE_GATHER4_CL_O, IMAGE_GATHER4_CL>; 1500def : MIMGOffsetMapping<IMAGE_GATHER4_L_O, IMAGE_GATHER4_L>; 1501def : MIMGOffsetMapping<IMAGE_GATHER4_B_O, IMAGE_GATHER4_B>; 1502def : MIMGOffsetMapping<IMAGE_GATHER4_B_CL_O, IMAGE_GATHER4_B_CL>; 1503def : MIMGOffsetMapping<IMAGE_GATHER4_LZ_O, IMAGE_GATHER4_LZ>; 1504def : MIMGOffsetMapping<IMAGE_GATHER4_C_O, IMAGE_GATHER4_C>; 1505def : MIMGOffsetMapping<IMAGE_GATHER4_C_CL_O, IMAGE_GATHER4_C_CL>; 1506def : MIMGOffsetMapping<IMAGE_GATHER4_C_L_O, IMAGE_GATHER4_C_L>; 1507def : MIMGOffsetMapping<IMAGE_GATHER4_C_B_O, IMAGE_GATHER4_C_B>; 1508def : MIMGOffsetMapping<IMAGE_GATHER4_C_B_CL_O, IMAGE_GATHER4_C_B_CL>; 1509def : MIMGOffsetMapping<IMAGE_GATHER4_C_LZ_O, IMAGE_GATHER4_C_LZ>; 1510def : MIMGOffsetMapping<IMAGE_SAMPLE_CD_O, IMAGE_SAMPLE_CD>; 1511def : MIMGOffsetMapping<IMAGE_SAMPLE_CD_CL_O, IMAGE_SAMPLE_CD_CL>; 1512def : MIMGOffsetMapping<IMAGE_SAMPLE_C_CD_O, IMAGE_SAMPLE_C_CD>; 1513def : MIMGOffsetMapping<IMAGE_SAMPLE_C_CD_CL_O, IMAGE_SAMPLE_C_CD_CL>; 1514def : MIMGOffsetMapping<IMAGE_SAMPLE_CD_O_G16, IMAGE_SAMPLE_CD_G16>; 1515def : MIMGOffsetMapping<IMAGE_SAMPLE_CD_CL_O_G16, IMAGE_SAMPLE_CD_CL_G16>; 1516def : MIMGOffsetMapping<IMAGE_SAMPLE_C_CD_O_G16, IMAGE_SAMPLE_C_CD_G16>; 1517def : MIMGOffsetMapping<IMAGE_SAMPLE_C_CD_CL_O_G16, IMAGE_SAMPLE_C_CD_CL_G16>; 1518 1519// G to G16 Optimization Mapping 1520def : MIMGG16Mapping<IMAGE_SAMPLE_D, IMAGE_SAMPLE_D_G16>; 1521def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL, IMAGE_SAMPLE_D_CL_G16>; 1522def : MIMGG16Mapping<IMAGE_SAMPLE_C_D, IMAGE_SAMPLE_C_D_G16>; 1523def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_CL, IMAGE_SAMPLE_C_D_CL_G16>; 1524def : MIMGG16Mapping<IMAGE_SAMPLE_D_O, IMAGE_SAMPLE_D_O_G16>; 1525def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL_O, IMAGE_SAMPLE_D_CL_O_G16>; 1526def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_O, IMAGE_SAMPLE_C_D_O_G16>; 1527def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_CL_O, IMAGE_SAMPLE_C_D_CL_O_G16>; 1528def : MIMGG16Mapping<IMAGE_SAMPLE_CD, IMAGE_SAMPLE_CD_G16>; 1529def : MIMGG16Mapping<IMAGE_SAMPLE_CD_CL, IMAGE_SAMPLE_CD_CL_G16>; 1530def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD, IMAGE_SAMPLE_C_CD_G16>; 1531def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_CL, IMAGE_SAMPLE_C_CD_CL_G16>; 1532def : MIMGG16Mapping<IMAGE_SAMPLE_CD_O, IMAGE_SAMPLE_CD_O_G16>; 1533def : MIMGG16Mapping<IMAGE_SAMPLE_CD_CL_O, IMAGE_SAMPLE_CD_CL_O_G16>; 1534def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_O, IMAGE_SAMPLE_C_CD_O_G16>; 1535def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_CL_O, IMAGE_SAMPLE_C_CD_CL_O_G16>; 1536