1//===-- MIMGInstructions.td - MIMG Instruction Defintions -----------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// MIMG-specific encoding families to distinguish between semantically 10// equivalent machine instructions with different encoding. 11// 12// - MIMGEncGfx6: encoding introduced with gfx6 (obsoleted for atomics in gfx8) 13// - MIMGEncGfx8: encoding introduced with gfx8 for atomics 14// - MIMGEncGfx10Default: gfx default (non-NSA) encoding 15// - MIMGEncGfx10NSA: gfx10 NSA encoding 16class MIMGEncoding; 17 18def MIMGEncGfx6 : MIMGEncoding; 19def MIMGEncGfx8 : MIMGEncoding; 20def MIMGEncGfx10Default : MIMGEncoding; 21def MIMGEncGfx10NSA : MIMGEncoding; 22 23def MIMGEncoding : GenericEnum { 24 let FilterClass = "MIMGEncoding"; 25} 26 27// Represent an ISA-level opcode, independent of the encoding and the 28// vdata/vaddr size. 29class MIMGBaseOpcode : PredicateControl { 30 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME); 31 bit Store = 0; 32 bit Atomic = 0; 33 bit AtomicX2 = 0; // (f)cmpswap 34 bit Sampler = 0; 35 bit Gather4 = 0; 36 bits<8> NumExtraArgs = 0; 37 bit Gradients = 0; 38 bit Coordinates = 1; 39 bit LodOrClampOrMip = 0; 40 bit HasD16 = 0; 41} 42 43def MIMGBaseOpcode : GenericEnum { 44 let FilterClass = "MIMGBaseOpcode"; 45} 46 47def MIMGBaseOpcodesTable : GenericTable { 48 let FilterClass = "MIMGBaseOpcode"; 49 let CppTypeName = "MIMGBaseOpcodeInfo"; 50 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler", "Gather4", 51 "NumExtraArgs", "Gradients", "Coordinates", "LodOrClampOrMip", 52 "HasD16"]; 53 GenericEnum TypeOf_BaseOpcode = MIMGBaseOpcode; 54 55 let PrimaryKey = ["BaseOpcode"]; 56 let PrimaryKeyName = "getMIMGBaseOpcodeInfo"; 57} 58 59def MIMGDim : GenericEnum { 60 let FilterClass = "AMDGPUDimProps"; 61} 62 63def MIMGDimInfoTable : GenericTable { 64 let FilterClass = "AMDGPUDimProps"; 65 let CppTypeName = "MIMGDimInfo"; 66 let Fields = ["Dim", "NumCoords", "NumGradients", "DA", "Encoding", "AsmSuffix"]; 67 GenericEnum TypeOf_Dim = MIMGDim; 68 69 let PrimaryKey = ["Dim"]; 70 let PrimaryKeyName = "getMIMGDimInfo"; 71} 72 73def getMIMGDimInfoByEncoding : SearchIndex { 74 let Table = MIMGDimInfoTable; 75 let Key = ["Encoding"]; 76} 77 78def getMIMGDimInfoByAsmSuffix : SearchIndex { 79 let Table = MIMGDimInfoTable; 80 let Key = ["AsmSuffix"]; 81} 82 83class mimg <bits<8> si_gfx10, bits<8> vi = si_gfx10> { 84 field bits<8> SI_GFX10 = si_gfx10; 85 field bits<8> VI = vi; 86} 87 88class MIMGLZMapping<MIMGBaseOpcode l, MIMGBaseOpcode lz> { 89 MIMGBaseOpcode L = l; 90 MIMGBaseOpcode LZ = lz; 91} 92 93def MIMGLZMappingTable : GenericTable { 94 let FilterClass = "MIMGLZMapping"; 95 let CppTypeName = "MIMGLZMappingInfo"; 96 let Fields = ["L", "LZ"]; 97 GenericEnum TypeOf_L = MIMGBaseOpcode; 98 GenericEnum TypeOf_LZ = MIMGBaseOpcode; 99 100 let PrimaryKey = ["L"]; 101 let PrimaryKeyName = "getMIMGLZMappingInfo"; 102} 103 104class MIMGMIPMapping<MIMGBaseOpcode mip, MIMGBaseOpcode nonmip> { 105 MIMGBaseOpcode MIP = mip; 106 MIMGBaseOpcode NONMIP = nonmip; 107} 108 109def MIMGMIPMappingTable : GenericTable { 110 let FilterClass = "MIMGMIPMapping"; 111 let CppTypeName = "MIMGMIPMappingInfo"; 112 let Fields = ["MIP", "NONMIP"]; 113 GenericEnum TypeOf_MIP = MIMGBaseOpcode; 114 GenericEnum TypeOf_NONMIP = MIMGBaseOpcode; 115 116 let PrimaryKey = ["MIP"]; 117 let PrimaryKeyName = "getMIMGMIPMappingInfo"; 118} 119 120class MIMG_Base <dag outs, string dns = ""> 121 : InstSI <outs, (ins), "", []> { 122 123 let VM_CNT = 1; 124 let EXP_CNT = 1; 125 let MIMG = 1; 126 let Uses = [EXEC]; 127 let mayLoad = 1; 128 let mayStore = 0; 129 let SchedRW = [WriteVMEM]; 130 let UseNamedOperandTable = 1; 131 let hasSideEffects = 0; // XXX ???? 132 133 let DecoderNamespace = dns; 134 let isAsmParserOnly = !if(!eq(dns,""), 1, 0); 135 let usesCustomInserter = 1; 136} 137 138class MIMG <dag outs, string dns = ""> 139 : MIMG_Base <outs, dns> { 140 141 let hasPostISelHook = 1; 142 let AsmMatchConverter = "cvtMIMG"; 143 144 Instruction Opcode = !cast<Instruction>(NAME); 145 MIMGBaseOpcode BaseOpcode; 146 MIMGEncoding MIMGEncoding; 147 bits<8> VDataDwords; 148 bits<8> VAddrDwords; 149} 150 151def MIMGInfoTable : GenericTable { 152 let FilterClass = "MIMG"; 153 let CppTypeName = "MIMGInfo"; 154 let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"]; 155 GenericEnum TypeOf_BaseOpcode = MIMGBaseOpcode; 156 GenericEnum TypeOf_MIMGEncoding = MIMGEncoding; 157 158 let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"]; 159 let PrimaryKeyName = "getMIMGOpcodeHelper"; 160} 161 162def getMIMGInfo : SearchIndex { 163 let Table = MIMGInfoTable; 164 let Key = ["Opcode"]; 165} 166 167// This is a separate class so that TableGen memoizes the computations. 168class MIMGNSAHelper<int num_addrs> { 169 list<string> AddrAsmNames = 170 !foldl([]<string>, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11], lhs, i, 171 !if(!lt(i, num_addrs), !listconcat(lhs, ["vaddr"#!size(lhs)]), lhs)); 172 dag AddrIns = !dag(ins, !foreach(arg, AddrAsmNames, VGPR_32), AddrAsmNames); 173 string AddrAsm = "[" # !foldl("$" # !head(AddrAsmNames), !tail(AddrAsmNames), lhs, rhs, 174 lhs # ", $" # rhs) # "]"; 175 176 int NSA = !if(!le(num_addrs, 1), ?, 177 !if(!le(num_addrs, 5), 1, 178 !if(!le(num_addrs, 9), 2, 179 !if(!le(num_addrs, 13), 3, ?)))); 180} 181 182// Base class of all pre-gfx10 MIMG instructions. 183class MIMG_gfx6789<bits<8> op, dag outs, string dns = ""> 184 : MIMG<outs, dns>, MIMGe_gfx6789<op> { 185 let SubtargetPredicate = isGFX6GFX7GFX8GFX9; 186 let AssemblerPredicate = isGFX6GFX7GFX8GFX9; 187 188 let MIMGEncoding = MIMGEncGfx6; 189 190 let d16 = !if(BaseOpcode.HasD16, ?, 0); 191} 192 193// Base class of all non-NSA gfx10 MIMG instructions. 194class MIMG_gfx10<int op, dag outs, string dns = ""> 195 : MIMG<outs, dns>, MIMGe_gfx10<op> { 196 let SubtargetPredicate = isGFX10Plus; 197 let AssemblerPredicate = isGFX10Plus; 198 199 let MIMGEncoding = MIMGEncGfx10Default; 200 201 let d16 = !if(BaseOpcode.HasD16, ?, 0); 202 let nsa = 0; 203} 204 205// Base class for all NSA MIMG instructions. Note that 1-dword addresses always 206// use non-NSA variants. 207class MIMG_nsa_gfx10<int op, dag outs, int num_addrs, string dns=""> 208 : MIMG<outs, dns>, MIMGe_gfx10<op> { 209 let SubtargetPredicate = isGFX10Plus; 210 let AssemblerPredicate = isGFX10Plus; 211 212 let MIMGEncoding = MIMGEncGfx10NSA; 213 214 MIMGNSAHelper nsah = MIMGNSAHelper<num_addrs>; 215 dag AddrIns = nsah.AddrIns; 216 string AddrAsm = nsah.AddrAsm; 217 218 let d16 = !if(BaseOpcode.HasD16, ?, 0); 219 let nsa = nsah.NSA; 220} 221 222class MIMG_NoSampler_Helper <bits<8> op, string asm, 223 RegisterClass dst_rc, 224 RegisterClass addr_rc, 225 string dns=""> 226 : MIMG_gfx6789 <op, (outs dst_rc:$vdata), dns> { 227 let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc, 228 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 229 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 230 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 231 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 232 #!if(BaseOpcode.HasD16, "$d16", ""); 233} 234 235class MIMG_NoSampler_gfx10<int op, string opcode, 236 RegisterClass DataRC, RegisterClass AddrRC, 237 string dns=""> 238 : MIMG_gfx10<op, (outs DataRC:$vdata), dns> { 239 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask, 240 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 241 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe), 242 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 243 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe" 244 #!if(BaseOpcode.HasD16, "$d16", ""); 245} 246 247class MIMG_NoSampler_nsa_gfx10<int op, string opcode, 248 RegisterClass DataRC, int num_addrs, 249 string dns=""> 250 : MIMG_nsa_gfx10<op, (outs DataRC:$vdata), num_addrs, dns> { 251 let InOperandList = !con(AddrIns, 252 (ins SReg_256:$srsrc, DMask:$dmask, 253 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 254 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe), 255 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 256 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe" 257 #!if(BaseOpcode.HasD16, "$d16", ""); 258} 259 260multiclass MIMG_NoSampler_Src_Helper <bits<8> op, string asm, 261 RegisterClass dst_rc, 262 bit enableDisasm> { 263 let ssamp = 0 in { 264 let VAddrDwords = 1 in { 265 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32, 266 !if(enableDisasm, "AMDGPU", "")>; 267 def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPR_32, 268 !if(enableDisasm, "AMDGPU", "")>; 269 } 270 271 let VAddrDwords = 2 in { 272 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>; 273 def _V2_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_64>; 274 def _V2_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 2>; 275 } 276 277 let VAddrDwords = 3 in { 278 def _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96>; 279 def _V3_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_96>; 280 def _V3_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 3>; 281 } 282 283 let VAddrDwords = 4 in { 284 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>; 285 def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_128>; 286 def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 4, 287 !if(enableDisasm, "AMDGPU", "")>; 288 } 289 } 290} 291 292multiclass MIMG_NoSampler <bits<8> op, string asm, bit has_d16, bit mip = 0, 293 bit isResInfo = 0> { 294 def "" : MIMGBaseOpcode { 295 let Coordinates = !if(isResInfo, 0, 1); 296 let LodOrClampOrMip = mip; 297 let HasD16 = has_d16; 298 } 299 300 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), 301 mayLoad = !if(isResInfo, 0, 1) in { 302 let VDataDwords = 1 in 303 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>; 304 let VDataDwords = 2 in 305 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 0>; 306 let VDataDwords = 3 in 307 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 0>; 308 let VDataDwords = 4 in 309 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 0>; 310 let VDataDwords = 5 in 311 defm _V5 : MIMG_NoSampler_Src_Helper <op, asm, VReg_160, 0>; 312 } 313} 314 315class MIMG_Store_Helper <bits<8> op, string asm, 316 RegisterClass data_rc, 317 RegisterClass addr_rc, 318 string dns = ""> 319 : MIMG_gfx6789<op, (outs), dns> { 320 let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 321 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 322 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 323 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 324 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 325 #!if(BaseOpcode.HasD16, "$d16", ""); 326} 327 328class MIMG_Store_gfx10<int op, string opcode, 329 RegisterClass DataRC, RegisterClass AddrRC, 330 string dns=""> 331 : MIMG_gfx10<op, (outs), dns> { 332 let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc, 333 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc, 334 GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe), 335 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 336 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe" 337 #!if(BaseOpcode.HasD16, "$d16", ""); 338} 339 340class MIMG_Store_nsa_gfx10<int op, string opcode, 341 RegisterClass DataRC, int num_addrs, 342 string dns=""> 343 : MIMG_nsa_gfx10<op, (outs), num_addrs, dns> { 344 let InOperandList = !con((ins DataRC:$vdata), 345 AddrIns, 346 (ins SReg_256:$srsrc, DMask:$dmask, 347 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 348 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe), 349 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 350 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe" 351 #!if(BaseOpcode.HasD16, "$d16", ""); 352} 353 354multiclass MIMG_Store_Addr_Helper <int op, string asm, 355 RegisterClass data_rc, 356 bit enableDisasm> { 357 let mayLoad = 0, mayStore = 1, hasSideEffects = 0, hasPostISelHook = 0, 358 DisableWQM = 1, ssamp = 0 in { 359 let VAddrDwords = 1 in { 360 def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32, 361 !if(enableDisasm, "AMDGPU", "")>; 362 def _V1_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VGPR_32, 363 !if(enableDisasm, "AMDGPU", "")>; 364 } 365 let VAddrDwords = 2 in { 366 def _V2 : MIMG_Store_Helper <op, asm, data_rc, VReg_64>; 367 def _V2_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_64>; 368 def _V2_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 2>; 369 } 370 let VAddrDwords = 3 in { 371 def _V3 : MIMG_Store_Helper <op, asm, data_rc, VReg_96>; 372 def _V3_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_96>; 373 def _V3_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 3>; 374 } 375 let VAddrDwords = 4 in { 376 def _V4 : MIMG_Store_Helper <op, asm, data_rc, VReg_128>; 377 def _V4_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_128>; 378 def _V4_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 4, 379 !if(enableDisasm, "AMDGPU", "")>; 380 } 381 } 382} 383 384multiclass MIMG_Store <bits<8> op, string asm, bit has_d16, bit mip = 0> { 385 def "" : MIMGBaseOpcode { 386 let Store = 1; 387 let LodOrClampOrMip = mip; 388 let HasD16 = has_d16; 389 } 390 391 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in { 392 let VDataDwords = 1 in 393 defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>; 394 let VDataDwords = 2 in 395 defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 0>; 396 let VDataDwords = 3 in 397 defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 0>; 398 let VDataDwords = 4 in 399 defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 0>; 400 } 401} 402 403class MIMG_Atomic_gfx6789_base <bits<8> op, string asm, RegisterClass data_rc, 404 RegisterClass addr_rc, string dns=""> 405 : MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> { 406 let Constraints = "$vdst = $vdata"; 407 let AsmMatchConverter = "cvtMIMGAtomic"; 408 409 let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 410 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 411 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da); 412 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"; 413} 414 415class MIMG_Atomic_si<mimg op, string asm, RegisterClass data_rc, 416 RegisterClass addr_rc, bit enableDasm = 0> 417 : MIMG_Atomic_gfx6789_base<op.SI_GFX10, asm, data_rc, addr_rc, 418 !if(enableDasm, "GFX6GFX7", "")> { 419 let AssemblerPredicate = isGFX6GFX7; 420} 421 422class MIMG_Atomic_vi<mimg op, string asm, RegisterClass data_rc, 423 RegisterClass addr_rc, bit enableDasm = 0> 424 : MIMG_Atomic_gfx6789_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX8", "")> { 425 let AssemblerPredicate = isGFX8GFX9; 426 let MIMGEncoding = MIMGEncGfx8; 427} 428 429class MIMG_Atomic_gfx10<mimg op, string opcode, 430 RegisterClass DataRC, RegisterClass AddrRC, 431 bit enableDisasm = 0> 432 : MIMG_gfx10<!cast<int>(op.SI_GFX10), (outs DataRC:$vdst), 433 !if(enableDisasm, "AMDGPU", "")> { 434 let Constraints = "$vdst = $vdata"; 435 let AsmMatchConverter = "cvtMIMGAtomic"; 436 437 let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc, 438 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc, 439 GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe); 440 let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"; 441} 442 443class MIMG_Atomic_nsa_gfx10<mimg op, string opcode, 444 RegisterClass DataRC, int num_addrs, 445 bit enableDisasm = 0> 446 : MIMG_nsa_gfx10<!cast<int>(op.SI_GFX10), (outs DataRC:$vdst), num_addrs, 447 !if(enableDisasm, "AMDGPU", "")> { 448 let Constraints = "$vdst = $vdata"; 449 let AsmMatchConverter = "cvtMIMGAtomic"; 450 451 let InOperandList = !con((ins DataRC:$vdata), 452 AddrIns, 453 (ins SReg_256:$srsrc, DMask:$dmask, 454 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 455 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe)); 456 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"; 457} 458 459multiclass MIMG_Atomic_Addr_Helper_m <mimg op, string asm, 460 RegisterClass data_rc, 461 bit enableDasm = 0> { 462 let hasSideEffects = 1, // FIXME: remove this 463 mayLoad = 1, mayStore = 1, hasPostISelHook = 0, DisableWQM = 1, 464 ssamp = 0 in { 465 let VAddrDwords = 1 in { 466 def _V1_si : MIMG_Atomic_si <op, asm, data_rc, VGPR_32, enableDasm>; 467 def _V1_vi : MIMG_Atomic_vi <op, asm, data_rc, VGPR_32, enableDasm>; 468 def _V1_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VGPR_32, enableDasm>; 469 } 470 let VAddrDwords = 2 in { 471 def _V2_si : MIMG_Atomic_si <op, asm, data_rc, VReg_64, 0>; 472 def _V2_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_64, 0>; 473 def _V2_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_64, 0>; 474 def _V2_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 2, 0>; 475 } 476 let VAddrDwords = 3 in { 477 def _V3_si : MIMG_Atomic_si <op, asm, data_rc, VReg_96, 0>; 478 def _V3_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_96, 0>; 479 def _V3_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_96, 0>; 480 def _V3_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 3, 0>; 481 } 482 let VAddrDwords = 4 in { 483 def _V4_si : MIMG_Atomic_si <op, asm, data_rc, VReg_128, 0>; 484 def _V4_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_128, 0>; 485 def _V4_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_128, 0>; 486 def _V4_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 4, enableDasm>; 487 } 488 } 489} 490 491multiclass MIMG_Atomic <mimg op, string asm, bit isCmpSwap = 0> { // 64-bit atomics 492 def "" : MIMGBaseOpcode { 493 let Atomic = 1; 494 let AtomicX2 = isCmpSwap; 495 } 496 497 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in { 498 // _V* variants have different dst size, but the size is encoded implicitly, 499 // using dmask and tfe. Only 32-bit variant is registered with disassembler. 500 // Other variants are reconstructed by disassembler using dmask and tfe. 501 let VDataDwords = !if(isCmpSwap, 2, 1) in 502 defm _V1 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_64, VGPR_32), 1>; 503 let VDataDwords = !if(isCmpSwap, 4, 2) in 504 defm _V2 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_128, VReg_64)>; 505 } 506} 507 508class MIMG_Sampler_Helper <bits<8> op, string asm, RegisterClass dst_rc, 509 RegisterClass src_rc, string dns=""> 510 : MIMG_gfx6789 <op, (outs dst_rc:$vdata), dns> { 511 let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, 512 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 513 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 514 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 515 let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da" 516 #!if(BaseOpcode.HasD16, "$d16", ""); 517} 518 519class MIMG_Sampler_gfx10<int op, string opcode, 520 RegisterClass DataRC, RegisterClass AddrRC, 521 string dns=""> 522 : MIMG_gfx10<op, (outs DataRC:$vdata), dns> { 523 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, SReg_128:$ssamp, 524 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc, 525 GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe), 526 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 527 let AsmString = opcode#" $vdata, $vaddr0, $srsrc, $ssamp$dmask$dim$unorm" 528 #"$dlc$glc$slc$r128$tfe$lwe" 529 #!if(BaseOpcode.HasD16, "$d16", ""); 530} 531 532class MIMG_Sampler_nsa_gfx10<int op, string opcode, 533 RegisterClass DataRC, int num_addrs, 534 string dns=""> 535 : MIMG_nsa_gfx10<op, (outs DataRC:$vdata), num_addrs, dns> { 536 let InOperandList = !con(AddrIns, 537 (ins SReg_256:$srsrc, SReg_128:$ssamp, DMask:$dmask, 538 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 539 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe), 540 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 541 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc, $ssamp$dmask$dim$unorm" 542 #"$dlc$glc$slc$r128$tfe$lwe" 543 #!if(BaseOpcode.HasD16, "$d16", ""); 544} 545 546class MIMGAddrSize<int dw, bit enable_disasm> { 547 int NumWords = dw; 548 549 RegisterClass RegClass = !if(!le(NumWords, 0), ?, 550 !if(!eq(NumWords, 1), VGPR_32, 551 !if(!eq(NumWords, 2), VReg_64, 552 !if(!eq(NumWords, 3), VReg_96, 553 !if(!eq(NumWords, 4), VReg_128, 554 !if(!le(NumWords, 8), VReg_256, 555 !if(!le(NumWords, 16), VReg_512, ?))))))); 556 557 // Whether the instruction variant with this vaddr size should be enabled for 558 // the auto-generated disassembler. 559 bit Disassemble = enable_disasm; 560} 561 562// Return whether x is in lst. 563class isIntInList<int x, list<int> lst> { 564 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !eq(x, y))); 565} 566 567// Return whether a value inside the range [min, max] (endpoints inclusive) 568// is in the given list. 569class isRangeInList<int min, int max, list<int> lst> { 570 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !and(!le(min, y), !le(y, max)))); 571} 572 573class MIMGAddrSizes_tmp<list<MIMGAddrSize> lst, int min> { 574 list<MIMGAddrSize> List = lst; 575 int Min = min; 576} 577 578class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> { 579 // List of all possible numbers of address words, taking all combinations of 580 // A16 and image dimension into account (note: no MSAA, since this is for 581 // sample/gather ops). 582 list<int> AllNumAddrWords = 583 !foreach(dw, !if(sample.Gradients, 584 !if(!eq(sample.LodOrClamp, ""), 585 [2, 3, 4, 5, 6, 7, 9], 586 [2, 3, 4, 5, 7, 8, 10]), 587 !if(!eq(sample.LodOrClamp, ""), 588 [1, 2, 3], 589 [1, 2, 3, 4])), 590 !add(dw, !size(sample.ExtraAddrArgs))); 591 592 // Generate machine instructions based on possible register classes for the 593 // required numbers of address words. The disassembler defaults to the 594 // smallest register class. 595 list<MIMGAddrSize> MachineInstrs = 596 !foldl(MIMGAddrSizes_tmp<[], 0>, [1, 2, 3, 4, 8, 16], lhs, dw, 597 !if(isRangeInList<lhs.Min, dw, AllNumAddrWords>.ret, 598 MIMGAddrSizes_tmp< 599 !listconcat(lhs.List, [MIMGAddrSize<dw, !empty(lhs.List)>]), 600 !if(!eq(dw, 3), 3, !add(dw, 1))>, // we still need _V4 for codegen w/ 3 dwords 601 lhs)).List; 602 603 // For NSA, generate machine instructions for all possible numbers of words 604 // except 1 (which is already covered by the non-NSA case). 605 // The disassembler defaults to the largest number of arguments among the 606 // variants with the same number of NSA words, and custom code then derives 607 // the exact variant based on the sample variant and the image dimension. 608 list<MIMGAddrSize> NSAInstrs = 609 !foldl([]<MIMGAddrSize>, [[12, 11, 10], [9, 8, 7, 6], [5, 4, 3, 2]], prev, nsa_group, 610 !listconcat(prev, 611 !foldl([]<MIMGAddrSize>, nsa_group, lhs, dw, 612 !if(isIntInList<dw, AllNumAddrWords>.ret, 613 !listconcat(lhs, [MIMGAddrSize<dw, !empty(lhs)>]), 614 lhs)))); 615} 616 617multiclass MIMG_Sampler_Src_Helper <bits<8> op, string asm, 618 AMDGPUSampleVariant sample, RegisterClass dst_rc, 619 bit enableDisasm = 0> { 620 foreach addr = MIMG_Sampler_AddrSizes<sample>.MachineInstrs in { 621 let VAddrDwords = addr.NumWords in { 622 def _V # addr.NumWords 623 : MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass, 624 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 625 def _V # addr.NumWords # _gfx10 626 : MIMG_Sampler_gfx10 <op, asm, dst_rc, addr.RegClass, 627 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 628 } 629 } 630 631 foreach addr = MIMG_Sampler_AddrSizes<sample>.NSAInstrs in { 632 let VAddrDwords = addr.NumWords in { 633 def _V # addr.NumWords # _nsa_gfx10 634 : MIMG_Sampler_nsa_gfx10<op, asm, dst_rc, addr.NumWords, 635 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 636 } 637 } 638} 639 640class MIMG_Sampler_BaseOpcode<AMDGPUSampleVariant sample> 641 : MIMGBaseOpcode { 642 let Sampler = 1; 643 let NumExtraArgs = !size(sample.ExtraAddrArgs); 644 let Gradients = sample.Gradients; 645 let LodOrClampOrMip = !ne(sample.LodOrClamp, ""); 646} 647 648multiclass MIMG_Sampler <bits<8> op, AMDGPUSampleVariant sample, bit wqm = 0, 649 bit isGetLod = 0, 650 string asm = "image_sample"#sample.LowerCaseMod> { 651 def "" : MIMG_Sampler_BaseOpcode<sample> { 652 let HasD16 = !if(isGetLod, 0, 1); 653 } 654 655 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm, 656 mayLoad = !if(isGetLod, 0, 1) in { 657 let VDataDwords = 1 in 658 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, sample, VGPR_32, 1>; 659 let VDataDwords = 2 in 660 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>; 661 let VDataDwords = 3 in 662 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_96>; 663 let VDataDwords = 4 in 664 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128>; 665 let VDataDwords = 5 in 666 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160>; 667 } 668} 669 670multiclass MIMG_Sampler_WQM <bits<8> op, AMDGPUSampleVariant sample> 671 : MIMG_Sampler<op, sample, 1>; 672 673multiclass MIMG_Gather <bits<8> op, AMDGPUSampleVariant sample, bit wqm = 0, 674 string asm = "image_gather4"#sample.LowerCaseMod> { 675 def "" : MIMG_Sampler_BaseOpcode<sample> { 676 let HasD16 = 1; 677 let Gather4 = 1; 678 } 679 680 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm, 681 Gather4 = 1, hasPostISelHook = 0 in { 682 let VDataDwords = 2 in 683 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>; /* for packed D16 only */ 684 let VDataDwords = 4 in 685 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 1>; 686 let VDataDwords = 5 in 687 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160>; 688 } 689} 690 691multiclass MIMG_Gather_WQM <bits<8> op, AMDGPUSampleVariant sample> 692 : MIMG_Gather<op, sample, 1>; 693 694//===----------------------------------------------------------------------===// 695// MIMG Instructions 696//===----------------------------------------------------------------------===// 697defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load", 1>; 698defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip", 1, 1>; 699defm IMAGE_LOAD_PCK : MIMG_NoSampler <0x00000002, "image_load_pck", 0>; 700defm IMAGE_LOAD_PCK_SGN : MIMG_NoSampler <0x00000003, "image_load_pck_sgn", 0>; 701defm IMAGE_LOAD_MIP_PCK : MIMG_NoSampler <0x00000004, "image_load_mip_pck", 0, 1>; 702defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoSampler <0x00000005, "image_load_mip_pck_sgn", 0, 1>; 703defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store", 1>; 704defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip", 1, 1>; 705defm IMAGE_STORE_PCK : MIMG_Store <0x0000000a, "image_store_pck", 0>; 706defm IMAGE_STORE_MIP_PCK : MIMG_Store <0x0000000b, "image_store_mip_pck", 0, 1>; 707 708defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo", 0, 1, 1>; 709 710defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimg<0x0f, 0x10>, "image_atomic_swap">; 711defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimg<0x10, 0x11>, "image_atomic_cmpswap", 1>; 712defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimg<0x11, 0x12>, "image_atomic_add">; 713defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimg<0x12, 0x13>, "image_atomic_sub">; 714//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; -- not on VI 715defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimg<0x14>, "image_atomic_smin">; 716defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimg<0x15>, "image_atomic_umin">; 717defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimg<0x16>, "image_atomic_smax">; 718defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimg<0x17>, "image_atomic_umax">; 719defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimg<0x18>, "image_atomic_and">; 720defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimg<0x19>, "image_atomic_or">; 721defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimg<0x1a>, "image_atomic_xor">; 722defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimg<0x1b>, "image_atomic_inc">; 723defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimg<0x1c>, "image_atomic_dec">; 724//let FPAtomic = 1 in { 725//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d, 1>; -- not on VI 726//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; -- not on VI 727//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; -- not on VI 728//} // End let FPAtomic = 1 729defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, AMDGPUSample>; 730defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, AMDGPUSample_cl>; 731defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, AMDGPUSample_d>; 732defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, AMDGPUSample_d_cl>; 733defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, AMDGPUSample_l>; 734defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, AMDGPUSample_b>; 735defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, AMDGPUSample_b_cl>; 736defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, AMDGPUSample_lz>; 737defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, AMDGPUSample_c>; 738defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, AMDGPUSample_c_cl>; 739defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, AMDGPUSample_c_d>; 740defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, AMDGPUSample_c_d_cl>; 741defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, AMDGPUSample_c_l>; 742defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, AMDGPUSample_c_b>; 743defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, AMDGPUSample_c_b_cl>; 744defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, AMDGPUSample_c_lz>; 745defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, AMDGPUSample_o>; 746defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, AMDGPUSample_cl_o>; 747defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, AMDGPUSample_d_o>; 748defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, AMDGPUSample_d_cl_o>; 749defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, AMDGPUSample_l_o>; 750defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, AMDGPUSample_b_o>; 751defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, AMDGPUSample_b_cl_o>; 752defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, AMDGPUSample_lz_o>; 753defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, AMDGPUSample_c_o>; 754defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, AMDGPUSample_c_cl_o>; 755defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, AMDGPUSample_c_d_o>; 756defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, AMDGPUSample_c_d_cl_o>; 757defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, AMDGPUSample_c_l_o>; 758defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, AMDGPUSample_c_b_cl_o>; 759defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, AMDGPUSample_c_b_o>; 760defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, AMDGPUSample_c_lz_o>; 761defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, AMDGPUSample>; 762defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, AMDGPUSample_cl>; 763defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, AMDGPUSample_l>; 764defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, AMDGPUSample_b>; 765defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, AMDGPUSample_b_cl>; 766defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, AMDGPUSample_lz>; 767defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, AMDGPUSample_c>; 768defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, AMDGPUSample_c_cl>; 769defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, AMDGPUSample_c_l>; 770defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, AMDGPUSample_c_b>; 771defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, AMDGPUSample_c_b_cl>; 772defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, AMDGPUSample_c_lz>; 773defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, AMDGPUSample_o>; 774defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, AMDGPUSample_cl_o>; 775defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, AMDGPUSample_l_o>; 776defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, AMDGPUSample_b_o>; 777defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, AMDGPUSample_b_cl_o>; 778defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, AMDGPUSample_lz_o>; 779defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, AMDGPUSample_c_o>; 780defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, AMDGPUSample_c_cl_o>; 781defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, AMDGPUSample_c_l_o>; 782defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, AMDGPUSample_c_b_o>; 783defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, AMDGPUSample_c_b_cl_o>; 784defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, AMDGPUSample_c_lz_o>; 785 786defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, AMDGPUSample, 1, 1, "image_get_lod">; 787 788defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, AMDGPUSample_cd>; 789defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, AMDGPUSample_cd_cl>; 790defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, AMDGPUSample_c_cd>; 791defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, AMDGPUSample_c_cd_cl>; 792defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, AMDGPUSample_cd_o>; 793defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, AMDGPUSample_cd_cl_o>; 794defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, AMDGPUSample_c_cd_o>; 795defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, AMDGPUSample_c_cd_cl_o>; 796//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>; 797//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>; 798 799/********** ========================================= **********/ 800/********** Table of dimension-aware image intrinsics **********/ 801/********** ========================================= **********/ 802 803class ImageDimIntrinsicInfo<AMDGPUImageDimIntrinsic I> { 804 Intrinsic Intr = I; 805 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(!strconcat("IMAGE_", I.P.OpMod)); 806 AMDGPUDimProps Dim = I.P.Dim; 807} 808 809def ImageDimIntrinsicTable : GenericTable { 810 let FilterClass = "ImageDimIntrinsicInfo"; 811 let Fields = ["Intr", "BaseOpcode", "Dim"]; 812 GenericEnum TypeOf_BaseOpcode = MIMGBaseOpcode; 813 GenericEnum TypeOf_Dim = MIMGDim; 814 815 let PrimaryKey = ["Intr"]; 816 let PrimaryKeyName = "getImageDimIntrinsicInfo"; 817 let PrimaryKeyEarlyOut = 1; 818} 819 820foreach intr = !listconcat(AMDGPUImageDimIntrinsics, 821 AMDGPUImageDimAtomicIntrinsics) in { 822 def : ImageDimIntrinsicInfo<intr>; 823} 824 825// L to LZ Optimization Mapping 826def : MIMGLZMapping<IMAGE_SAMPLE_L, IMAGE_SAMPLE_LZ>; 827def : MIMGLZMapping<IMAGE_SAMPLE_C_L, IMAGE_SAMPLE_C_LZ>; 828def : MIMGLZMapping<IMAGE_SAMPLE_L_O, IMAGE_SAMPLE_LZ_O>; 829def : MIMGLZMapping<IMAGE_SAMPLE_C_L_O, IMAGE_SAMPLE_C_LZ_O>; 830def : MIMGLZMapping<IMAGE_GATHER4_L, IMAGE_GATHER4_LZ>; 831def : MIMGLZMapping<IMAGE_GATHER4_C_L, IMAGE_GATHER4_C_LZ>; 832def : MIMGLZMapping<IMAGE_GATHER4_L_O, IMAGE_GATHER4_LZ_O>; 833def : MIMGLZMapping<IMAGE_GATHER4_C_L_O, IMAGE_GATHER4_C_LZ_O>; 834 835// MIP to NONMIP Optimization Mapping 836def : MIMGMIPMapping<IMAGE_LOAD_MIP, IMAGE_LOAD>; 837def : MIMGMIPMapping<IMAGE_STORE_MIP, IMAGE_STORE>; 838