1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPUPTNote.h" 15 #include "AMDKernelCodeT.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/MC/MCAssembler.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCELFStreamer.h" 23 #include "llvm/MC/MCSectionELF.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Support/AMDGPUMetadata.h" 26 #include "llvm/Support/AMDHSAKernelDescriptor.h" 27 #include "llvm/Support/Casting.h" 28 #include "llvm/Support/FormattedStream.h" 29 #include "llvm/TargetParser/TargetParser.h" 30 31 using namespace llvm; 32 using namespace llvm::AMDGPU; 33 34 //===----------------------------------------------------------------------===// 35 // AMDGPUTargetStreamer 36 //===----------------------------------------------------------------------===// 37 38 static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor, 39 uint32_t &Stepping, bool Sramecc, bool Xnack) { 40 if (Major == 9 && Minor == 0) { 41 switch (Stepping) { 42 case 0: 43 case 2: 44 case 4: 45 case 6: 46 if (Xnack) 47 Stepping++; 48 } 49 } 50 } 51 52 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 53 HSAMD::Metadata HSAMetadata; 54 if (HSAMD::fromString(HSAMetadataString, HSAMetadata)) 55 return false; 56 return EmitHSAMetadata(HSAMetadata); 57 } 58 59 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 60 msgpack::Document HSAMetadataDoc; 61 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 62 return false; 63 return EmitHSAMetadata(HSAMetadataDoc, false); 64 } 65 66 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 67 AMDGPU::GPUKind AK; 68 69 // clang-format off 70 switch (ElfMach) { 71 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 72 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 73 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 74 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 75 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 76 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 77 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 78 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 79 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 80 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 81 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 82 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 83 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 84 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 85 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 86 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break; 96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break; 100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 105 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break; 106 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 107 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: AK = GK_GFX90A; break; 108 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break; 109 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX940: AK = GK_GFX940; break; 110 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX941: AK = GK_GFX941; break; 111 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX942: AK = GK_GFX942; break; 112 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; 113 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; 114 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break; 115 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013: AK = GK_GFX1013; break; 116 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break; 117 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break; 118 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break; 119 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break; 120 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: AK = GK_GFX1034; break; 121 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035: AK = GK_GFX1035; break; 122 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036: AK = GK_GFX1036; break; 123 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100: AK = GK_GFX1100; break; 124 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101: AK = GK_GFX1101; break; 125 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102: AK = GK_GFX1102; break; 126 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103: AK = GK_GFX1103; break; 127 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1150: AK = GK_GFX1150; break; 128 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151: AK = GK_GFX1151; break; 129 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1200: AK = GK_GFX1200; break; 130 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1201: AK = GK_GFX1201; break; 131 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 132 default: AK = GK_NONE; break; 133 } 134 // clang-format on 135 136 StringRef GPUName = getArchNameAMDGCN(AK); 137 if (GPUName != "") 138 return GPUName; 139 return getArchNameR600(AK); 140 } 141 142 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 143 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 144 if (AK == AMDGPU::GPUKind::GK_NONE) 145 AK = parseArchR600(GPU); 146 147 // clang-format off 148 switch (AK) { 149 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 150 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 151 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 152 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 153 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 154 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 155 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 156 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 157 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 158 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 159 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 160 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 161 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 162 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 163 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 164 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 165 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 166 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 167 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602; 168 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 169 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 170 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 171 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 172 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 173 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705; 174 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 175 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 176 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 177 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805; 178 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 179 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 180 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 181 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 182 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 183 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908; 184 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 185 case GK_GFX90A: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A; 186 case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C; 187 case GK_GFX940: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX940; 188 case GK_GFX941: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX941; 189 case GK_GFX942: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX942; 190 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; 191 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; 192 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012; 193 case GK_GFX1013: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013; 194 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030; 195 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031; 196 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032; 197 case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033; 198 case GK_GFX1034: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034; 199 case GK_GFX1035: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035; 200 case GK_GFX1036: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036; 201 case GK_GFX1100: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100; 202 case GK_GFX1101: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101; 203 case GK_GFX1102: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102; 204 case GK_GFX1103: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103; 205 case GK_GFX1150: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1150; 206 case GK_GFX1151: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151; 207 case GK_GFX1200: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1200; 208 case GK_GFX1201: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1201; 209 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 210 } 211 // clang-format on 212 213 llvm_unreachable("unknown GPU"); 214 } 215 216 //===----------------------------------------------------------------------===// 217 // AMDGPUTargetAsmStreamer 218 //===----------------------------------------------------------------------===// 219 220 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 221 formatted_raw_ostream &OS) 222 : AMDGPUTargetStreamer(S), OS(OS) { } 223 224 // A hook for emitting stuff at the end. 225 // We use it for emitting the accumulated PAL metadata as directives. 226 // The PAL metadata is reset after it is emitted. 227 void AMDGPUTargetAsmStreamer::finish() { 228 std::string S; 229 getPALMetadata()->toString(S); 230 OS << S; 231 232 // Reset the pal metadata so its data will not affect a compilation that 233 // reuses this object. 234 getPALMetadata()->reset(); 235 } 236 237 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() { 238 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n"; 239 } 240 241 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 242 uint32_t Major, uint32_t Minor) { 243 OS << "\t.hsa_code_object_version " << 244 Twine(Major) << "," << Twine(Minor) << '\n'; 245 } 246 247 void 248 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 249 uint32_t Minor, 250 uint32_t Stepping, 251 StringRef VendorName, 252 StringRef ArchName) { 253 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 254 OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << "," 255 << Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 256 } 257 258 void 259 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 260 OS << "\t.amd_kernel_code_t\n"; 261 dumpAmdKernelCode(&Header, OS, "\t\t"); 262 OS << "\t.end_amd_kernel_code_t\n"; 263 } 264 265 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 266 unsigned Type) { 267 switch (Type) { 268 default: llvm_unreachable("Invalid AMDGPU symbol type"); 269 case ELF::STT_AMDGPU_HSA_KERNEL: 270 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 271 break; 272 } 273 } 274 275 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 276 Align Alignment) { 277 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", " 278 << Alignment.value() << '\n'; 279 } 280 281 bool AMDGPUTargetAsmStreamer::EmitISAVersion() { 282 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n"; 283 return true; 284 } 285 286 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 287 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 288 std::string HSAMetadataString; 289 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 290 return false; 291 292 OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n'; 293 OS << HSAMetadataString << '\n'; 294 OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n'; 295 return true; 296 } 297 298 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 299 msgpack::Document &HSAMetadataDoc, bool Strict) { 300 HSAMD::V3::MetadataVerifier Verifier(Strict); 301 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 302 return false; 303 304 std::string HSAMetadataString; 305 raw_string_ostream StrOS(HSAMetadataString); 306 HSAMetadataDoc.toYAML(StrOS); 307 308 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n'; 309 OS << StrOS.str() << '\n'; 310 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n'; 311 return true; 312 } 313 314 bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 315 const uint32_t Encoded_s_code_end = 0xbf9f0000; 316 const uint32_t Encoded_s_nop = 0xbf800000; 317 uint32_t Encoded_pad = Encoded_s_code_end; 318 319 // Instruction cache line size in bytes. 320 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6; 321 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 322 323 // Extra padding amount in bytes to support prefetch mode 3. 324 unsigned FillSize = 3 * CacheLineSize; 325 326 if (AMDGPU::isGFX90A(STI)) { 327 Encoded_pad = Encoded_s_nop; 328 FillSize = 16 * CacheLineSize; 329 } 330 331 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n'; 332 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n'; 333 return true; 334 } 335 336 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 337 const MCSubtargetInfo &STI, StringRef KernelName, 338 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 339 bool ReserveVCC, bool ReserveFlatScr, unsigned CodeObjectVersion) { 340 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 341 342 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 343 344 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 345 STREAM << "\t\t" << DIRECTIVE << " " \ 346 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 347 348 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 349 << '\n'; 350 OS << "\t\t.amdhsa_private_segment_fixed_size " 351 << KD.private_segment_fixed_size << '\n'; 352 OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n'; 353 354 PRINT_FIELD(OS, ".amdhsa_user_sgpr_count", KD, 355 compute_pgm_rsrc2, 356 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT); 357 358 if (!hasArchitectedFlatScratch(STI)) 359 PRINT_FIELD( 360 OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 361 kernel_code_properties, 362 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 363 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 364 kernel_code_properties, 365 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 366 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 367 kernel_code_properties, 368 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 369 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 370 kernel_code_properties, 371 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 372 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 373 kernel_code_properties, 374 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 375 if (!hasArchitectedFlatScratch(STI)) 376 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 377 kernel_code_properties, 378 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 379 if (hasKernargPreload(STI)) { 380 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_preload_length ", KD, 381 kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_LENGTH); 382 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_preload_offset ", KD, 383 kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_OFFSET); 384 } 385 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 386 kernel_code_properties, 387 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 388 if (IVersion.Major >= 10) 389 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD, 390 kernel_code_properties, 391 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 392 if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5) 393 PRINT_FIELD(OS, ".amdhsa_uses_dynamic_stack", KD, kernel_code_properties, 394 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 395 PRINT_FIELD(OS, 396 (hasArchitectedFlatScratch(STI) 397 ? ".amdhsa_enable_private_segment" 398 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"), 399 KD, compute_pgm_rsrc2, 400 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 401 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 402 compute_pgm_rsrc2, 403 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 404 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 405 compute_pgm_rsrc2, 406 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 407 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 408 compute_pgm_rsrc2, 409 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 410 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 411 compute_pgm_rsrc2, 412 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 413 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 414 compute_pgm_rsrc2, 415 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 416 417 // These directives are required. 418 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 419 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 420 421 if (AMDGPU::isGFX90A(STI)) 422 OS << "\t\t.amdhsa_accum_offset " << 423 (AMDHSA_BITS_GET(KD.compute_pgm_rsrc3, 424 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 425 << '\n'; 426 427 if (!ReserveVCC) 428 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 429 if (IVersion.Major >= 7 && !ReserveFlatScr && !hasArchitectedFlatScratch(STI)) 430 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 431 432 switch (CodeObjectVersion) { 433 default: 434 break; 435 case AMDGPU::AMDHSA_COV4: 436 case AMDGPU::AMDHSA_COV5: 437 if (getTargetID()->isXnackSupported()) 438 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n'; 439 break; 440 } 441 442 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 443 compute_pgm_rsrc1, 444 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 445 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 446 compute_pgm_rsrc1, 447 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 448 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 449 compute_pgm_rsrc1, 450 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 451 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 452 compute_pgm_rsrc1, 453 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 454 if (IVersion.Major < 12) { 455 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, compute_pgm_rsrc1, 456 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP); 457 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, compute_pgm_rsrc1, 458 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE); 459 } 460 if (IVersion.Major >= 9) 461 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 462 compute_pgm_rsrc1, 463 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL); 464 if (AMDGPU::isGFX90A(STI)) 465 PRINT_FIELD(OS, ".amdhsa_tg_split", KD, 466 compute_pgm_rsrc3, 467 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 468 if (IVersion.Major >= 10) { 469 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, 470 compute_pgm_rsrc1, 471 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE); 472 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, 473 compute_pgm_rsrc1, 474 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED); 475 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, 476 compute_pgm_rsrc1, 477 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS); 478 } 479 if (IVersion.Major >= 10 && IVersion.Major < 12) { 480 PRINT_FIELD(OS, ".amdhsa_shared_vgpr_count", KD, compute_pgm_rsrc3, 481 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 482 } 483 if (IVersion.Major >= 12) 484 PRINT_FIELD(OS, ".amdhsa_round_robin_scheduling", KD, compute_pgm_rsrc1, 485 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN); 486 PRINT_FIELD( 487 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 488 compute_pgm_rsrc2, 489 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 490 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 491 compute_pgm_rsrc2, 492 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 493 PRINT_FIELD( 494 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 495 compute_pgm_rsrc2, 496 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 497 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 498 compute_pgm_rsrc2, 499 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 500 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 501 compute_pgm_rsrc2, 502 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 503 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 504 compute_pgm_rsrc2, 505 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 506 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 507 compute_pgm_rsrc2, 508 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 509 #undef PRINT_FIELD 510 511 OS << "\t.end_amdhsa_kernel\n"; 512 } 513 514 //===----------------------------------------------------------------------===// 515 // AMDGPUTargetELFStreamer 516 //===----------------------------------------------------------------------===// 517 518 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S, 519 const MCSubtargetInfo &STI) 520 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {} 521 522 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 523 return static_cast<MCELFStreamer &>(Streamer); 524 } 525 526 // A hook for emitting stuff at the end. 527 // We use it for emitting the accumulated PAL metadata as a .note record. 528 // The PAL metadata is reset after it is emitted. 529 void AMDGPUTargetELFStreamer::finish() { 530 MCAssembler &MCA = getStreamer().getAssembler(); 531 MCA.setELFHeaderEFlags(getEFlags()); 532 533 std::string Blob; 534 const char *Vendor = getPALMetadata()->getVendor(); 535 unsigned Type = getPALMetadata()->getType(); 536 getPALMetadata()->toBlob(Type, Blob); 537 if (Blob.empty()) 538 return; 539 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 540 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); }); 541 542 // Reset the pal metadata so its data will not affect a compilation that 543 // reuses this object. 544 getPALMetadata()->reset(); 545 } 546 547 void AMDGPUTargetELFStreamer::EmitNote( 548 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 549 function_ref<void(MCELFStreamer &)> EmitDesc) { 550 auto &S = getStreamer(); 551 auto &Context = S.getContext(); 552 553 auto NameSZ = Name.size() + 1; 554 555 unsigned NoteFlags = 0; 556 // TODO Apparently, this is currently needed for OpenCL as mentioned in 557 // https://reviews.llvm.org/D74995 558 if (isHsaAbi(STI)) 559 NoteFlags = ELF::SHF_ALLOC; 560 561 S.pushSection(); 562 S.switchSection( 563 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags)); 564 S.emitInt32(NameSZ); // namesz 565 S.emitValue(DescSZ, 4); // descz 566 S.emitInt32(NoteType); // type 567 S.emitBytes(Name); // name 568 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0 569 EmitDesc(S); // desc 570 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0 571 S.popSection(); 572 } 573 574 unsigned AMDGPUTargetELFStreamer::getEFlags() { 575 switch (STI.getTargetTriple().getArch()) { 576 default: 577 llvm_unreachable("Unsupported Arch"); 578 case Triple::r600: 579 return getEFlagsR600(); 580 case Triple::amdgcn: 581 return getEFlagsAMDGCN(); 582 } 583 } 584 585 unsigned AMDGPUTargetELFStreamer::getEFlagsR600() { 586 assert(STI.getTargetTriple().getArch() == Triple::r600); 587 588 return getElfMach(STI.getCPU()); 589 } 590 591 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() { 592 assert(STI.getTargetTriple().getArch() == Triple::amdgcn); 593 594 switch (STI.getTargetTriple().getOS()) { 595 default: 596 // TODO: Why are some tests have "mingw" listed as OS? 597 // llvm_unreachable("Unsupported OS"); 598 case Triple::UnknownOS: 599 return getEFlagsUnknownOS(); 600 case Triple::AMDHSA: 601 return getEFlagsAMDHSA(); 602 case Triple::AMDPAL: 603 return getEFlagsAMDPAL(); 604 case Triple::Mesa3D: 605 return getEFlagsMesa3D(); 606 } 607 } 608 609 unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() { 610 // TODO: Why are some tests have "mingw" listed as OS? 611 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS); 612 613 return getEFlagsV3(); 614 } 615 616 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() { 617 assert(isHsaAbi(STI)); 618 619 if (std::optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) { 620 switch (*HsaAbiVer) { 621 case ELF::ELFABIVERSION_AMDGPU_HSA_V3: 622 return getEFlagsV3(); 623 case ELF::ELFABIVERSION_AMDGPU_HSA_V4: 624 case ELF::ELFABIVERSION_AMDGPU_HSA_V5: 625 return getEFlagsV4(); 626 } 627 } 628 629 llvm_unreachable("HSA OS ABI Version identification must be defined"); 630 } 631 632 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() { 633 assert(STI.getTargetTriple().getOS() == Triple::AMDPAL); 634 635 return getEFlagsV3(); 636 } 637 638 unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() { 639 assert(STI.getTargetTriple().getOS() == Triple::Mesa3D); 640 641 return getEFlagsV3(); 642 } 643 644 unsigned AMDGPUTargetELFStreamer::getEFlagsV3() { 645 unsigned EFlagsV3 = 0; 646 647 // mach. 648 EFlagsV3 |= getElfMach(STI.getCPU()); 649 650 // xnack. 651 if (getTargetID()->isXnackOnOrAny()) 652 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_XNACK_V3; 653 // sramecc. 654 if (getTargetID()->isSramEccOnOrAny()) 655 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_V3; 656 657 return EFlagsV3; 658 } 659 660 unsigned AMDGPUTargetELFStreamer::getEFlagsV4() { 661 unsigned EFlagsV4 = 0; 662 663 // mach. 664 EFlagsV4 |= getElfMach(STI.getCPU()); 665 666 // xnack. 667 switch (getTargetID()->getXnackSetting()) { 668 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 669 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4; 670 break; 671 case AMDGPU::IsaInfo::TargetIDSetting::Any: 672 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4; 673 break; 674 case AMDGPU::IsaInfo::TargetIDSetting::Off: 675 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4; 676 break; 677 case AMDGPU::IsaInfo::TargetIDSetting::On: 678 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4; 679 break; 680 } 681 // sramecc. 682 switch (getTargetID()->getSramEccSetting()) { 683 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 684 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4; 685 break; 686 case AMDGPU::IsaInfo::TargetIDSetting::Any: 687 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4; 688 break; 689 case AMDGPU::IsaInfo::TargetIDSetting::Off: 690 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4; 691 break; 692 case AMDGPU::IsaInfo::TargetIDSetting::On: 693 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4; 694 break; 695 } 696 697 return EFlagsV4; 698 } 699 700 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {} 701 702 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 703 uint32_t Major, uint32_t Minor) { 704 705 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 706 ELF::NT_AMD_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 707 OS.emitInt32(Major); 708 OS.emitInt32(Minor); 709 }); 710 } 711 712 void 713 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 714 uint32_t Minor, 715 uint32_t Stepping, 716 StringRef VendorName, 717 StringRef ArchName) { 718 uint16_t VendorNameSize = VendorName.size() + 1; 719 uint16_t ArchNameSize = ArchName.size() + 1; 720 721 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 722 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 723 VendorNameSize + ArchNameSize; 724 725 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 726 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 727 ELF::NT_AMD_HSA_ISA_VERSION, [&](MCELFStreamer &OS) { 728 OS.emitInt16(VendorNameSize); 729 OS.emitInt16(ArchNameSize); 730 OS.emitInt32(Major); 731 OS.emitInt32(Minor); 732 OS.emitInt32(Stepping); 733 OS.emitBytes(VendorName); 734 OS.emitInt8(0); // NULL terminate VendorName 735 OS.emitBytes(ArchName); 736 OS.emitInt8(0); // NULL terminate ArchName 737 }); 738 } 739 740 void 741 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 742 743 MCStreamer &OS = getStreamer(); 744 OS.pushSection(); 745 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header))); 746 OS.popSection(); 747 } 748 749 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 750 unsigned Type) { 751 MCSymbolELF *Symbol = cast<MCSymbolELF>( 752 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 753 Symbol->setType(Type); 754 } 755 756 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 757 Align Alignment) { 758 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol); 759 SymbolELF->setType(ELF::STT_OBJECT); 760 761 if (!SymbolELF->isBindingSet()) { 762 SymbolELF->setBinding(ELF::STB_GLOBAL); 763 SymbolELF->setExternal(true); 764 } 765 766 if (SymbolELF->declareCommon(Size, Alignment, true)) { 767 report_fatal_error("Symbol: " + Symbol->getName() + 768 " redeclared as different type"); 769 } 770 771 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS); 772 SymbolELF->setSize(MCConstantExpr::create(Size, getContext())); 773 } 774 775 bool AMDGPUTargetELFStreamer::EmitISAVersion() { 776 // Create two labels to mark the beginning and end of the desc field 777 // and a MCExpr to calculate the size of the desc field. 778 auto &Context = getContext(); 779 auto *DescBegin = Context.createTempSymbol(); 780 auto *DescEnd = Context.createTempSymbol(); 781 auto *DescSZ = MCBinaryExpr::createSub( 782 MCSymbolRefExpr::create(DescEnd, Context), 783 MCSymbolRefExpr::create(DescBegin, Context), Context); 784 785 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME, 786 [&](MCELFStreamer &OS) { 787 OS.emitLabel(DescBegin); 788 OS.emitBytes(getTargetID()->toString()); 789 OS.emitLabel(DescEnd); 790 }); 791 return true; 792 } 793 794 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 795 bool Strict) { 796 HSAMD::V3::MetadataVerifier Verifier(Strict); 797 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 798 return false; 799 800 std::string HSAMetadataString; 801 HSAMetadataDoc.writeToBlob(HSAMetadataString); 802 803 // Create two labels to mark the beginning and end of the desc field 804 // and a MCExpr to calculate the size of the desc field. 805 auto &Context = getContext(); 806 auto *DescBegin = Context.createTempSymbol(); 807 auto *DescEnd = Context.createTempSymbol(); 808 auto *DescSZ = MCBinaryExpr::createSub( 809 MCSymbolRefExpr::create(DescEnd, Context), 810 MCSymbolRefExpr::create(DescBegin, Context), Context); 811 812 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 813 [&](MCELFStreamer &OS) { 814 OS.emitLabel(DescBegin); 815 OS.emitBytes(HSAMetadataString); 816 OS.emitLabel(DescEnd); 817 }); 818 return true; 819 } 820 821 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 822 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 823 std::string HSAMetadataString; 824 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 825 return false; 826 827 // Create two labels to mark the beginning and end of the desc field 828 // and a MCExpr to calculate the size of the desc field. 829 auto &Context = getContext(); 830 auto *DescBegin = Context.createTempSymbol(); 831 auto *DescEnd = Context.createTempSymbol(); 832 auto *DescSZ = MCBinaryExpr::createSub( 833 MCSymbolRefExpr::create(DescEnd, Context), 834 MCSymbolRefExpr::create(DescBegin, Context), Context); 835 836 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_METADATA, 837 [&](MCELFStreamer &OS) { 838 OS.emitLabel(DescBegin); 839 OS.emitBytes(HSAMetadataString); 840 OS.emitLabel(DescEnd); 841 }); 842 return true; 843 } 844 845 bool AMDGPUTargetAsmStreamer::EmitKernargPreloadHeader( 846 const MCSubtargetInfo &STI) { 847 for (int i = 0; i < 64; ++i) { 848 OS << "\ts_nop 0\n"; 849 } 850 return true; 851 } 852 853 bool AMDGPUTargetELFStreamer::EmitKernargPreloadHeader( 854 const MCSubtargetInfo &STI) { 855 const uint32_t Encoded_s_nop = 0xbf800000; 856 MCStreamer &OS = getStreamer(); 857 for (int i = 0; i < 64; ++i) { 858 OS.emitInt32(Encoded_s_nop); 859 } 860 return true; 861 } 862 863 bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 864 const uint32_t Encoded_s_code_end = 0xbf9f0000; 865 const uint32_t Encoded_s_nop = 0xbf800000; 866 uint32_t Encoded_pad = Encoded_s_code_end; 867 868 // Instruction cache line size in bytes. 869 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6; 870 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 871 872 // Extra padding amount in bytes to support prefetch mode 3. 873 unsigned FillSize = 3 * CacheLineSize; 874 875 if (AMDGPU::isGFX90A(STI)) { 876 Encoded_pad = Encoded_s_nop; 877 FillSize = 16 * CacheLineSize; 878 } 879 880 MCStreamer &OS = getStreamer(); 881 OS.pushSection(); 882 OS.emitValueToAlignment(Align(CacheLineSize), Encoded_pad, 4); 883 for (unsigned I = 0; I < FillSize; I += 4) 884 OS.emitInt32(Encoded_pad); 885 OS.popSection(); 886 return true; 887 } 888 889 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 890 const MCSubtargetInfo &STI, StringRef KernelName, 891 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 892 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, 893 unsigned CodeObjectVersion) { 894 auto &Streamer = getStreamer(); 895 auto &Context = Streamer.getContext(); 896 897 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 898 Context.getOrCreateSymbol(Twine(KernelName))); 899 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 900 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 901 902 // Copy kernel descriptor symbol's binding, other and visibility from the 903 // kernel code symbol. 904 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 905 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 906 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 907 // Kernel descriptor symbol's type and size are fixed. 908 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 909 KernelDescriptorSymbol->setSize( 910 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 911 912 // The visibility of the kernel code symbol must be protected or less to allow 913 // static relocations from the kernel descriptor to be used. 914 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 915 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 916 917 Streamer.emitLabel(KernelDescriptorSymbol); 918 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size); 919 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size); 920 Streamer.emitInt32(KernelDescriptor.kernarg_size); 921 922 for (uint8_t Res : KernelDescriptor.reserved0) 923 Streamer.emitInt8(Res); 924 925 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 926 // expression being created is: 927 // (start of kernel code) - (start of kernel descriptor) 928 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 929 Streamer.emitValue(MCBinaryExpr::createSub( 930 MCSymbolRefExpr::create( 931 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 932 MCSymbolRefExpr::create( 933 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 934 Context), 935 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 936 for (uint8_t Res : KernelDescriptor.reserved1) 937 Streamer.emitInt8(Res); 938 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3); 939 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1); 940 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2); 941 Streamer.emitInt16(KernelDescriptor.kernel_code_properties); 942 Streamer.emitInt16(KernelDescriptor.kernarg_preload); 943 for (uint8_t Res : KernelDescriptor.reserved3) 944 Streamer.emitInt8(Res); 945 } 946