1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPUPTNote.h" 15 #include "AMDKernelCodeT.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/MC/MCAssembler.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCELFStreamer.h" 23 #include "llvm/MC/MCSectionELF.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Support/AMDGPUMetadata.h" 26 #include "llvm/Support/AMDHSAKernelDescriptor.h" 27 #include "llvm/Support/Casting.h" 28 #include "llvm/Support/FormattedStream.h" 29 #include "llvm/TargetParser/TargetParser.h" 30 31 using namespace llvm; 32 using namespace llvm::AMDGPU; 33 34 //===----------------------------------------------------------------------===// 35 // AMDGPUTargetStreamer 36 //===----------------------------------------------------------------------===// 37 38 static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor, 39 uint32_t &Stepping, bool Sramecc, bool Xnack) { 40 if (Major == 9 && Minor == 0) { 41 switch (Stepping) { 42 case 0: 43 case 2: 44 case 4: 45 case 6: 46 if (Xnack) 47 Stepping++; 48 } 49 } 50 } 51 52 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 53 HSAMD::Metadata HSAMetadata; 54 if (HSAMD::fromString(HSAMetadataString, HSAMetadata)) 55 return false; 56 return EmitHSAMetadata(HSAMetadata); 57 } 58 59 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 60 msgpack::Document HSAMetadataDoc; 61 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 62 return false; 63 return EmitHSAMetadata(HSAMetadataDoc, false); 64 } 65 66 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 67 AMDGPU::GPUKind AK; 68 69 switch (ElfMach) { 70 default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type"); 71 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 72 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 73 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 74 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 75 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 76 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 77 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 78 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 79 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 80 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 81 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 82 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 83 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 84 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 85 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 86 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break; 96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break; 100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 105 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break; 106 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 107 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: AK = GK_GFX90A; break; 108 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break; 109 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX940: AK = GK_GFX940; break; 110 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX941: AK = GK_GFX941; break; 111 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX942: AK = GK_GFX942; break; 112 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; 113 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; 114 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break; 115 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013: AK = GK_GFX1013; break; 116 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break; 117 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break; 118 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break; 119 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break; 120 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: AK = GK_GFX1034; break; 121 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035: AK = GK_GFX1035; break; 122 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036: AK = GK_GFX1036; break; 123 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100: AK = GK_GFX1100; break; 124 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101: AK = GK_GFX1101; break; 125 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102: AK = GK_GFX1102; break; 126 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103: AK = GK_GFX1103; break; 127 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1150: AK = GK_GFX1150; break; 128 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151: AK = GK_GFX1151; break; 129 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 130 } 131 132 StringRef GPUName = getArchNameAMDGCN(AK); 133 if (GPUName != "") 134 return GPUName; 135 return getArchNameR600(AK); 136 } 137 138 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 139 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 140 if (AK == AMDGPU::GPUKind::GK_NONE) 141 AK = parseArchR600(GPU); 142 143 switch (AK) { 144 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 145 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 146 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 147 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 148 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 149 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 150 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 151 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 152 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 153 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 154 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 155 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 156 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 157 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 158 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 159 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 160 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 161 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 162 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602; 163 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 164 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 165 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 166 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 167 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 168 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705; 169 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 170 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 171 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 172 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805; 173 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 174 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 175 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 176 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 177 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 178 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908; 179 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 180 case GK_GFX90A: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A; 181 case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C; 182 case GK_GFX940: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX940; 183 case GK_GFX941: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX941; 184 case GK_GFX942: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX942; 185 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; 186 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; 187 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012; 188 case GK_GFX1013: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013; 189 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030; 190 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031; 191 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032; 192 case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033; 193 case GK_GFX1034: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034; 194 case GK_GFX1035: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035; 195 case GK_GFX1036: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036; 196 case GK_GFX1100: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100; 197 case GK_GFX1101: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101; 198 case GK_GFX1102: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102; 199 case GK_GFX1103: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103; 200 case GK_GFX1150: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1150; 201 case GK_GFX1151: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151; 202 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 203 } 204 205 llvm_unreachable("unknown GPU"); 206 } 207 208 //===----------------------------------------------------------------------===// 209 // AMDGPUTargetAsmStreamer 210 //===----------------------------------------------------------------------===// 211 212 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 213 formatted_raw_ostream &OS) 214 : AMDGPUTargetStreamer(S), OS(OS) { } 215 216 // A hook for emitting stuff at the end. 217 // We use it for emitting the accumulated PAL metadata as directives. 218 // The PAL metadata is reset after it is emitted. 219 void AMDGPUTargetAsmStreamer::finish() { 220 std::string S; 221 getPALMetadata()->toString(S); 222 OS << S; 223 224 // Reset the pal metadata so its data will not affect a compilation that 225 // reuses this object. 226 getPALMetadata()->reset(); 227 } 228 229 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() { 230 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n"; 231 } 232 233 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 234 uint32_t Major, uint32_t Minor) { 235 OS << "\t.hsa_code_object_version " << 236 Twine(Major) << "," << Twine(Minor) << '\n'; 237 } 238 239 void 240 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 241 uint32_t Minor, 242 uint32_t Stepping, 243 StringRef VendorName, 244 StringRef ArchName) { 245 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 246 OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << "," 247 << Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 248 } 249 250 void 251 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 252 OS << "\t.amd_kernel_code_t\n"; 253 dumpAmdKernelCode(&Header, OS, "\t\t"); 254 OS << "\t.end_amd_kernel_code_t\n"; 255 } 256 257 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 258 unsigned Type) { 259 switch (Type) { 260 default: llvm_unreachable("Invalid AMDGPU symbol type"); 261 case ELF::STT_AMDGPU_HSA_KERNEL: 262 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 263 break; 264 } 265 } 266 267 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 268 Align Alignment) { 269 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", " 270 << Alignment.value() << '\n'; 271 } 272 273 bool AMDGPUTargetAsmStreamer::EmitISAVersion() { 274 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n"; 275 return true; 276 } 277 278 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 279 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 280 std::string HSAMetadataString; 281 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 282 return false; 283 284 OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n'; 285 OS << HSAMetadataString << '\n'; 286 OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n'; 287 return true; 288 } 289 290 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 291 msgpack::Document &HSAMetadataDoc, bool Strict) { 292 HSAMD::V3::MetadataVerifier Verifier(Strict); 293 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 294 return false; 295 296 std::string HSAMetadataString; 297 raw_string_ostream StrOS(HSAMetadataString); 298 HSAMetadataDoc.toYAML(StrOS); 299 300 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n'; 301 OS << StrOS.str() << '\n'; 302 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n'; 303 return true; 304 } 305 306 bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 307 const uint32_t Encoded_s_code_end = 0xbf9f0000; 308 const uint32_t Encoded_s_nop = 0xbf800000; 309 uint32_t Encoded_pad = Encoded_s_code_end; 310 311 // Instruction cache line size in bytes. 312 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6; 313 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 314 315 // Extra padding amount in bytes to support prefetch mode 3. 316 unsigned FillSize = 3 * CacheLineSize; 317 318 if (AMDGPU::isGFX90A(STI)) { 319 Encoded_pad = Encoded_s_nop; 320 FillSize = 16 * CacheLineSize; 321 } 322 323 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n'; 324 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n'; 325 return true; 326 } 327 328 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 329 const MCSubtargetInfo &STI, StringRef KernelName, 330 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 331 bool ReserveVCC, bool ReserveFlatScr, unsigned CodeObjectVersion) { 332 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 333 334 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 335 336 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 337 STREAM << "\t\t" << DIRECTIVE << " " \ 338 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 339 340 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 341 << '\n'; 342 OS << "\t\t.amdhsa_private_segment_fixed_size " 343 << KD.private_segment_fixed_size << '\n'; 344 OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n'; 345 346 PRINT_FIELD(OS, ".amdhsa_user_sgpr_count", KD, 347 compute_pgm_rsrc2, 348 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT); 349 350 if (!hasArchitectedFlatScratch(STI)) 351 PRINT_FIELD( 352 OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 353 kernel_code_properties, 354 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 355 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 356 kernel_code_properties, 357 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 358 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 359 kernel_code_properties, 360 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 361 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 362 kernel_code_properties, 363 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 364 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 365 kernel_code_properties, 366 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 367 if (!hasArchitectedFlatScratch(STI)) 368 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 369 kernel_code_properties, 370 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 371 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 372 kernel_code_properties, 373 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 374 if (IVersion.Major >= 10) 375 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD, 376 kernel_code_properties, 377 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 378 if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5) 379 PRINT_FIELD(OS, ".amdhsa_uses_dynamic_stack", KD, kernel_code_properties, 380 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 381 PRINT_FIELD(OS, 382 (hasArchitectedFlatScratch(STI) 383 ? ".amdhsa_enable_private_segment" 384 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"), 385 KD, compute_pgm_rsrc2, 386 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 387 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 388 compute_pgm_rsrc2, 389 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 390 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 391 compute_pgm_rsrc2, 392 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 393 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 394 compute_pgm_rsrc2, 395 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 396 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 397 compute_pgm_rsrc2, 398 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 399 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 400 compute_pgm_rsrc2, 401 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 402 403 // These directives are required. 404 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 405 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 406 407 if (AMDGPU::isGFX90A(STI)) 408 OS << "\t\t.amdhsa_accum_offset " << 409 (AMDHSA_BITS_GET(KD.compute_pgm_rsrc3, 410 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 411 << '\n'; 412 413 if (!ReserveVCC) 414 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 415 if (IVersion.Major >= 7 && !ReserveFlatScr && !hasArchitectedFlatScratch(STI)) 416 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 417 418 switch (CodeObjectVersion) { 419 default: 420 break; 421 case AMDGPU::AMDHSA_COV2: 422 break; 423 case AMDGPU::AMDHSA_COV3: 424 case AMDGPU::AMDHSA_COV4: 425 case AMDGPU::AMDHSA_COV5: 426 if (getTargetID()->isXnackSupported()) 427 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n'; 428 break; 429 } 430 431 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 432 compute_pgm_rsrc1, 433 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 434 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 435 compute_pgm_rsrc1, 436 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 437 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 438 compute_pgm_rsrc1, 439 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 440 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 441 compute_pgm_rsrc1, 442 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 443 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 444 compute_pgm_rsrc1, 445 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 446 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 447 compute_pgm_rsrc1, 448 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 449 if (IVersion.Major >= 9) 450 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 451 compute_pgm_rsrc1, 452 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 453 if (AMDGPU::isGFX90A(STI)) 454 PRINT_FIELD(OS, ".amdhsa_tg_split", KD, 455 compute_pgm_rsrc3, 456 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 457 if (IVersion.Major >= 10) { 458 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, 459 compute_pgm_rsrc1, 460 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE); 461 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, 462 compute_pgm_rsrc1, 463 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED); 464 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, 465 compute_pgm_rsrc1, 466 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS); 467 PRINT_FIELD(OS, ".amdhsa_shared_vgpr_count", KD, compute_pgm_rsrc3, 468 amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT); 469 } 470 PRINT_FIELD( 471 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 472 compute_pgm_rsrc2, 473 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 474 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 475 compute_pgm_rsrc2, 476 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 477 PRINT_FIELD( 478 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 479 compute_pgm_rsrc2, 480 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 481 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 482 compute_pgm_rsrc2, 483 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 484 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 485 compute_pgm_rsrc2, 486 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 487 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 488 compute_pgm_rsrc2, 489 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 490 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 491 compute_pgm_rsrc2, 492 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 493 #undef PRINT_FIELD 494 495 OS << "\t.end_amdhsa_kernel\n"; 496 } 497 498 //===----------------------------------------------------------------------===// 499 // AMDGPUTargetELFStreamer 500 //===----------------------------------------------------------------------===// 501 502 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S, 503 const MCSubtargetInfo &STI) 504 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {} 505 506 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 507 return static_cast<MCELFStreamer &>(Streamer); 508 } 509 510 // A hook for emitting stuff at the end. 511 // We use it for emitting the accumulated PAL metadata as a .note record. 512 // The PAL metadata is reset after it is emitted. 513 void AMDGPUTargetELFStreamer::finish() { 514 MCAssembler &MCA = getStreamer().getAssembler(); 515 MCA.setELFHeaderEFlags(getEFlags()); 516 517 std::string Blob; 518 const char *Vendor = getPALMetadata()->getVendor(); 519 unsigned Type = getPALMetadata()->getType(); 520 getPALMetadata()->toBlob(Type, Blob); 521 if (Blob.empty()) 522 return; 523 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 524 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); }); 525 526 // Reset the pal metadata so its data will not affect a compilation that 527 // reuses this object. 528 getPALMetadata()->reset(); 529 } 530 531 void AMDGPUTargetELFStreamer::EmitNote( 532 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 533 function_ref<void(MCELFStreamer &)> EmitDesc) { 534 auto &S = getStreamer(); 535 auto &Context = S.getContext(); 536 537 auto NameSZ = Name.size() + 1; 538 539 unsigned NoteFlags = 0; 540 // TODO Apparently, this is currently needed for OpenCL as mentioned in 541 // https://reviews.llvm.org/D74995 542 if (STI.getTargetTriple().getOS() == Triple::AMDHSA) 543 NoteFlags = ELF::SHF_ALLOC; 544 545 S.pushSection(); 546 S.switchSection( 547 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags)); 548 S.emitInt32(NameSZ); // namesz 549 S.emitValue(DescSZ, 4); // descz 550 S.emitInt32(NoteType); // type 551 S.emitBytes(Name); // name 552 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0 553 EmitDesc(S); // desc 554 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0 555 S.popSection(); 556 } 557 558 unsigned AMDGPUTargetELFStreamer::getEFlags() { 559 switch (STI.getTargetTriple().getArch()) { 560 default: 561 llvm_unreachable("Unsupported Arch"); 562 case Triple::r600: 563 return getEFlagsR600(); 564 case Triple::amdgcn: 565 return getEFlagsAMDGCN(); 566 } 567 } 568 569 unsigned AMDGPUTargetELFStreamer::getEFlagsR600() { 570 assert(STI.getTargetTriple().getArch() == Triple::r600); 571 572 return getElfMach(STI.getCPU()); 573 } 574 575 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() { 576 assert(STI.getTargetTriple().getArch() == Triple::amdgcn); 577 578 switch (STI.getTargetTriple().getOS()) { 579 default: 580 // TODO: Why are some tests have "mingw" listed as OS? 581 // llvm_unreachable("Unsupported OS"); 582 case Triple::UnknownOS: 583 return getEFlagsUnknownOS(); 584 case Triple::AMDHSA: 585 return getEFlagsAMDHSA(); 586 case Triple::AMDPAL: 587 return getEFlagsAMDPAL(); 588 case Triple::Mesa3D: 589 return getEFlagsMesa3D(); 590 } 591 } 592 593 unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() { 594 // TODO: Why are some tests have "mingw" listed as OS? 595 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS); 596 597 return getEFlagsV3(); 598 } 599 600 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() { 601 assert(STI.getTargetTriple().getOS() == Triple::AMDHSA); 602 603 if (std::optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) { 604 switch (*HsaAbiVer) { 605 case ELF::ELFABIVERSION_AMDGPU_HSA_V2: 606 case ELF::ELFABIVERSION_AMDGPU_HSA_V3: 607 return getEFlagsV3(); 608 case ELF::ELFABIVERSION_AMDGPU_HSA_V4: 609 case ELF::ELFABIVERSION_AMDGPU_HSA_V5: 610 return getEFlagsV4(); 611 } 612 } 613 614 llvm_unreachable("HSA OS ABI Version identification must be defined"); 615 } 616 617 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() { 618 assert(STI.getTargetTriple().getOS() == Triple::AMDPAL); 619 620 return getEFlagsV3(); 621 } 622 623 unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() { 624 assert(STI.getTargetTriple().getOS() == Triple::Mesa3D); 625 626 return getEFlagsV3(); 627 } 628 629 unsigned AMDGPUTargetELFStreamer::getEFlagsV3() { 630 unsigned EFlagsV3 = 0; 631 632 // mach. 633 EFlagsV3 |= getElfMach(STI.getCPU()); 634 635 // xnack. 636 if (getTargetID()->isXnackOnOrAny()) 637 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_XNACK_V3; 638 // sramecc. 639 if (getTargetID()->isSramEccOnOrAny()) 640 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_V3; 641 642 return EFlagsV3; 643 } 644 645 unsigned AMDGPUTargetELFStreamer::getEFlagsV4() { 646 unsigned EFlagsV4 = 0; 647 648 // mach. 649 EFlagsV4 |= getElfMach(STI.getCPU()); 650 651 // xnack. 652 switch (getTargetID()->getXnackSetting()) { 653 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 654 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4; 655 break; 656 case AMDGPU::IsaInfo::TargetIDSetting::Any: 657 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4; 658 break; 659 case AMDGPU::IsaInfo::TargetIDSetting::Off: 660 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4; 661 break; 662 case AMDGPU::IsaInfo::TargetIDSetting::On: 663 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4; 664 break; 665 } 666 // sramecc. 667 switch (getTargetID()->getSramEccSetting()) { 668 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 669 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4; 670 break; 671 case AMDGPU::IsaInfo::TargetIDSetting::Any: 672 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4; 673 break; 674 case AMDGPU::IsaInfo::TargetIDSetting::Off: 675 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4; 676 break; 677 case AMDGPU::IsaInfo::TargetIDSetting::On: 678 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4; 679 break; 680 } 681 682 return EFlagsV4; 683 } 684 685 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {} 686 687 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 688 uint32_t Major, uint32_t Minor) { 689 690 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 691 ELF::NT_AMD_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 692 OS.emitInt32(Major); 693 OS.emitInt32(Minor); 694 }); 695 } 696 697 void 698 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 699 uint32_t Minor, 700 uint32_t Stepping, 701 StringRef VendorName, 702 StringRef ArchName) { 703 uint16_t VendorNameSize = VendorName.size() + 1; 704 uint16_t ArchNameSize = ArchName.size() + 1; 705 706 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 707 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 708 VendorNameSize + ArchNameSize; 709 710 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 711 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 712 ELF::NT_AMD_HSA_ISA_VERSION, [&](MCELFStreamer &OS) { 713 OS.emitInt16(VendorNameSize); 714 OS.emitInt16(ArchNameSize); 715 OS.emitInt32(Major); 716 OS.emitInt32(Minor); 717 OS.emitInt32(Stepping); 718 OS.emitBytes(VendorName); 719 OS.emitInt8(0); // NULL terminate VendorName 720 OS.emitBytes(ArchName); 721 OS.emitInt8(0); // NULL terminate ArchName 722 }); 723 } 724 725 void 726 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 727 728 MCStreamer &OS = getStreamer(); 729 OS.pushSection(); 730 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header))); 731 OS.popSection(); 732 } 733 734 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 735 unsigned Type) { 736 MCSymbolELF *Symbol = cast<MCSymbolELF>( 737 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 738 Symbol->setType(Type); 739 } 740 741 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 742 Align Alignment) { 743 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol); 744 SymbolELF->setType(ELF::STT_OBJECT); 745 746 if (!SymbolELF->isBindingSet()) { 747 SymbolELF->setBinding(ELF::STB_GLOBAL); 748 SymbolELF->setExternal(true); 749 } 750 751 if (SymbolELF->declareCommon(Size, Alignment, true)) { 752 report_fatal_error("Symbol: " + Symbol->getName() + 753 " redeclared as different type"); 754 } 755 756 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS); 757 SymbolELF->setSize(MCConstantExpr::create(Size, getContext())); 758 } 759 760 bool AMDGPUTargetELFStreamer::EmitISAVersion() { 761 // Create two labels to mark the beginning and end of the desc field 762 // and a MCExpr to calculate the size of the desc field. 763 auto &Context = getContext(); 764 auto *DescBegin = Context.createTempSymbol(); 765 auto *DescEnd = Context.createTempSymbol(); 766 auto *DescSZ = MCBinaryExpr::createSub( 767 MCSymbolRefExpr::create(DescEnd, Context), 768 MCSymbolRefExpr::create(DescBegin, Context), Context); 769 770 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME, 771 [&](MCELFStreamer &OS) { 772 OS.emitLabel(DescBegin); 773 OS.emitBytes(getTargetID()->toString()); 774 OS.emitLabel(DescEnd); 775 }); 776 return true; 777 } 778 779 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 780 bool Strict) { 781 HSAMD::V3::MetadataVerifier Verifier(Strict); 782 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 783 return false; 784 785 std::string HSAMetadataString; 786 HSAMetadataDoc.writeToBlob(HSAMetadataString); 787 788 // Create two labels to mark the beginning and end of the desc field 789 // and a MCExpr to calculate the size of the desc field. 790 auto &Context = getContext(); 791 auto *DescBegin = Context.createTempSymbol(); 792 auto *DescEnd = Context.createTempSymbol(); 793 auto *DescSZ = MCBinaryExpr::createSub( 794 MCSymbolRefExpr::create(DescEnd, Context), 795 MCSymbolRefExpr::create(DescBegin, Context), Context); 796 797 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 798 [&](MCELFStreamer &OS) { 799 OS.emitLabel(DescBegin); 800 OS.emitBytes(HSAMetadataString); 801 OS.emitLabel(DescEnd); 802 }); 803 return true; 804 } 805 806 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 807 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 808 std::string HSAMetadataString; 809 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 810 return false; 811 812 // Create two labels to mark the beginning and end of the desc field 813 // and a MCExpr to calculate the size of the desc field. 814 auto &Context = getContext(); 815 auto *DescBegin = Context.createTempSymbol(); 816 auto *DescEnd = Context.createTempSymbol(); 817 auto *DescSZ = MCBinaryExpr::createSub( 818 MCSymbolRefExpr::create(DescEnd, Context), 819 MCSymbolRefExpr::create(DescBegin, Context), Context); 820 821 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_METADATA, 822 [&](MCELFStreamer &OS) { 823 OS.emitLabel(DescBegin); 824 OS.emitBytes(HSAMetadataString); 825 OS.emitLabel(DescEnd); 826 }); 827 return true; 828 } 829 830 bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 831 const uint32_t Encoded_s_code_end = 0xbf9f0000; 832 const uint32_t Encoded_s_nop = 0xbf800000; 833 uint32_t Encoded_pad = Encoded_s_code_end; 834 835 // Instruction cache line size in bytes. 836 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6; 837 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 838 839 // Extra padding amount in bytes to support prefetch mode 3. 840 unsigned FillSize = 3 * CacheLineSize; 841 842 if (AMDGPU::isGFX90A(STI)) { 843 Encoded_pad = Encoded_s_nop; 844 FillSize = 16 * CacheLineSize; 845 } 846 847 MCStreamer &OS = getStreamer(); 848 OS.pushSection(); 849 OS.emitValueToAlignment(Align(CacheLineSize), Encoded_pad, 4); 850 for (unsigned I = 0; I < FillSize; I += 4) 851 OS.emitInt32(Encoded_pad); 852 OS.popSection(); 853 return true; 854 } 855 856 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 857 const MCSubtargetInfo &STI, StringRef KernelName, 858 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 859 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, 860 unsigned CodeObjectVersion) { 861 auto &Streamer = getStreamer(); 862 auto &Context = Streamer.getContext(); 863 864 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 865 Context.getOrCreateSymbol(Twine(KernelName))); 866 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 867 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 868 869 // Copy kernel descriptor symbol's binding, other and visibility from the 870 // kernel code symbol. 871 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 872 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 873 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 874 // Kernel descriptor symbol's type and size are fixed. 875 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 876 KernelDescriptorSymbol->setSize( 877 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 878 879 // The visibility of the kernel code symbol must be protected or less to allow 880 // static relocations from the kernel descriptor to be used. 881 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 882 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 883 884 Streamer.emitLabel(KernelDescriptorSymbol); 885 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size); 886 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size); 887 Streamer.emitInt32(KernelDescriptor.kernarg_size); 888 889 for (uint8_t Res : KernelDescriptor.reserved0) 890 Streamer.emitInt8(Res); 891 892 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 893 // expression being created is: 894 // (start of kernel code) - (start of kernel descriptor) 895 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 896 Streamer.emitValue(MCBinaryExpr::createSub( 897 MCSymbolRefExpr::create( 898 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 899 MCSymbolRefExpr::create( 900 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 901 Context), 902 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 903 for (uint8_t Res : KernelDescriptor.reserved1) 904 Streamer.emitInt8(Res); 905 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3); 906 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1); 907 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2); 908 Streamer.emitInt16(KernelDescriptor.kernel_code_properties); 909 for (uint8_t Res : KernelDescriptor.reserved2) 910 Streamer.emitInt8(Res); 911 } 912