1 //===-- AMDGPUMCTargetDesc.h - AMDGPU Target Descriptions -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// Provides AMDGPU specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H 16 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H 17 18 #include "llvm/Support/DataTypes.h" 19 20 #include <memory> 21 22 namespace llvm { 23 class MCAsmBackend; 24 class MCCodeEmitter; 25 class MCContext; 26 class MCInstrInfo; 27 class MCObjectTargetWriter; 28 class MCRegisterInfo; 29 class MCSubtargetInfo; 30 class MCTargetOptions; 31 class StringRef; 32 class Target; 33 class Triple; 34 class raw_pwrite_stream; 35 36 enum AMDGPUDwarfFlavour { Wave64 = 0, Wave32 = 1 }; 37 38 MCRegisterInfo *createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour); 39 40 MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII, 41 const MCRegisterInfo &MRI, 42 MCContext &Ctx); 43 MCInstrInfo *createR600MCInstrInfo(); 44 45 MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII, 46 const MCRegisterInfo &MRI, 47 MCContext &Ctx); 48 49 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, 50 const MCSubtargetInfo &STI, 51 const MCRegisterInfo &MRI, 52 const MCTargetOptions &Options); 53 54 std::unique_ptr<MCObjectTargetWriter> 55 createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, 56 bool HasRelocationAddend, uint8_t ABIVersion); 57 } // End llvm namespace 58 59 #define GET_REGINFO_ENUM 60 #include "AMDGPUGenRegisterInfo.inc" 61 #undef GET_REGINFO_ENUM 62 63 #define GET_REGINFO_ENUM 64 #include "R600GenRegisterInfo.inc" 65 #undef GET_REGINFO_ENUM 66 67 #define GET_INSTRINFO_ENUM 68 #define GET_INSTRINFO_OPERAND_ENUM 69 #define GET_INSTRINFO_SCHED_ENUM 70 #include "AMDGPUGenInstrInfo.inc" 71 #undef GET_INSTRINFO_SCHED_ENUM 72 #undef GET_INSTRINFO_OPERAND_ENUM 73 #undef GET_INSTRINFO_ENUM 74 75 #define GET_INSTRINFO_ENUM 76 #define GET_INSTRINFO_OPERAND_ENUM 77 #define GET_INSTRINFO_SCHED_ENUM 78 #include "R600GenInstrInfo.inc" 79 #undef GET_INSTRINFO_SCHED_ENUM 80 #undef GET_INSTRINFO_OPERAND_ENUM 81 #undef GET_INSTRINFO_ENUM 82 83 #define GET_SUBTARGETINFO_ENUM 84 #include "AMDGPUGenSubtargetInfo.inc" 85 #undef GET_SUBTARGETINFO_ENUM 86 87 #define GET_SUBTARGETINFO_ENUM 88 #include "R600GenSubtargetInfo.inc" 89 #undef GET_SUBTARGETINFO_ENUM 90 91 #endif 92