1 //===-- AMDGPUMCTargetDesc.h - AMDGPU Target Descriptions -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// Provides AMDGPU specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H 16 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H 17 18 #include <memory> 19 20 namespace llvm { 21 class MCAsmBackend; 22 class MCCodeEmitter; 23 class MCContext; 24 class MCInstrInfo; 25 class MCObjectTargetWriter; 26 class MCRegisterInfo; 27 class MCSubtargetInfo; 28 class MCTargetOptions; 29 class StringRef; 30 class Target; 31 class Triple; 32 class raw_pwrite_stream; 33 34 enum AMDGPUDwarfFlavour : unsigned { Wave64 = 0, Wave32 = 1 }; 35 36 MCRegisterInfo *createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour); 37 38 MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII, 39 const MCRegisterInfo &MRI, 40 MCContext &Ctx); 41 MCInstrInfo *createR600MCInstrInfo(); 42 43 MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII, 44 const MCRegisterInfo &MRI, 45 MCContext &Ctx); 46 47 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, 48 const MCSubtargetInfo &STI, 49 const MCRegisterInfo &MRI, 50 const MCTargetOptions &Options); 51 52 std::unique_ptr<MCObjectTargetWriter> 53 createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, 54 bool HasRelocationAddend, uint8_t ABIVersion); 55 } // End llvm namespace 56 57 #define GET_REGINFO_ENUM 58 #include "AMDGPUGenRegisterInfo.inc" 59 60 #define GET_REGINFO_ENUM 61 #include "R600GenRegisterInfo.inc" 62 63 #define GET_INSTRINFO_ENUM 64 #define GET_INSTRINFO_OPERAND_ENUM 65 #define GET_INSTRINFO_SCHED_ENUM 66 #include "AMDGPUGenInstrInfo.inc" 67 68 #define GET_INSTRINFO_ENUM 69 #define GET_INSTRINFO_OPERAND_ENUM 70 #define GET_INSTRINFO_SCHED_ENUM 71 #include "R600GenInstrInfo.inc" 72 73 #define GET_SUBTARGETINFO_ENUM 74 #include "AMDGPUGenSubtargetInfo.inc" 75 76 #define GET_SUBTARGETINFO_ENUM 77 #include "R600GenSubtargetInfo.inc" 78 79 #endif 80