1 //===-- AMDGPUMCCodeEmitter.cpp - AMDGPU Code Emitter ---------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// The AMDGPU code emitter produces machine code that can be executed 11 /// directly on the GPU device. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "MCTargetDesc/AMDGPUFixupKinds.h" 16 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 17 #include "SIDefines.h" 18 #include "Utils/AMDGPUBaseInfo.h" 19 #include "llvm/ADT/APInt.h" 20 #include "llvm/MC/MCCodeEmitter.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCExpr.h" 23 #include "llvm/MC/MCInstrInfo.h" 24 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/Support/Casting.h" 27 #include "llvm/Support/EndianStream.h" 28 #include "llvm/TargetParser/SubtargetFeature.h" 29 #include <optional> 30 31 using namespace llvm; 32 33 namespace { 34 35 class AMDGPUMCCodeEmitter : public MCCodeEmitter { 36 const MCRegisterInfo &MRI; 37 const MCInstrInfo &MCII; 38 39 public: 40 AMDGPUMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI) 41 : MRI(MRI), MCII(MCII) {} 42 43 /// Encode the instruction and write it to the OS. 44 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB, 45 SmallVectorImpl<MCFixup> &Fixups, 46 const MCSubtargetInfo &STI) const override; 47 48 void getMachineOpValue(const MCInst &MI, const MCOperand &MO, APInt &Op, 49 SmallVectorImpl<MCFixup> &Fixups, 50 const MCSubtargetInfo &STI) const; 51 52 /// Use a fixup to encode the simm16 field for SOPP branch 53 /// instructions. 54 void getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, APInt &Op, 55 SmallVectorImpl<MCFixup> &Fixups, 56 const MCSubtargetInfo &STI) const; 57 58 void getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo, APInt &Op, 59 SmallVectorImpl<MCFixup> &Fixups, 60 const MCSubtargetInfo &STI) const; 61 62 void getSDWASrcEncoding(const MCInst &MI, unsigned OpNo, APInt &Op, 63 SmallVectorImpl<MCFixup> &Fixups, 64 const MCSubtargetInfo &STI) const; 65 66 void getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo, APInt &Op, 67 SmallVectorImpl<MCFixup> &Fixups, 68 const MCSubtargetInfo &STI) const; 69 70 void getAVOperandEncoding(const MCInst &MI, unsigned OpNo, APInt &Op, 71 SmallVectorImpl<MCFixup> &Fixups, 72 const MCSubtargetInfo &STI) const; 73 74 private: 75 uint64_t getImplicitOpSelHiEncoding(int Opcode) const; 76 void getMachineOpValueCommon(const MCInst &MI, const MCOperand &MO, 77 unsigned OpNo, APInt &Op, 78 SmallVectorImpl<MCFixup> &Fixups, 79 const MCSubtargetInfo &STI) const; 80 81 /// Encode an fp or int literal. 82 std::optional<uint32_t> getLitEncoding(const MCOperand &MO, 83 const MCOperandInfo &OpInfo, 84 const MCSubtargetInfo &STI) const; 85 86 void getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, 87 APInt &Inst, APInt &Scratch, 88 const MCSubtargetInfo &STI) const; 89 }; 90 91 } // end anonymous namespace 92 93 MCCodeEmitter *llvm::createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, 94 MCContext &Ctx) { 95 return new AMDGPUMCCodeEmitter(MCII, *Ctx.getRegisterInfo()); 96 } 97 98 // Returns the encoding value to use if the given integer is an integer inline 99 // immediate value, or 0 if it is not. 100 template <typename IntTy> 101 static uint32_t getIntInlineImmEncoding(IntTy Imm) { 102 if (Imm >= 0 && Imm <= 64) 103 return 128 + Imm; 104 105 if (Imm >= -16 && Imm <= -1) 106 return 192 + std::abs(Imm); 107 108 return 0; 109 } 110 111 static uint32_t getLit16IntEncoding(uint16_t Val, const MCSubtargetInfo &STI) { 112 uint16_t IntImm = getIntInlineImmEncoding(static_cast<int16_t>(Val)); 113 return IntImm == 0 ? 255 : IntImm; 114 } 115 116 static uint32_t getLit16Encoding(uint16_t Val, const MCSubtargetInfo &STI) { 117 uint16_t IntImm = getIntInlineImmEncoding(static_cast<int16_t>(Val)); 118 if (IntImm != 0) 119 return IntImm; 120 121 if (Val == 0x3800) // 0.5 122 return 240; 123 124 if (Val == 0xB800) // -0.5 125 return 241; 126 127 if (Val == 0x3C00) // 1.0 128 return 242; 129 130 if (Val == 0xBC00) // -1.0 131 return 243; 132 133 if (Val == 0x4000) // 2.0 134 return 244; 135 136 if (Val == 0xC000) // -2.0 137 return 245; 138 139 if (Val == 0x4400) // 4.0 140 return 246; 141 142 if (Val == 0xC400) // -4.0 143 return 247; 144 145 if (Val == 0x3118 && // 1.0 / (2.0 * pi) 146 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) 147 return 248; 148 149 return 255; 150 } 151 152 static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI) { 153 uint32_t IntImm = getIntInlineImmEncoding(static_cast<int32_t>(Val)); 154 if (IntImm != 0) 155 return IntImm; 156 157 if (Val == llvm::bit_cast<uint32_t>(0.5f)) 158 return 240; 159 160 if (Val == llvm::bit_cast<uint32_t>(-0.5f)) 161 return 241; 162 163 if (Val == llvm::bit_cast<uint32_t>(1.0f)) 164 return 242; 165 166 if (Val == llvm::bit_cast<uint32_t>(-1.0f)) 167 return 243; 168 169 if (Val == llvm::bit_cast<uint32_t>(2.0f)) 170 return 244; 171 172 if (Val == llvm::bit_cast<uint32_t>(-2.0f)) 173 return 245; 174 175 if (Val == llvm::bit_cast<uint32_t>(4.0f)) 176 return 246; 177 178 if (Val == llvm::bit_cast<uint32_t>(-4.0f)) 179 return 247; 180 181 if (Val == 0x3e22f983 && // 1.0 / (2.0 * pi) 182 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) 183 return 248; 184 185 return 255; 186 } 187 188 static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) { 189 uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val)); 190 if (IntImm != 0) 191 return IntImm; 192 193 if (Val == llvm::bit_cast<uint64_t>(0.5)) 194 return 240; 195 196 if (Val == llvm::bit_cast<uint64_t>(-0.5)) 197 return 241; 198 199 if (Val == llvm::bit_cast<uint64_t>(1.0)) 200 return 242; 201 202 if (Val == llvm::bit_cast<uint64_t>(-1.0)) 203 return 243; 204 205 if (Val == llvm::bit_cast<uint64_t>(2.0)) 206 return 244; 207 208 if (Val == llvm::bit_cast<uint64_t>(-2.0)) 209 return 245; 210 211 if (Val == llvm::bit_cast<uint64_t>(4.0)) 212 return 246; 213 214 if (Val == llvm::bit_cast<uint64_t>(-4.0)) 215 return 247; 216 217 if (Val == 0x3fc45f306dc9c882 && // 1.0 / (2.0 * pi) 218 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) 219 return 248; 220 221 return 255; 222 } 223 224 std::optional<uint32_t> 225 AMDGPUMCCodeEmitter::getLitEncoding(const MCOperand &MO, 226 const MCOperandInfo &OpInfo, 227 const MCSubtargetInfo &STI) const { 228 int64_t Imm; 229 if (MO.isExpr()) { 230 const auto *C = dyn_cast<MCConstantExpr>(MO.getExpr()); 231 if (!C) 232 return 255; 233 234 Imm = C->getValue(); 235 } else { 236 237 assert(!MO.isDFPImm()); 238 239 if (!MO.isImm()) 240 return {}; 241 242 Imm = MO.getImm(); 243 } 244 245 switch (OpInfo.OperandType) { 246 case AMDGPU::OPERAND_REG_IMM_INT32: 247 case AMDGPU::OPERAND_REG_IMM_FP32: 248 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: 249 case AMDGPU::OPERAND_REG_INLINE_C_INT32: 250 case AMDGPU::OPERAND_REG_INLINE_C_FP32: 251 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: 252 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: 253 case AMDGPU::OPERAND_REG_IMM_V2INT32: 254 case AMDGPU::OPERAND_REG_IMM_V2FP32: 255 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: 256 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: 257 return getLit32Encoding(static_cast<uint32_t>(Imm), STI); 258 259 case AMDGPU::OPERAND_REG_IMM_INT64: 260 case AMDGPU::OPERAND_REG_IMM_FP64: 261 case AMDGPU::OPERAND_REG_INLINE_C_INT64: 262 case AMDGPU::OPERAND_REG_INLINE_C_FP64: 263 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: 264 return getLit64Encoding(static_cast<uint64_t>(Imm), STI); 265 266 case AMDGPU::OPERAND_REG_IMM_INT16: 267 case AMDGPU::OPERAND_REG_INLINE_C_INT16: 268 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: 269 return getLit16IntEncoding(static_cast<uint16_t>(Imm), STI); 270 case AMDGPU::OPERAND_REG_IMM_FP16: 271 case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: 272 case AMDGPU::OPERAND_REG_INLINE_C_FP16: 273 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: 274 // FIXME Is this correct? What do inline immediates do on SI for f16 src 275 // which does not have f16 support? 276 return getLit16Encoding(static_cast<uint16_t>(Imm), STI); 277 case AMDGPU::OPERAND_REG_IMM_V2INT16: 278 case AMDGPU::OPERAND_REG_IMM_V2FP16: { 279 if (!isUInt<16>(Imm) && STI.hasFeature(AMDGPU::FeatureVOP3Literal)) 280 return getLit32Encoding(static_cast<uint32_t>(Imm), STI); 281 if (OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2FP16) 282 return getLit16Encoding(static_cast<uint16_t>(Imm), STI); 283 [[fallthrough]]; 284 } 285 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: 286 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: 287 return getLit16IntEncoding(static_cast<uint16_t>(Imm), STI); 288 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: 289 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: { 290 uint16_t Lo16 = static_cast<uint16_t>(Imm); 291 uint32_t Encoding = getLit16Encoding(Lo16, STI); 292 return Encoding; 293 } 294 case AMDGPU::OPERAND_KIMM32: 295 case AMDGPU::OPERAND_KIMM16: 296 return MO.getImm(); 297 default: 298 llvm_unreachable("invalid operand size"); 299 } 300 } 301 302 uint64_t AMDGPUMCCodeEmitter::getImplicitOpSelHiEncoding(int Opcode) const { 303 using namespace AMDGPU::VOP3PEncoding; 304 using namespace AMDGPU::OpName; 305 306 if (AMDGPU::hasNamedOperand(Opcode, op_sel_hi)) { 307 if (AMDGPU::hasNamedOperand(Opcode, src2)) 308 return 0; 309 if (AMDGPU::hasNamedOperand(Opcode, src1)) 310 return OP_SEL_HI_2; 311 if (AMDGPU::hasNamedOperand(Opcode, src0)) 312 return OP_SEL_HI_1 | OP_SEL_HI_2; 313 } 314 return OP_SEL_HI_0 | OP_SEL_HI_1 | OP_SEL_HI_2; 315 } 316 317 static bool isVCMPX64(const MCInstrDesc &Desc) { 318 return (Desc.TSFlags & SIInstrFlags::VOP3) && 319 Desc.hasImplicitDefOfPhysReg(AMDGPU::EXEC); 320 } 321 322 void AMDGPUMCCodeEmitter::encodeInstruction(const MCInst &MI, 323 SmallVectorImpl<char> &CB, 324 SmallVectorImpl<MCFixup> &Fixups, 325 const MCSubtargetInfo &STI) const { 326 int Opcode = MI.getOpcode(); 327 APInt Encoding, Scratch; 328 getBinaryCodeForInstr(MI, Fixups, Encoding, Scratch, STI); 329 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 330 unsigned bytes = Desc.getSize(); 331 332 // Set unused op_sel_hi bits to 1 for VOP3P and MAI instructions. 333 // Note that accvgpr_read/write are MAI, have src0, but do not use op_sel. 334 if ((Desc.TSFlags & SIInstrFlags::VOP3P) || 335 Opcode == AMDGPU::V_ACCVGPR_READ_B32_vi || 336 Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_vi) { 337 Encoding |= getImplicitOpSelHiEncoding(Opcode); 338 } 339 340 // GFX10+ v_cmpx opcodes promoted to VOP3 have implied dst=EXEC. 341 // Documentation requires dst to be encoded as EXEC (0x7E), 342 // but it looks like the actual value encoded for dst operand 343 // is ignored by HW. It was decided to define dst as "do not care" 344 // in td files to allow disassembler accept any dst value. 345 // However, dst is encoded as EXEC for compatibility with SP3. 346 if (AMDGPU::isGFX10Plus(STI) && isVCMPX64(Desc)) { 347 assert((Encoding & 0xFF) == 0); 348 Encoding |= MRI.getEncodingValue(AMDGPU::EXEC_LO); 349 } 350 351 for (unsigned i = 0; i < bytes; i++) { 352 CB.push_back((uint8_t)Encoding.extractBitsAsZExtValue(8, 8 * i)); 353 } 354 355 // NSA encoding. 356 if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) { 357 int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 358 AMDGPU::OpName::vaddr0); 359 int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 360 AMDGPU::OpName::srsrc); 361 assert(vaddr0 >= 0 && srsrc > vaddr0); 362 unsigned NumExtraAddrs = srsrc - vaddr0 - 1; 363 unsigned NumPadding = (-NumExtraAddrs) & 3; 364 365 for (unsigned i = 0; i < NumExtraAddrs; ++i) { 366 getMachineOpValue(MI, MI.getOperand(vaddr0 + 1 + i), Encoding, Fixups, 367 STI); 368 CB.push_back((uint8_t)Encoding.getLimitedValue()); 369 } 370 CB.append(NumPadding, 0); 371 } 372 373 if ((bytes > 8 && STI.hasFeature(AMDGPU::FeatureVOP3Literal)) || 374 (bytes > 4 && !STI.hasFeature(AMDGPU::FeatureVOP3Literal))) 375 return; 376 377 // Do not print literals from SISrc Operands for insts with mandatory literals 378 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::imm)) 379 return; 380 381 // Check for additional literals 382 for (unsigned i = 0, e = Desc.getNumOperands(); i < e; ++i) { 383 384 // Check if this operand should be encoded as [SV]Src 385 if (!AMDGPU::isSISrcOperand(Desc, i)) 386 continue; 387 388 // Is this operand a literal immediate? 389 const MCOperand &Op = MI.getOperand(i); 390 auto Enc = getLitEncoding(Op, Desc.operands()[i], STI); 391 if (!Enc || *Enc != 255) 392 continue; 393 394 // Yes! Encode it 395 int64_t Imm = 0; 396 397 if (Op.isImm()) 398 Imm = Op.getImm(); 399 else if (Op.isExpr()) { 400 if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr())) 401 Imm = C->getValue(); 402 403 } else if (!Op.isExpr()) // Exprs will be replaced with a fixup value. 404 llvm_unreachable("Must be immediate or expr"); 405 406 support::endian::write<uint32_t>(CB, Imm, support::endianness::little); 407 408 // Only one literal value allowed 409 break; 410 } 411 } 412 413 void AMDGPUMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, 414 APInt &Op, 415 SmallVectorImpl<MCFixup> &Fixups, 416 const MCSubtargetInfo &STI) const { 417 const MCOperand &MO = MI.getOperand(OpNo); 418 419 if (MO.isExpr()) { 420 const MCExpr *Expr = MO.getExpr(); 421 MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br; 422 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 423 Op = APInt::getZero(96); 424 } else { 425 getMachineOpValue(MI, MO, Op, Fixups, STI); 426 } 427 } 428 429 void AMDGPUMCCodeEmitter::getSMEMOffsetEncoding( 430 const MCInst &MI, unsigned OpNo, APInt &Op, 431 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { 432 auto Offset = MI.getOperand(OpNo).getImm(); 433 // VI only supports 20-bit unsigned offsets. 434 assert(!AMDGPU::isVI(STI) || isUInt<20>(Offset)); 435 Op = Offset; 436 } 437 438 void AMDGPUMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo, 439 APInt &Op, 440 SmallVectorImpl<MCFixup> &Fixups, 441 const MCSubtargetInfo &STI) const { 442 using namespace AMDGPU::SDWA; 443 444 uint64_t RegEnc = 0; 445 446 const MCOperand &MO = MI.getOperand(OpNo); 447 448 if (MO.isReg()) { 449 unsigned Reg = MO.getReg(); 450 RegEnc |= MRI.getEncodingValue(Reg); 451 RegEnc &= SDWA9EncValues::SRC_VGPR_MASK; 452 if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) { 453 RegEnc |= SDWA9EncValues::SRC_SGPR_MASK; 454 } 455 Op = RegEnc; 456 return; 457 } else { 458 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 459 auto Enc = getLitEncoding(MO, Desc.operands()[OpNo], STI); 460 if (Enc && *Enc != 255) { 461 Op = *Enc | SDWA9EncValues::SRC_SGPR_MASK; 462 return; 463 } 464 } 465 466 llvm_unreachable("Unsupported operand kind"); 467 } 468 469 void AMDGPUMCCodeEmitter::getSDWAVopcDstEncoding( 470 const MCInst &MI, unsigned OpNo, APInt &Op, 471 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { 472 using namespace AMDGPU::SDWA; 473 474 uint64_t RegEnc = 0; 475 476 const MCOperand &MO = MI.getOperand(OpNo); 477 478 unsigned Reg = MO.getReg(); 479 if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) { 480 RegEnc |= MRI.getEncodingValue(Reg); 481 RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 482 RegEnc |= SDWA9EncValues::VOPC_DST_VCC_MASK; 483 } 484 Op = RegEnc; 485 } 486 487 void AMDGPUMCCodeEmitter::getAVOperandEncoding( 488 const MCInst &MI, unsigned OpNo, APInt &Op, 489 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { 490 unsigned Reg = MI.getOperand(OpNo).getReg(); 491 uint64_t Enc = MRI.getEncodingValue(Reg); 492 493 // VGPR and AGPR have the same encoding, but SrcA and SrcB operands of mfma 494 // instructions use acc[0:1] modifier bits to distinguish. These bits are 495 // encoded as a virtual 9th bit of the register for these operands. 496 if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) || 497 MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) || 498 MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) || 499 MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) || 500 MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) || 501 MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) || 502 MRI.getRegClass(AMDGPU::AReg_224RegClassID).contains(Reg) || 503 MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) || 504 MRI.getRegClass(AMDGPU::AReg_288RegClassID).contains(Reg) || 505 MRI.getRegClass(AMDGPU::AReg_320RegClassID).contains(Reg) || 506 MRI.getRegClass(AMDGPU::AReg_352RegClassID).contains(Reg) || 507 MRI.getRegClass(AMDGPU::AReg_384RegClassID).contains(Reg) || 508 MRI.getRegClass(AMDGPU::AReg_512RegClassID).contains(Reg) || 509 MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg)) 510 Enc |= 512; 511 512 Op = Enc; 513 } 514 515 static bool needsPCRel(const MCExpr *Expr) { 516 switch (Expr->getKind()) { 517 case MCExpr::SymbolRef: { 518 auto *SE = cast<MCSymbolRefExpr>(Expr); 519 MCSymbolRefExpr::VariantKind Kind = SE->getKind(); 520 return Kind != MCSymbolRefExpr::VK_AMDGPU_ABS32_LO && 521 Kind != MCSymbolRefExpr::VK_AMDGPU_ABS32_HI; 522 } 523 case MCExpr::Binary: { 524 auto *BE = cast<MCBinaryExpr>(Expr); 525 if (BE->getOpcode() == MCBinaryExpr::Sub) 526 return false; 527 return needsPCRel(BE->getLHS()) || needsPCRel(BE->getRHS()); 528 } 529 case MCExpr::Unary: 530 return needsPCRel(cast<MCUnaryExpr>(Expr)->getSubExpr()); 531 case MCExpr::Target: 532 case MCExpr::Constant: 533 return false; 534 } 535 llvm_unreachable("invalid kind"); 536 } 537 538 void AMDGPUMCCodeEmitter::getMachineOpValue(const MCInst &MI, 539 const MCOperand &MO, APInt &Op, 540 SmallVectorImpl<MCFixup> &Fixups, 541 const MCSubtargetInfo &STI) const { 542 if (MO.isReg()){ 543 Op = MRI.getEncodingValue(MO.getReg()); 544 return; 545 } 546 unsigned OpNo = &MO - MI.begin(); 547 getMachineOpValueCommon(MI, MO, OpNo, Op, Fixups, STI); 548 } 549 550 void AMDGPUMCCodeEmitter::getMachineOpValueCommon( 551 const MCInst &MI, const MCOperand &MO, unsigned OpNo, APInt &Op, 552 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { 553 554 if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) { 555 // FIXME: If this is expression is PCRel or not should not depend on what 556 // the expression looks like. Given that this is just a general expression, 557 // it should probably be FK_Data_4 and whatever is producing 558 // 559 // s_add_u32 s2, s2, (extern_const_addrspace+16 560 // 561 // And expecting a PCRel should instead produce 562 // 563 // .Ltmp1: 564 // s_add_u32 s2, s2, (extern_const_addrspace+16)-.Ltmp1 565 MCFixupKind Kind; 566 if (needsPCRel(MO.getExpr())) 567 Kind = FK_PCRel_4; 568 else 569 Kind = FK_Data_4; 570 571 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 572 uint32_t Offset = Desc.getSize(); 573 assert(Offset == 4 || Offset == 8); 574 575 Fixups.push_back(MCFixup::create(Offset, MO.getExpr(), Kind, MI.getLoc())); 576 } 577 578 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 579 if (AMDGPU::isSISrcOperand(Desc, OpNo)) { 580 if (auto Enc = getLitEncoding(MO, Desc.operands()[OpNo], STI)) { 581 Op = *Enc; 582 return; 583 } 584 } else if (MO.isImm()) { 585 Op = MO.getImm(); 586 return; 587 } 588 589 llvm_unreachable("Encoding of this operand type is not supported yet."); 590 } 591 592 #include "AMDGPUGenMCCodeEmitter.inc" 593