1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 // \file 8 //===----------------------------------------------------------------------===// 9 10 #include "AMDGPUInstPrinter.h" 11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 12 #include "SIDefines.h" 13 #include "SIRegisterInfo.h" 14 #include "Utils/AMDGPUAsmUtils.h" 15 #include "Utils/AMDGPUBaseInfo.h" 16 #include "llvm/MC/MCExpr.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCInstrDesc.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/Support/CommandLine.h" 22 #include "llvm/TargetParser/TargetParser.h" 23 24 using namespace llvm; 25 using namespace llvm::AMDGPU; 26 27 static cl::opt<bool> Keep16BitSuffixes( 28 "amdgpu-keep-16-bit-reg-suffixes", 29 cl::desc("Keep .l and .h suffixes in asm for debugging purposes"), 30 cl::init(false), 31 cl::ReallyHidden); 32 33 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { 34 // FIXME: The current implementation of 35 // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this 36 // as an integer or we provide a name which represents a physical register. 37 // For CFI instructions we really want to emit a name for the DWARF register 38 // instead, because there may be multiple DWARF registers corresponding to a 39 // single physical register. One case where this problem manifests is with 40 // wave32/wave64 where using the physical register name is ambiguous: if we 41 // write e.g. `.cfi_undefined v0` we lose information about the wavefront 42 // size which we need to encode the register in the final DWARF. Ideally we 43 // would extend MC to support parsing DWARF register names so we could do 44 // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with 45 // non-pretty DWARF register names in assembly text. 46 OS << Reg.id(); 47 } 48 49 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address, 50 StringRef Annot, const MCSubtargetInfo &STI, 51 raw_ostream &OS) { 52 OS.flush(); 53 printInstruction(MI, Address, STI, OS); 54 printAnnotation(OS, Annot); 55 } 56 57 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo, 58 const MCSubtargetInfo &STI, 59 raw_ostream &O) { 60 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); 61 } 62 63 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, 64 const MCSubtargetInfo &STI, 65 raw_ostream &O) { 66 // It's possible to end up with a 32-bit literal used with a 16-bit operand 67 // with ignored high bits. Print as 32-bit anyway in that case. 68 int64_t Imm = MI->getOperand(OpNo).getImm(); 69 if (isInt<16>(Imm) || isUInt<16>(Imm)) 70 O << formatHex(static_cast<uint64_t>(Imm & 0xffff)); 71 else 72 printU32ImmOperand(MI, OpNo, STI, O); 73 } 74 75 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, 76 raw_ostream &O) { 77 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf); 78 } 79 80 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, 81 raw_ostream &O) { 82 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); 83 } 84 85 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, 86 raw_ostream &O) { 87 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); 88 } 89 90 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo, 91 const MCSubtargetInfo &STI, 92 raw_ostream &O) { 93 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); 94 } 95 96 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo, 97 raw_ostream &O, StringRef BitName) { 98 if (MI->getOperand(OpNo).getImm()) { 99 O << ' ' << BitName; 100 } 101 } 102 103 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo, 104 const MCSubtargetInfo &STI, 105 raw_ostream &O) { 106 uint16_t Imm = MI->getOperand(OpNo).getImm(); 107 if (Imm != 0) { 108 O << " offset:"; 109 printU16ImmDecOperand(MI, OpNo, O); 110 } 111 } 112 113 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo, 114 const MCSubtargetInfo &STI, 115 raw_ostream &O) { 116 uint16_t Imm = MI->getOperand(OpNo).getImm(); 117 if (Imm != 0) { 118 O << " offset:"; 119 120 const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 121 bool IsFlatSeg = !(Desc.TSFlags & 122 (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch)); 123 124 if (IsFlatSeg) // Unsigned offset 125 printU16ImmDecOperand(MI, OpNo, O); 126 else // Signed offset 127 O << formatDec(SignExtend32(Imm, AMDGPU::getNumFlatOffsetBits(STI))); 128 } 129 } 130 131 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo, 132 const MCSubtargetInfo &STI, 133 raw_ostream &O) { 134 if (MI->getOperand(OpNo).getImm()) { 135 O << " offset0:"; 136 printU8ImmDecOperand(MI, OpNo, O); 137 } 138 } 139 140 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo, 141 const MCSubtargetInfo &STI, 142 raw_ostream &O) { 143 if (MI->getOperand(OpNo).getImm()) { 144 O << " offset1:"; 145 printU8ImmDecOperand(MI, OpNo, O); 146 } 147 } 148 149 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo, 150 const MCSubtargetInfo &STI, 151 raw_ostream &O) { 152 printU32ImmOperand(MI, OpNo, STI, O); 153 } 154 155 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo, 156 const MCSubtargetInfo &STI, 157 raw_ostream &O) { 158 O << formatHex(MI->getOperand(OpNo).getImm()); 159 } 160 161 void AMDGPUInstPrinter::printSMEMOffsetMod(const MCInst *MI, unsigned OpNo, 162 const MCSubtargetInfo &STI, 163 raw_ostream &O) { 164 O << " offset:"; 165 printSMEMOffset(MI, OpNo, STI, O); 166 } 167 168 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo, 169 const MCSubtargetInfo &STI, 170 raw_ostream &O) { 171 printU32ImmOperand(MI, OpNo, STI, O); 172 } 173 174 void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo, 175 const MCSubtargetInfo &STI, raw_ostream &O) { 176 auto Imm = MI->getOperand(OpNo).getImm(); 177 if (Imm & CPol::GLC) 178 O << ((AMDGPU::isGFX940(STI) && 179 !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD)) ? " sc0" 180 : " glc"); 181 if (Imm & CPol::SLC) 182 O << (AMDGPU::isGFX940(STI) ? " nt" : " slc"); 183 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI)) 184 O << " dlc"; 185 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI)) 186 O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc"); 187 if (Imm & ~CPol::ALL) 188 O << " /* unexpected cache policy bit */"; 189 } 190 191 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo, 192 const MCSubtargetInfo &STI, raw_ostream &O) { 193 if (MI->getOperand(OpNo).getImm()) { 194 O << " dmask:"; 195 printU16ImmOperand(MI, OpNo, STI, O); 196 } 197 } 198 199 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo, 200 const MCSubtargetInfo &STI, raw_ostream &O) { 201 unsigned Dim = MI->getOperand(OpNo).getImm(); 202 O << " dim:SQ_RSRC_IMG_"; 203 204 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); 205 if (DimInfo) 206 O << DimInfo->AsmSuffix; 207 else 208 O << Dim; 209 } 210 211 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo, 212 const MCSubtargetInfo &STI, raw_ostream &O) { 213 if (STI.hasFeature(AMDGPU::FeatureR128A16)) 214 printNamedBit(MI, OpNo, O, "a16"); 215 else 216 printNamedBit(MI, OpNo, O, "r128"); 217 } 218 219 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo, 220 const MCSubtargetInfo &STI, 221 raw_ostream &O) { 222 } 223 224 void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI, 225 const MCSubtargetInfo &STI, 226 raw_ostream &O) { 227 using namespace llvm::AMDGPU::MTBUFFormat; 228 229 int OpNo = 230 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format); 231 assert(OpNo != -1); 232 233 unsigned Val = MI->getOperand(OpNo).getImm(); 234 if (AMDGPU::isGFX10Plus(STI)) { 235 if (Val == UFMT_DEFAULT) 236 return; 237 if (isValidUnifiedFormat(Val, STI)) { 238 O << " format:[" << getUnifiedFormatName(Val, STI) << ']'; 239 } else { 240 O << " format:" << Val; 241 } 242 } else { 243 if (Val == DFMT_NFMT_DEFAULT) 244 return; 245 if (isValidDfmtNfmt(Val, STI)) { 246 unsigned Dfmt; 247 unsigned Nfmt; 248 decodeDfmtNfmt(Val, Dfmt, Nfmt); 249 O << " format:["; 250 if (Dfmt != DFMT_DEFAULT) { 251 O << getDfmtName(Dfmt); 252 if (Nfmt != NFMT_DEFAULT) { 253 O << ','; 254 } 255 } 256 if (Nfmt != NFMT_DEFAULT) { 257 O << getNfmtName(Nfmt, STI); 258 } 259 O << ']'; 260 } else { 261 O << " format:" << Val; 262 } 263 } 264 } 265 266 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O, 267 const MCRegisterInfo &MRI) { 268 #if !defined(NDEBUG) 269 switch (RegNo) { 270 case AMDGPU::FP_REG: 271 case AMDGPU::SP_REG: 272 case AMDGPU::PRIVATE_RSRC_REG: 273 llvm_unreachable("pseudo-register should not ever be emitted"); 274 case AMDGPU::SCC: 275 llvm_unreachable("pseudo scc should not ever be emitted"); 276 default: 277 break; 278 } 279 #endif 280 281 StringRef RegName(getRegisterName(RegNo)); 282 if (!Keep16BitSuffixes) 283 if (!RegName.consume_back(".l")) 284 RegName.consume_back(".h"); 285 286 O << RegName; 287 } 288 289 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo, 290 const MCSubtargetInfo &STI, raw_ostream &O) { 291 auto Opcode = MI->getOpcode(); 292 auto Flags = MII.get(Opcode).TSFlags; 293 if (OpNo == 0) { 294 if (Flags & SIInstrFlags::VOP3 && Flags & SIInstrFlags::DPP) 295 O << "_e64_dpp"; 296 else if (Flags & SIInstrFlags::VOP3) { 297 if (!getVOP3IsSingle(Opcode)) 298 O << "_e64"; 299 } else if (Flags & SIInstrFlags::DPP) 300 O << "_dpp"; 301 else if (Flags & SIInstrFlags::SDWA) 302 O << "_sdwa"; 303 else if (((Flags & SIInstrFlags::VOP1) && !getVOP1IsSingle(Opcode)) || 304 ((Flags & SIInstrFlags::VOP2) && !getVOP2IsSingle(Opcode))) 305 O << "_e32"; 306 O << " "; 307 } 308 309 printRegularOperand(MI, OpNo, STI, O); 310 311 // Print default vcc/vcc_lo operand. 312 switch (Opcode) { 313 default: break; 314 315 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10: 316 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10: 317 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: 318 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10: 319 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10: 320 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10: 321 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10: 322 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10: 323 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10: 324 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10: 325 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10: 326 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10: 327 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11: 328 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11: 329 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11: 330 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11: 331 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11: 332 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11: 333 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11: 334 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11: 335 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11: 336 printDefaultVccOperand(false, STI, O); 337 break; 338 } 339 } 340 341 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo, 342 const MCSubtargetInfo &STI, raw_ostream &O) { 343 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI)) 344 O << " "; 345 else 346 O << "_e32 "; 347 348 printRegularOperand(MI, OpNo, STI, O); 349 } 350 351 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm, 352 const MCSubtargetInfo &STI, 353 raw_ostream &O) { 354 int16_t SImm = static_cast<int16_t>(Imm); 355 if (isInlinableIntLiteral(SImm)) { 356 O << SImm; 357 } else { 358 uint64_t Imm16 = static_cast<uint16_t>(Imm); 359 O << formatHex(Imm16); 360 } 361 } 362 363 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm, 364 const MCSubtargetInfo &STI, 365 raw_ostream &O) { 366 int16_t SImm = static_cast<int16_t>(Imm); 367 if (isInlinableIntLiteral(SImm)) { 368 O << SImm; 369 return; 370 } 371 372 if (Imm == 0x3C00) 373 O<< "1.0"; 374 else if (Imm == 0xBC00) 375 O<< "-1.0"; 376 else if (Imm == 0x3800) 377 O<< "0.5"; 378 else if (Imm == 0xB800) 379 O<< "-0.5"; 380 else if (Imm == 0x4000) 381 O<< "2.0"; 382 else if (Imm == 0xC000) 383 O<< "-2.0"; 384 else if (Imm == 0x4400) 385 O<< "4.0"; 386 else if (Imm == 0xC400) 387 O<< "-4.0"; 388 else if (Imm == 0x3118 && 389 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) { 390 O << "0.15915494"; 391 } else { 392 uint64_t Imm16 = static_cast<uint16_t>(Imm); 393 O << formatHex(Imm16); 394 } 395 } 396 397 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm, 398 const MCSubtargetInfo &STI, 399 raw_ostream &O) { 400 uint16_t Lo16 = static_cast<uint16_t>(Imm); 401 printImmediate16(Lo16, STI, O); 402 } 403 404 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, 405 const MCSubtargetInfo &STI, 406 raw_ostream &O) { 407 int32_t SImm = static_cast<int32_t>(Imm); 408 if (SImm >= -16 && SImm <= 64) { 409 O << SImm; 410 return; 411 } 412 413 if (Imm == llvm::bit_cast<uint32_t>(0.0f)) 414 O << "0.0"; 415 else if (Imm == llvm::bit_cast<uint32_t>(1.0f)) 416 O << "1.0"; 417 else if (Imm == llvm::bit_cast<uint32_t>(-1.0f)) 418 O << "-1.0"; 419 else if (Imm == llvm::bit_cast<uint32_t>(0.5f)) 420 O << "0.5"; 421 else if (Imm == llvm::bit_cast<uint32_t>(-0.5f)) 422 O << "-0.5"; 423 else if (Imm == llvm::bit_cast<uint32_t>(2.0f)) 424 O << "2.0"; 425 else if (Imm == llvm::bit_cast<uint32_t>(-2.0f)) 426 O << "-2.0"; 427 else if (Imm == llvm::bit_cast<uint32_t>(4.0f)) 428 O << "4.0"; 429 else if (Imm == llvm::bit_cast<uint32_t>(-4.0f)) 430 O << "-4.0"; 431 else if (Imm == 0x3e22f983 && 432 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) 433 O << "0.15915494"; 434 else 435 O << formatHex(static_cast<uint64_t>(Imm)); 436 } 437 438 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm, 439 const MCSubtargetInfo &STI, 440 raw_ostream &O) { 441 int64_t SImm = static_cast<int64_t>(Imm); 442 if (SImm >= -16 && SImm <= 64) { 443 O << SImm; 444 return; 445 } 446 447 if (Imm == llvm::bit_cast<uint64_t>(0.0)) 448 O << "0.0"; 449 else if (Imm == llvm::bit_cast<uint64_t>(1.0)) 450 O << "1.0"; 451 else if (Imm == llvm::bit_cast<uint64_t>(-1.0)) 452 O << "-1.0"; 453 else if (Imm == llvm::bit_cast<uint64_t>(0.5)) 454 O << "0.5"; 455 else if (Imm == llvm::bit_cast<uint64_t>(-0.5)) 456 O << "-0.5"; 457 else if (Imm == llvm::bit_cast<uint64_t>(2.0)) 458 O << "2.0"; 459 else if (Imm == llvm::bit_cast<uint64_t>(-2.0)) 460 O << "-2.0"; 461 else if (Imm == llvm::bit_cast<uint64_t>(4.0)) 462 O << "4.0"; 463 else if (Imm == llvm::bit_cast<uint64_t>(-4.0)) 464 O << "-4.0"; 465 else if (Imm == 0x3fc45f306dc9c882 && 466 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) 467 O << "0.15915494309189532"; 468 else { 469 assert(isUInt<32>(Imm) || isInt<32>(Imm)); 470 471 // In rare situations, we will have a 32-bit literal in a 64-bit 472 // operand. This is technically allowed for the encoding of s_mov_b64. 473 O << formatHex(static_cast<uint64_t>(Imm)); 474 } 475 } 476 477 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo, 478 const MCSubtargetInfo &STI, 479 raw_ostream &O) { 480 unsigned Imm = MI->getOperand(OpNo).getImm(); 481 if (!Imm) 482 return; 483 484 if (AMDGPU::isGFX940(STI)) { 485 switch (MI->getOpcode()) { 486 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd: 487 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd: 488 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd: 489 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd: 490 O << " neg:[" << (Imm & 1) << ',' << ((Imm >> 1) & 1) << ',' 491 << ((Imm >> 2) & 1) << ']'; 492 return; 493 } 494 } 495 496 O << " blgp:" << Imm; 497 } 498 499 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo, 500 const MCSubtargetInfo &STI, 501 raw_ostream &O) { 502 unsigned Imm = MI->getOperand(OpNo).getImm(); 503 if (!Imm) 504 return; 505 506 O << " cbsz:" << Imm; 507 } 508 509 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo, 510 const MCSubtargetInfo &STI, 511 raw_ostream &O) { 512 unsigned Imm = MI->getOperand(OpNo).getImm(); 513 if (!Imm) 514 return; 515 516 O << " abid:" << Imm; 517 } 518 519 void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand, 520 const MCSubtargetInfo &STI, 521 raw_ostream &O) { 522 if (!FirstOperand) 523 O << ", "; 524 printRegOperand(STI.hasFeature(AMDGPU::FeatureWavefrontSize64) 525 ? AMDGPU::VCC 526 : AMDGPU::VCC_LO, 527 O, MRI); 528 if (FirstOperand) 529 O << ", "; 530 } 531 532 void AMDGPUInstPrinter::printWaitVDST(const MCInst *MI, unsigned OpNo, 533 const MCSubtargetInfo &STI, 534 raw_ostream &O) { 535 uint8_t Imm = MI->getOperand(OpNo).getImm(); 536 if (Imm != 0) { 537 O << " wait_vdst:"; 538 printU4ImmDecOperand(MI, OpNo, O); 539 } 540 } 541 542 void AMDGPUInstPrinter::printWaitEXP(const MCInst *MI, unsigned OpNo, 543 const MCSubtargetInfo &STI, 544 raw_ostream &O) { 545 uint8_t Imm = MI->getOperand(OpNo).getImm(); 546 if (Imm != 0) { 547 O << " wait_exp:"; 548 printU4ImmDecOperand(MI, OpNo, O); 549 } 550 } 551 552 bool AMDGPUInstPrinter::needsImpliedVcc(const MCInstrDesc &Desc, 553 unsigned OpNo) const { 554 return OpNo == 0 && (Desc.TSFlags & SIInstrFlags::DPP) && 555 (Desc.TSFlags & SIInstrFlags::VOPC) && 556 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) || 557 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)); 558 } 559 560 // Print default vcc/vcc_lo operand of VOPC. 561 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 562 const MCSubtargetInfo &STI, 563 raw_ostream &O) { 564 unsigned Opc = MI->getOpcode(); 565 const MCInstrDesc &Desc = MII.get(Opc); 566 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); 567 // 0, 1 and 2 are the first printed operands in different cases 568 // If there are printed modifiers, printOperandAndFPInputMods or 569 // printOperandAndIntInputMods will be called instead 570 if ((OpNo == 0 || 571 (OpNo == 1 && (Desc.TSFlags & SIInstrFlags::DPP) && ModIdx != -1)) && 572 (Desc.TSFlags & SIInstrFlags::VOPC) && 573 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) || 574 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO))) 575 printDefaultVccOperand(true, STI, O); 576 577 printRegularOperand(MI, OpNo, STI, O); 578 } 579 580 // Print operands after vcc or modifier handling. 581 void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo, 582 const MCSubtargetInfo &STI, 583 raw_ostream &O) { 584 const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 585 586 if (OpNo >= MI->getNumOperands()) { 587 O << "/*Missing OP" << OpNo << "*/"; 588 return; 589 } 590 591 const MCOperand &Op = MI->getOperand(OpNo); 592 if (Op.isReg()) { 593 printRegOperand(Op.getReg(), O, MRI); 594 595 // Check if operand register class contains register used. 596 // Intention: print disassembler message when invalid code is decoded, 597 // for example sgpr register used in VReg or VISrc(VReg or imm) operand. 598 int RCID = Desc.operands()[OpNo].RegClass; 599 if (RCID != -1) { 600 const MCRegisterClass RC = MRI.getRegClass(RCID); 601 auto Reg = mc2PseudoReg(Op.getReg()); 602 if (!RC.contains(Reg) && !isInlineValue(Reg)) { 603 O << "/*Invalid register, operand has \'" << MRI.getRegClassName(&RC) 604 << "\' register class*/"; 605 } 606 } 607 } else if (Op.isImm()) { 608 const uint8_t OpTy = Desc.operands()[OpNo].OperandType; 609 switch (OpTy) { 610 case AMDGPU::OPERAND_REG_IMM_INT32: 611 case AMDGPU::OPERAND_REG_IMM_FP32: 612 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: 613 case AMDGPU::OPERAND_REG_INLINE_C_INT32: 614 case AMDGPU::OPERAND_REG_INLINE_C_FP32: 615 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: 616 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: 617 case AMDGPU::OPERAND_REG_IMM_V2INT32: 618 case AMDGPU::OPERAND_REG_IMM_V2FP32: 619 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: 620 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: 621 case MCOI::OPERAND_IMMEDIATE: 622 printImmediate32(Op.getImm(), STI, O); 623 break; 624 case AMDGPU::OPERAND_REG_IMM_INT64: 625 case AMDGPU::OPERAND_REG_IMM_FP64: 626 case AMDGPU::OPERAND_REG_INLINE_C_INT64: 627 case AMDGPU::OPERAND_REG_INLINE_C_FP64: 628 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: 629 printImmediate64(Op.getImm(), STI, O); 630 break; 631 case AMDGPU::OPERAND_REG_INLINE_C_INT16: 632 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: 633 case AMDGPU::OPERAND_REG_IMM_INT16: 634 printImmediateInt16(Op.getImm(), STI, O); 635 break; 636 case AMDGPU::OPERAND_REG_INLINE_C_FP16: 637 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: 638 case AMDGPU::OPERAND_REG_IMM_FP16: 639 case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: 640 printImmediate16(Op.getImm(), STI, O); 641 break; 642 case AMDGPU::OPERAND_REG_IMM_V2INT16: 643 case AMDGPU::OPERAND_REG_IMM_V2FP16: 644 if (!isUInt<16>(Op.getImm()) && 645 STI.hasFeature(AMDGPU::FeatureVOP3Literal)) { 646 printImmediate32(Op.getImm(), STI, O); 647 break; 648 } 649 650 // Deal with 16-bit FP inline immediates not working. 651 if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) { 652 printImmediate16(static_cast<uint16_t>(Op.getImm()), STI, O); 653 break; 654 } 655 [[fallthrough]]; 656 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: 657 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: 658 printImmediateInt16(static_cast<uint16_t>(Op.getImm()), STI, O); 659 break; 660 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: 661 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: 662 printImmediateV216(Op.getImm(), STI, O); 663 break; 664 case MCOI::OPERAND_UNKNOWN: 665 case MCOI::OPERAND_PCREL: 666 O << formatDec(Op.getImm()); 667 break; 668 case MCOI::OPERAND_REGISTER: 669 // Disassembler does not fail when operand should not allow immediate 670 // operands but decodes them into 32bit immediate operand. 671 printImmediate32(Op.getImm(), STI, O); 672 O << "/*Invalid immediate*/"; 673 break; 674 default: 675 // We hit this for the immediate instruction bits that don't yet have a 676 // custom printer. 677 llvm_unreachable("unexpected immediate operand type"); 678 } 679 } else if (Op.isDFPImm()) { 680 double Value = bit_cast<double>(Op.getDFPImm()); 681 // We special case 0.0 because otherwise it will be printed as an integer. 682 if (Value == 0.0) 683 O << "0.0"; 684 else { 685 const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 686 int RCID = Desc.operands()[OpNo].RegClass; 687 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); 688 if (RCBits == 32) 689 printImmediate32(llvm::bit_cast<uint32_t>((float)Value), STI, O); 690 else if (RCBits == 64) 691 printImmediate64(llvm::bit_cast<uint64_t>(Value), STI, O); 692 else 693 llvm_unreachable("Invalid register class size"); 694 } 695 } else if (Op.isExpr()) { 696 const MCExpr *Exp = Op.getExpr(); 697 Exp->print(O, &MAI); 698 } else { 699 O << "/*INV_OP*/"; 700 } 701 702 // Print default vcc/vcc_lo operand of v_cndmask_b32_e32. 703 switch (MI->getOpcode()) { 704 default: break; 705 706 case AMDGPU::V_CNDMASK_B32_e32_gfx10: 707 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10: 708 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10: 709 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: 710 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10: 711 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10: 712 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10: 713 case AMDGPU::V_CNDMASK_B32_dpp8_gfx10: 714 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10: 715 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10: 716 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10: 717 case AMDGPU::V_CNDMASK_B32_e32_gfx11: 718 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11: 719 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11: 720 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11: 721 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11: 722 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11: 723 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11: 724 case AMDGPU::V_CNDMASK_B32_dpp8_gfx11: 725 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11: 726 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11: 727 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11: 728 729 case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7: 730 case AMDGPU::V_CNDMASK_B32_e32_vi: 731 if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(), 732 AMDGPU::OpName::src1)) 733 printDefaultVccOperand(OpNo == 0, STI, O); 734 break; 735 } 736 737 if (Desc.TSFlags & SIInstrFlags::MTBUF) { 738 int SOffsetIdx = 739 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset); 740 assert(SOffsetIdx != -1); 741 if ((int)OpNo == SOffsetIdx) 742 printSymbolicFormat(MI, STI, O); 743 } 744 } 745 746 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI, 747 unsigned OpNo, 748 const MCSubtargetInfo &STI, 749 raw_ostream &O) { 750 const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 751 if (needsImpliedVcc(Desc, OpNo)) 752 printDefaultVccOperand(true, STI, O); 753 754 unsigned InputModifiers = MI->getOperand(OpNo).getImm(); 755 756 // Use 'neg(...)' instead of '-' to avoid ambiguity. 757 // This is important for integer literals because 758 // -1 is not the same value as neg(1). 759 bool NegMnemo = false; 760 761 if (InputModifiers & SISrcMods::NEG) { 762 if (OpNo + 1 < MI->getNumOperands() && 763 (InputModifiers & SISrcMods::ABS) == 0) { 764 const MCOperand &Op = MI->getOperand(OpNo + 1); 765 NegMnemo = Op.isImm() || Op.isDFPImm(); 766 } 767 if (NegMnemo) { 768 O << "neg("; 769 } else { 770 O << '-'; 771 } 772 } 773 774 if (InputModifiers & SISrcMods::ABS) 775 O << '|'; 776 printRegularOperand(MI, OpNo + 1, STI, O); 777 if (InputModifiers & SISrcMods::ABS) 778 O << '|'; 779 780 if (NegMnemo) { 781 O << ')'; 782 } 783 784 // Print default vcc/vcc_lo operand of VOP2b. 785 switch (MI->getOpcode()) { 786 default: 787 break; 788 789 case AMDGPU::V_CNDMASK_B32_sdwa_gfx10: 790 case AMDGPU::V_CNDMASK_B32_dpp_gfx10: 791 case AMDGPU::V_CNDMASK_B32_dpp_gfx11: 792 if ((int)OpNo + 1 == 793 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::src1)) 794 printDefaultVccOperand(OpNo == 0, STI, O); 795 break; 796 } 797 } 798 799 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI, 800 unsigned OpNo, 801 const MCSubtargetInfo &STI, 802 raw_ostream &O) { 803 const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 804 if (needsImpliedVcc(Desc, OpNo)) 805 printDefaultVccOperand(true, STI, O); 806 807 unsigned InputModifiers = MI->getOperand(OpNo).getImm(); 808 if (InputModifiers & SISrcMods::SEXT) 809 O << "sext("; 810 printRegularOperand(MI, OpNo + 1, STI, O); 811 if (InputModifiers & SISrcMods::SEXT) 812 O << ')'; 813 814 // Print default vcc/vcc_lo operand of VOP2b. 815 switch (MI->getOpcode()) { 816 default: break; 817 818 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10: 819 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10: 820 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10: 821 if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(), 822 AMDGPU::OpName::src1)) 823 printDefaultVccOperand(OpNo == 0, STI, O); 824 break; 825 } 826 } 827 828 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo, 829 const MCSubtargetInfo &STI, 830 raw_ostream &O) { 831 if (!AMDGPU::isGFX10Plus(STI)) 832 llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10"); 833 834 unsigned Imm = MI->getOperand(OpNo).getImm(); 835 O << "dpp8:[" << formatDec(Imm & 0x7); 836 for (size_t i = 1; i < 8; ++i) { 837 O << ',' << formatDec((Imm >> (3 * i)) & 0x7); 838 } 839 O << ']'; 840 } 841 842 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo, 843 const MCSubtargetInfo &STI, 844 raw_ostream &O) { 845 using namespace AMDGPU::DPP; 846 847 unsigned Imm = MI->getOperand(OpNo).getImm(); 848 const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 849 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), 850 AMDGPU::OpName::src0); 851 852 if (Src0Idx >= 0 && 853 Desc.operands()[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID && 854 !AMDGPU::isLegal64BitDPPControl(Imm)) { 855 O << " /* 64 bit dpp only supports row_newbcast */"; 856 return; 857 } else if (Imm <= DppCtrl::QUAD_PERM_LAST) { 858 O << "quad_perm:["; 859 O << formatDec(Imm & 0x3) << ','; 860 O << formatDec((Imm & 0xc) >> 2) << ','; 861 O << formatDec((Imm & 0x30) >> 4) << ','; 862 O << formatDec((Imm & 0xc0) >> 6) << ']'; 863 } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) && 864 (Imm <= DppCtrl::ROW_SHL_LAST)) { 865 O << "row_shl:"; 866 printU4ImmDecOperand(MI, OpNo, O); 867 } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) && 868 (Imm <= DppCtrl::ROW_SHR_LAST)) { 869 O << "row_shr:"; 870 printU4ImmDecOperand(MI, OpNo, O); 871 } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) && 872 (Imm <= DppCtrl::ROW_ROR_LAST)) { 873 O << "row_ror:"; 874 printU4ImmDecOperand(MI, OpNo, O); 875 } else if (Imm == DppCtrl::WAVE_SHL1) { 876 if (AMDGPU::isGFX10Plus(STI)) { 877 O << "/* wave_shl is not supported starting from GFX10 */"; 878 return; 879 } 880 O << "wave_shl:1"; 881 } else if (Imm == DppCtrl::WAVE_ROL1) { 882 if (AMDGPU::isGFX10Plus(STI)) { 883 O << "/* wave_rol is not supported starting from GFX10 */"; 884 return; 885 } 886 O << "wave_rol:1"; 887 } else if (Imm == DppCtrl::WAVE_SHR1) { 888 if (AMDGPU::isGFX10Plus(STI)) { 889 O << "/* wave_shr is not supported starting from GFX10 */"; 890 return; 891 } 892 O << "wave_shr:1"; 893 } else if (Imm == DppCtrl::WAVE_ROR1) { 894 if (AMDGPU::isGFX10Plus(STI)) { 895 O << "/* wave_ror is not supported starting from GFX10 */"; 896 return; 897 } 898 O << "wave_ror:1"; 899 } else if (Imm == DppCtrl::ROW_MIRROR) { 900 O << "row_mirror"; 901 } else if (Imm == DppCtrl::ROW_HALF_MIRROR) { 902 O << "row_half_mirror"; 903 } else if (Imm == DppCtrl::BCAST15) { 904 if (AMDGPU::isGFX10Plus(STI)) { 905 O << "/* row_bcast is not supported starting from GFX10 */"; 906 return; 907 } 908 O << "row_bcast:15"; 909 } else if (Imm == DppCtrl::BCAST31) { 910 if (AMDGPU::isGFX10Plus(STI)) { 911 O << "/* row_bcast is not supported starting from GFX10 */"; 912 return; 913 } 914 O << "row_bcast:31"; 915 } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) && 916 (Imm <= DppCtrl::ROW_SHARE_LAST)) { 917 if (AMDGPU::isGFX90A(STI)) { 918 O << "row_newbcast:"; 919 } else if (AMDGPU::isGFX10Plus(STI)) { 920 O << "row_share:"; 921 } else { 922 O << " /* row_newbcast/row_share is not supported on ASICs earlier " 923 "than GFX90A/GFX10 */"; 924 return; 925 } 926 printU4ImmDecOperand(MI, OpNo, O); 927 } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) && 928 (Imm <= DppCtrl::ROW_XMASK_LAST)) { 929 if (!AMDGPU::isGFX10Plus(STI)) { 930 O << "/* row_xmask is not supported on ASICs earlier than GFX10 */"; 931 return; 932 } 933 O << "row_xmask:"; 934 printU4ImmDecOperand(MI, OpNo, O); 935 } else { 936 O << "/* Invalid dpp_ctrl value */"; 937 } 938 } 939 940 void AMDGPUInstPrinter::printDppRowMask(const MCInst *MI, unsigned OpNo, 941 const MCSubtargetInfo &STI, 942 raw_ostream &O) { 943 O << " row_mask:"; 944 printU4ImmOperand(MI, OpNo, STI, O); 945 } 946 947 void AMDGPUInstPrinter::printDppBankMask(const MCInst *MI, unsigned OpNo, 948 const MCSubtargetInfo &STI, 949 raw_ostream &O) { 950 O << " bank_mask:"; 951 printU4ImmOperand(MI, OpNo, STI, O); 952 } 953 954 void AMDGPUInstPrinter::printDppBoundCtrl(const MCInst *MI, unsigned OpNo, 955 const MCSubtargetInfo &STI, 956 raw_ostream &O) { 957 unsigned Imm = MI->getOperand(OpNo).getImm(); 958 if (Imm) { 959 O << " bound_ctrl:1"; 960 } 961 } 962 963 void AMDGPUInstPrinter::printDppFI(const MCInst *MI, unsigned OpNo, 964 const MCSubtargetInfo &STI, raw_ostream &O) { 965 using namespace llvm::AMDGPU::DPP; 966 unsigned Imm = MI->getOperand(OpNo).getImm(); 967 if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) { 968 O << " fi:1"; 969 } 970 } 971 972 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo, 973 raw_ostream &O) { 974 using namespace llvm::AMDGPU::SDWA; 975 976 unsigned Imm = MI->getOperand(OpNo).getImm(); 977 switch (Imm) { 978 case SdwaSel::BYTE_0: O << "BYTE_0"; break; 979 case SdwaSel::BYTE_1: O << "BYTE_1"; break; 980 case SdwaSel::BYTE_2: O << "BYTE_2"; break; 981 case SdwaSel::BYTE_3: O << "BYTE_3"; break; 982 case SdwaSel::WORD_0: O << "WORD_0"; break; 983 case SdwaSel::WORD_1: O << "WORD_1"; break; 984 case SdwaSel::DWORD: O << "DWORD"; break; 985 default: llvm_unreachable("Invalid SDWA data select operand"); 986 } 987 } 988 989 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo, 990 const MCSubtargetInfo &STI, 991 raw_ostream &O) { 992 O << "dst_sel:"; 993 printSDWASel(MI, OpNo, O); 994 } 995 996 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo, 997 const MCSubtargetInfo &STI, 998 raw_ostream &O) { 999 O << "src0_sel:"; 1000 printSDWASel(MI, OpNo, O); 1001 } 1002 1003 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo, 1004 const MCSubtargetInfo &STI, 1005 raw_ostream &O) { 1006 O << "src1_sel:"; 1007 printSDWASel(MI, OpNo, O); 1008 } 1009 1010 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo, 1011 const MCSubtargetInfo &STI, 1012 raw_ostream &O) { 1013 using namespace llvm::AMDGPU::SDWA; 1014 1015 O << "dst_unused:"; 1016 unsigned Imm = MI->getOperand(OpNo).getImm(); 1017 switch (Imm) { 1018 case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break; 1019 case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break; 1020 case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break; 1021 default: llvm_unreachable("Invalid SDWA dest_unused operand"); 1022 } 1023 } 1024 1025 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo, 1026 const MCSubtargetInfo &STI, raw_ostream &O, 1027 unsigned N) { 1028 unsigned Opc = MI->getOpcode(); 1029 int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); 1030 unsigned En = MI->getOperand(EnIdx).getImm(); 1031 1032 int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); 1033 1034 // If compr is set, print as src0, src0, src1, src1 1035 if (MI->getOperand(ComprIdx).getImm()) 1036 OpNo = OpNo - N + N / 2; 1037 1038 if (En & (1 << N)) 1039 printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI); 1040 else 1041 O << "off"; 1042 } 1043 1044 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo, 1045 const MCSubtargetInfo &STI, 1046 raw_ostream &O) { 1047 printExpSrcN(MI, OpNo, STI, O, 0); 1048 } 1049 1050 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo, 1051 const MCSubtargetInfo &STI, 1052 raw_ostream &O) { 1053 printExpSrcN(MI, OpNo, STI, O, 1); 1054 } 1055 1056 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo, 1057 const MCSubtargetInfo &STI, 1058 raw_ostream &O) { 1059 printExpSrcN(MI, OpNo, STI, O, 2); 1060 } 1061 1062 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo, 1063 const MCSubtargetInfo &STI, 1064 raw_ostream &O) { 1065 printExpSrcN(MI, OpNo, STI, O, 3); 1066 } 1067 1068 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo, 1069 const MCSubtargetInfo &STI, 1070 raw_ostream &O) { 1071 using namespace llvm::AMDGPU::Exp; 1072 1073 // This is really a 6 bit field. 1074 unsigned Id = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1); 1075 1076 int Index; 1077 StringRef TgtName; 1078 if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) { 1079 O << ' ' << TgtName; 1080 if (Index >= 0) 1081 O << Index; 1082 } else { 1083 O << " invalid_target_" << Id; 1084 } 1085 } 1086 1087 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod, 1088 bool IsPacked, bool HasDstSel) { 1089 int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1); 1090 1091 for (int I = 0; I < NumOps; ++I) { 1092 if (!!(Ops[I] & Mod) != DefaultValue) 1093 return false; 1094 } 1095 1096 if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0) 1097 return false; 1098 1099 return true; 1100 } 1101 1102 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI, 1103 StringRef Name, 1104 unsigned Mod, 1105 raw_ostream &O) { 1106 unsigned Opc = MI->getOpcode(); 1107 int NumOps = 0; 1108 int Ops[3]; 1109 1110 for (int OpName : { AMDGPU::OpName::src0_modifiers, 1111 AMDGPU::OpName::src1_modifiers, 1112 AMDGPU::OpName::src2_modifiers }) { 1113 int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName); 1114 if (Idx == -1) 1115 break; 1116 1117 Ops[NumOps++] = MI->getOperand(Idx).getImm(); 1118 } 1119 1120 const bool HasDstSel = 1121 NumOps > 0 && 1122 Mod == SISrcMods::OP_SEL_0 && 1123 MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL; 1124 1125 const bool IsPacked = 1126 MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked; 1127 1128 if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel)) 1129 return; 1130 1131 O << Name; 1132 for (int I = 0; I < NumOps; ++I) { 1133 if (I != 0) 1134 O << ','; 1135 1136 O << !!(Ops[I] & Mod); 1137 } 1138 1139 if (HasDstSel) { 1140 O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL); 1141 } 1142 1143 O << ']'; 1144 } 1145 1146 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned, 1147 const MCSubtargetInfo &STI, 1148 raw_ostream &O) { 1149 unsigned Opc = MI->getOpcode(); 1150 if (isPermlane16(Opc)) { 1151 auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); 1152 auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers); 1153 unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0); 1154 unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0); 1155 if (FI || BC) 1156 O << " op_sel:[" << FI << ',' << BC << ']'; 1157 return; 1158 } 1159 1160 printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O); 1161 } 1162 1163 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo, 1164 const MCSubtargetInfo &STI, 1165 raw_ostream &O) { 1166 printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O); 1167 } 1168 1169 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo, 1170 const MCSubtargetInfo &STI, 1171 raw_ostream &O) { 1172 printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O); 1173 } 1174 1175 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo, 1176 const MCSubtargetInfo &STI, 1177 raw_ostream &O) { 1178 printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O); 1179 } 1180 1181 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum, 1182 const MCSubtargetInfo &STI, 1183 raw_ostream &O) { 1184 unsigned Imm = MI->getOperand(OpNum).getImm(); 1185 switch (Imm) { 1186 case 0: 1187 O << "p10"; 1188 break; 1189 case 1: 1190 O << "p20"; 1191 break; 1192 case 2: 1193 O << "p0"; 1194 break; 1195 default: 1196 O << "invalid_param_" << Imm; 1197 } 1198 } 1199 1200 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum, 1201 const MCSubtargetInfo &STI, 1202 raw_ostream &O) { 1203 unsigned Attr = MI->getOperand(OpNum).getImm(); 1204 O << "attr" << Attr; 1205 } 1206 1207 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum, 1208 const MCSubtargetInfo &STI, 1209 raw_ostream &O) { 1210 unsigned Chan = MI->getOperand(OpNum).getImm(); 1211 O << '.' << "xyzw"[Chan & 0x3]; 1212 } 1213 1214 void AMDGPUInstPrinter::printGPRIdxMode(const MCInst *MI, unsigned OpNo, 1215 const MCSubtargetInfo &STI, 1216 raw_ostream &O) { 1217 using namespace llvm::AMDGPU::VGPRIndexMode; 1218 unsigned Val = MI->getOperand(OpNo).getImm(); 1219 1220 if ((Val & ~ENABLE_MASK) != 0) { 1221 O << formatHex(static_cast<uint64_t>(Val)); 1222 } else { 1223 O << "gpr_idx("; 1224 bool NeedComma = false; 1225 for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) { 1226 if (Val & (1 << ModeId)) { 1227 if (NeedComma) 1228 O << ','; 1229 O << IdSymbolic[ModeId]; 1230 NeedComma = true; 1231 } 1232 } 1233 O << ')'; 1234 } 1235 } 1236 1237 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, 1238 const MCSubtargetInfo &STI, 1239 raw_ostream &O) { 1240 printRegularOperand(MI, OpNo, STI, O); 1241 O << ", "; 1242 printRegularOperand(MI, OpNo + 1, STI, O); 1243 } 1244 1245 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo, 1246 raw_ostream &O, StringRef Asm, 1247 StringRef Default) { 1248 const MCOperand &Op = MI->getOperand(OpNo); 1249 assert(Op.isImm()); 1250 if (Op.getImm() == 1) { 1251 O << Asm; 1252 } else { 1253 O << Default; 1254 } 1255 } 1256 1257 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo, 1258 raw_ostream &O, char Asm) { 1259 const MCOperand &Op = MI->getOperand(OpNo); 1260 assert(Op.isImm()); 1261 if (Op.getImm() == 1) 1262 O << Asm; 1263 } 1264 1265 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo, 1266 const MCSubtargetInfo &STI, 1267 raw_ostream &O) { 1268 int Imm = MI->getOperand(OpNo).getImm(); 1269 if (Imm == SIOutMods::MUL2) 1270 O << " mul:2"; 1271 else if (Imm == SIOutMods::MUL4) 1272 O << " mul:4"; 1273 else if (Imm == SIOutMods::DIV2) 1274 O << " div:2"; 1275 } 1276 1277 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo, 1278 const MCSubtargetInfo &STI, 1279 raw_ostream &O) { 1280 using namespace llvm::AMDGPU::SendMsg; 1281 1282 const unsigned Imm16 = MI->getOperand(OpNo).getImm(); 1283 1284 uint16_t MsgId; 1285 uint16_t OpId; 1286 uint16_t StreamId; 1287 decodeMsg(Imm16, MsgId, OpId, StreamId, STI); 1288 1289 StringRef MsgName = getMsgName(MsgId, STI); 1290 1291 if (!MsgName.empty() && isValidMsgOp(MsgId, OpId, STI) && 1292 isValidMsgStream(MsgId, OpId, StreamId, STI)) { 1293 O << "sendmsg(" << MsgName; 1294 if (msgRequiresOp(MsgId, STI)) { 1295 O << ", " << getMsgOpName(MsgId, OpId, STI); 1296 if (msgSupportsStream(MsgId, OpId, STI)) { 1297 O << ", " << StreamId; 1298 } 1299 } 1300 O << ')'; 1301 } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) { 1302 O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')'; 1303 } else { 1304 O << Imm16; // Unknown imm16 code. 1305 } 1306 } 1307 1308 static void printSwizzleBitmask(const uint16_t AndMask, 1309 const uint16_t OrMask, 1310 const uint16_t XorMask, 1311 raw_ostream &O) { 1312 using namespace llvm::AMDGPU::Swizzle; 1313 1314 uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask; 1315 uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask; 1316 1317 O << "\""; 1318 1319 for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) { 1320 uint16_t p0 = Probe0 & Mask; 1321 uint16_t p1 = Probe1 & Mask; 1322 1323 if (p0 == p1) { 1324 if (p0 == 0) { 1325 O << "0"; 1326 } else { 1327 O << "1"; 1328 } 1329 } else { 1330 if (p0 == 0) { 1331 O << "p"; 1332 } else { 1333 O << "i"; 1334 } 1335 } 1336 } 1337 1338 O << "\""; 1339 } 1340 1341 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo, 1342 const MCSubtargetInfo &STI, 1343 raw_ostream &O) { 1344 using namespace llvm::AMDGPU::Swizzle; 1345 1346 uint16_t Imm = MI->getOperand(OpNo).getImm(); 1347 if (Imm == 0) { 1348 return; 1349 } 1350 1351 O << " offset:"; 1352 1353 if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) { 1354 1355 O << "swizzle(" << IdSymbolic[ID_QUAD_PERM]; 1356 for (unsigned I = 0; I < LANE_NUM; ++I) { 1357 O << ","; 1358 O << formatDec(Imm & LANE_MASK); 1359 Imm >>= LANE_SHIFT; 1360 } 1361 O << ")"; 1362 1363 } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) { 1364 1365 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK; 1366 uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK; 1367 uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK; 1368 1369 if (AndMask == BITMASK_MAX && OrMask == 0 && llvm::popcount(XorMask) == 1) { 1370 1371 O << "swizzle(" << IdSymbolic[ID_SWAP]; 1372 O << ","; 1373 O << formatDec(XorMask); 1374 O << ")"; 1375 1376 } else if (AndMask == BITMASK_MAX && OrMask == 0 && XorMask > 0 && 1377 isPowerOf2_64(XorMask + 1)) { 1378 1379 O << "swizzle(" << IdSymbolic[ID_REVERSE]; 1380 O << ","; 1381 O << formatDec(XorMask + 1); 1382 O << ")"; 1383 1384 } else { 1385 1386 uint16_t GroupSize = BITMASK_MAX - AndMask + 1; 1387 if (GroupSize > 1 && 1388 isPowerOf2_64(GroupSize) && 1389 OrMask < GroupSize && 1390 XorMask == 0) { 1391 1392 O << "swizzle(" << IdSymbolic[ID_BROADCAST]; 1393 O << ","; 1394 O << formatDec(GroupSize); 1395 O << ","; 1396 O << formatDec(OrMask); 1397 O << ")"; 1398 1399 } else { 1400 O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM]; 1401 O << ","; 1402 printSwizzleBitmask(AndMask, OrMask, XorMask, O); 1403 O << ")"; 1404 } 1405 } 1406 } else { 1407 printU16ImmDecOperand(MI, OpNo, O); 1408 } 1409 } 1410 1411 void AMDGPUInstPrinter::printSWaitCnt(const MCInst *MI, unsigned OpNo, 1412 const MCSubtargetInfo &STI, 1413 raw_ostream &O) { 1414 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU()); 1415 1416 unsigned SImm16 = MI->getOperand(OpNo).getImm(); 1417 unsigned Vmcnt, Expcnt, Lgkmcnt; 1418 decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt); 1419 1420 bool IsDefaultVmcnt = Vmcnt == getVmcntBitMask(ISA); 1421 bool IsDefaultExpcnt = Expcnt == getExpcntBitMask(ISA); 1422 bool IsDefaultLgkmcnt = Lgkmcnt == getLgkmcntBitMask(ISA); 1423 bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt; 1424 1425 bool NeedSpace = false; 1426 1427 if (!IsDefaultVmcnt || PrintAll) { 1428 O << "vmcnt(" << Vmcnt << ')'; 1429 NeedSpace = true; 1430 } 1431 1432 if (!IsDefaultExpcnt || PrintAll) { 1433 if (NeedSpace) 1434 O << ' '; 1435 O << "expcnt(" << Expcnt << ')'; 1436 NeedSpace = true; 1437 } 1438 1439 if (!IsDefaultLgkmcnt || PrintAll) { 1440 if (NeedSpace) 1441 O << ' '; 1442 O << "lgkmcnt(" << Lgkmcnt << ')'; 1443 } 1444 } 1445 1446 void AMDGPUInstPrinter::printDepCtr(const MCInst *MI, unsigned OpNo, 1447 const MCSubtargetInfo &STI, 1448 raw_ostream &O) { 1449 using namespace llvm::AMDGPU::DepCtr; 1450 1451 uint64_t Imm16 = MI->getOperand(OpNo).getImm() & 0xffff; 1452 1453 bool HasNonDefaultVal = false; 1454 if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) { 1455 int Id = 0; 1456 StringRef Name; 1457 unsigned Val; 1458 bool IsDefault; 1459 bool NeedSpace = false; 1460 while (decodeDepCtr(Imm16, Id, Name, Val, IsDefault, STI)) { 1461 if (!IsDefault || !HasNonDefaultVal) { 1462 if (NeedSpace) 1463 O << ' '; 1464 O << Name << '(' << Val << ')'; 1465 NeedSpace = true; 1466 } 1467 } 1468 } else { 1469 O << formatHex(Imm16); 1470 } 1471 } 1472 1473 void AMDGPUInstPrinter::printSDelayALU(const MCInst *MI, unsigned OpNo, 1474 const MCSubtargetInfo &STI, 1475 raw_ostream &O) { 1476 const char *BadInstId = "/* invalid instid value */"; 1477 static const std::array<const char *, 12> InstIds = { 1478 "NO_DEP", "VALU_DEP_1", "VALU_DEP_2", 1479 "VALU_DEP_3", "VALU_DEP_4", "TRANS32_DEP_1", 1480 "TRANS32_DEP_2", "TRANS32_DEP_3", "FMA_ACCUM_CYCLE_1", 1481 "SALU_CYCLE_1", "SALU_CYCLE_2", "SALU_CYCLE_3"}; 1482 1483 const char *BadInstSkip = "/* invalid instskip value */"; 1484 static const std::array<const char *, 6> InstSkips = { 1485 "SAME", "NEXT", "SKIP_1", "SKIP_2", "SKIP_3", "SKIP_4"}; 1486 1487 unsigned SImm16 = MI->getOperand(OpNo).getImm(); 1488 const char *Prefix = ""; 1489 1490 unsigned Value = SImm16 & 0xF; 1491 if (Value) { 1492 const char *Name = Value < InstIds.size() ? InstIds[Value] : BadInstId; 1493 O << Prefix << "instid0(" << Name << ')'; 1494 Prefix = " | "; 1495 } 1496 1497 Value = (SImm16 >> 4) & 7; 1498 if (Value) { 1499 const char *Name = 1500 Value < InstSkips.size() ? InstSkips[Value] : BadInstSkip; 1501 O << Prefix << "instskip(" << Name << ')'; 1502 Prefix = " | "; 1503 } 1504 1505 Value = (SImm16 >> 7) & 0xF; 1506 if (Value) { 1507 const char *Name = Value < InstIds.size() ? InstIds[Value] : BadInstId; 1508 O << Prefix << "instid1(" << Name << ')'; 1509 Prefix = " | "; 1510 } 1511 1512 if (!*Prefix) 1513 O << "0"; 1514 } 1515 1516 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo, 1517 const MCSubtargetInfo &STI, raw_ostream &O) { 1518 unsigned Id; 1519 unsigned Offset; 1520 unsigned Width; 1521 1522 using namespace llvm::AMDGPU::Hwreg; 1523 unsigned Val = MI->getOperand(OpNo).getImm(); 1524 decodeHwreg(Val, Id, Offset, Width); 1525 StringRef HwRegName = getHwreg(Id, STI); 1526 1527 O << "hwreg("; 1528 if (!HwRegName.empty()) { 1529 O << HwRegName; 1530 } else { 1531 O << Id; 1532 } 1533 if (Width != WIDTH_DEFAULT_ || Offset != OFFSET_DEFAULT_) { 1534 O << ", " << Offset << ", " << Width; 1535 } 1536 O << ')'; 1537 } 1538 1539 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo, 1540 const MCSubtargetInfo &STI, 1541 raw_ostream &O) { 1542 uint16_t Imm = MI->getOperand(OpNo).getImm(); 1543 if (Imm == 0) { 1544 return; 1545 } 1546 1547 O << ' ' << formatDec(Imm); 1548 } 1549 1550 #include "AMDGPUGenAsmWriter.inc" 1551