1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 // \file 8 //===----------------------------------------------------------------------===// 9 10 #include "AMDGPUInstPrinter.h" 11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 12 #include "SIDefines.h" 13 #include "Utils/AMDGPUAsmUtils.h" 14 #include "Utils/AMDGPUBaseInfo.h" 15 #include "llvm/MC/MCExpr.h" 16 #include "llvm/MC/MCInst.h" 17 #include "llvm/MC/MCInstrDesc.h" 18 #include "llvm/MC/MCInstrInfo.h" 19 #include "llvm/MC/MCSubtargetInfo.h" 20 #include "llvm/Support/CommandLine.h" 21 #include "llvm/Support/TargetParser.h" 22 23 using namespace llvm; 24 using namespace llvm::AMDGPU; 25 26 static cl::opt<bool> Keep16BitSuffixes( 27 "amdgpu-keep-16-bit-reg-suffixes", 28 cl::desc("Keep .l and .h suffixes in asm for debugging purposes"), 29 cl::init(false), 30 cl::ReallyHidden); 31 32 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 33 // FIXME: The current implementation of 34 // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this 35 // as an integer or we provide a name which represents a physical register. 36 // For CFI instructions we really want to emit a name for the DWARF register 37 // instead, because there may be multiple DWARF registers corresponding to a 38 // single physical register. One case where this problem manifests is with 39 // wave32/wave64 where using the physical register name is ambiguous: if we 40 // write e.g. `.cfi_undefined v0` we lose information about the wavefront 41 // size which we need to encode the register in the final DWARF. Ideally we 42 // would extend MC to support parsing DWARF register names so we could do 43 // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with 44 // non-pretty DWARF register names in assembly text. 45 OS << RegNo; 46 } 47 48 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address, 49 StringRef Annot, const MCSubtargetInfo &STI, 50 raw_ostream &OS) { 51 OS.flush(); 52 printInstruction(MI, Address, STI, OS); 53 printAnnotation(OS, Annot); 54 } 55 56 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo, 57 const MCSubtargetInfo &STI, 58 raw_ostream &O) { 59 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); 60 } 61 62 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo, 63 raw_ostream &O) { 64 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); 65 } 66 67 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, 68 const MCSubtargetInfo &STI, 69 raw_ostream &O) { 70 // It's possible to end up with a 32-bit literal used with a 16-bit operand 71 // with ignored high bits. Print as 32-bit anyway in that case. 72 int64_t Imm = MI->getOperand(OpNo).getImm(); 73 if (isInt<16>(Imm) || isUInt<16>(Imm)) 74 O << formatHex(static_cast<uint64_t>(Imm & 0xffff)); 75 else 76 printU32ImmOperand(MI, OpNo, STI, O); 77 } 78 79 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, 80 raw_ostream &O) { 81 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf); 82 } 83 84 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, 85 raw_ostream &O) { 86 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); 87 } 88 89 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, 90 raw_ostream &O) { 91 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); 92 } 93 94 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo, 95 const MCSubtargetInfo &STI, 96 raw_ostream &O) { 97 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); 98 } 99 100 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo, 101 raw_ostream &O, StringRef BitName) { 102 if (MI->getOperand(OpNo).getImm()) { 103 O << ' ' << BitName; 104 } 105 } 106 107 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo, 108 raw_ostream &O) { 109 printNamedBit(MI, OpNo, O, "offen"); 110 } 111 112 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo, 113 raw_ostream &O) { 114 printNamedBit(MI, OpNo, O, "idxen"); 115 } 116 117 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo, 118 raw_ostream &O) { 119 printNamedBit(MI, OpNo, O, "addr64"); 120 } 121 122 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo, 123 raw_ostream &O) { 124 if (MI->getOperand(OpNo).getImm()) { 125 O << " offset:"; 126 printU16ImmDecOperand(MI, OpNo, O); 127 } 128 } 129 130 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo, 131 const MCSubtargetInfo &STI, 132 raw_ostream &O) { 133 uint16_t Imm = MI->getOperand(OpNo).getImm(); 134 if (Imm != 0) { 135 O << " offset:"; 136 printU16ImmDecOperand(MI, OpNo, O); 137 } 138 } 139 140 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo, 141 const MCSubtargetInfo &STI, 142 raw_ostream &O) { 143 uint16_t Imm = MI->getOperand(OpNo).getImm(); 144 if (Imm != 0) { 145 O << " offset:"; 146 147 const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 148 bool IsFlatSeg = !(Desc.TSFlags & 149 (SIInstrFlags::IsFlatGlobal | SIInstrFlags::IsFlatScratch)); 150 151 if (IsFlatSeg) { // Unsigned offset 152 printU16ImmDecOperand(MI, OpNo, O); 153 } else { // Signed offset 154 if (AMDGPU::isGFX10Plus(STI)) { 155 O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm())); 156 } else { 157 O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm())); 158 } 159 } 160 } 161 } 162 163 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo, 164 const MCSubtargetInfo &STI, 165 raw_ostream &O) { 166 if (MI->getOperand(OpNo).getImm()) { 167 O << " offset0:"; 168 printU8ImmDecOperand(MI, OpNo, O); 169 } 170 } 171 172 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo, 173 const MCSubtargetInfo &STI, 174 raw_ostream &O) { 175 if (MI->getOperand(OpNo).getImm()) { 176 O << " offset1:"; 177 printU8ImmDecOperand(MI, OpNo, O); 178 } 179 } 180 181 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo, 182 const MCSubtargetInfo &STI, 183 raw_ostream &O) { 184 printU32ImmOperand(MI, OpNo, STI, O); 185 } 186 187 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo, 188 const MCSubtargetInfo &STI, 189 raw_ostream &O) { 190 O << formatHex(MI->getOperand(OpNo).getImm()); 191 } 192 193 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo, 194 const MCSubtargetInfo &STI, 195 raw_ostream &O) { 196 printU32ImmOperand(MI, OpNo, STI, O); 197 } 198 199 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo, 200 const MCSubtargetInfo &STI, raw_ostream &O) { 201 printNamedBit(MI, OpNo, O, "gds"); 202 } 203 204 void AMDGPUInstPrinter::printDLC(const MCInst *MI, unsigned OpNo, 205 const MCSubtargetInfo &STI, raw_ostream &O) { 206 if (AMDGPU::isGFX10Plus(STI)) 207 printNamedBit(MI, OpNo, O, "dlc"); 208 } 209 210 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo, 211 const MCSubtargetInfo &STI, raw_ostream &O) { 212 printNamedBit(MI, OpNo, O, "glc"); 213 } 214 215 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo, 216 const MCSubtargetInfo &STI, raw_ostream &O) { 217 printNamedBit(MI, OpNo, O, "slc"); 218 } 219 220 void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo, 221 const MCSubtargetInfo &STI, raw_ostream &O) { 222 } 223 224 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo, 225 const MCSubtargetInfo &STI, raw_ostream &O) { 226 printNamedBit(MI, OpNo, O, "tfe"); 227 } 228 229 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo, 230 const MCSubtargetInfo &STI, raw_ostream &O) { 231 if (MI->getOperand(OpNo).getImm()) { 232 O << " dmask:"; 233 printU16ImmOperand(MI, OpNo, STI, O); 234 } 235 } 236 237 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo, 238 const MCSubtargetInfo &STI, raw_ostream &O) { 239 unsigned Dim = MI->getOperand(OpNo).getImm(); 240 O << " dim:SQ_RSRC_IMG_"; 241 242 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); 243 if (DimInfo) 244 O << DimInfo->AsmSuffix; 245 else 246 O << Dim; 247 } 248 249 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo, 250 const MCSubtargetInfo &STI, raw_ostream &O) { 251 printNamedBit(MI, OpNo, O, "unorm"); 252 } 253 254 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo, 255 const MCSubtargetInfo &STI, raw_ostream &O) { 256 printNamedBit(MI, OpNo, O, "da"); 257 } 258 259 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo, 260 const MCSubtargetInfo &STI, raw_ostream &O) { 261 if (STI.hasFeature(AMDGPU::FeatureR128A16)) 262 printNamedBit(MI, OpNo, O, "a16"); 263 else 264 printNamedBit(MI, OpNo, O, "r128"); 265 } 266 267 void AMDGPUInstPrinter::printGFX10A16(const MCInst *MI, unsigned OpNo, 268 const MCSubtargetInfo &STI, raw_ostream &O) { 269 printNamedBit(MI, OpNo, O, "a16"); 270 } 271 272 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo, 273 const MCSubtargetInfo &STI, raw_ostream &O) { 274 printNamedBit(MI, OpNo, O, "lwe"); 275 } 276 277 void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo, 278 const MCSubtargetInfo &STI, raw_ostream &O) { 279 printNamedBit(MI, OpNo, O, "d16"); 280 } 281 282 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo, 283 const MCSubtargetInfo &STI, 284 raw_ostream &O) { 285 printNamedBit(MI, OpNo, O, "compr"); 286 } 287 288 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo, 289 const MCSubtargetInfo &STI, 290 raw_ostream &O) { 291 printNamedBit(MI, OpNo, O, "vm"); 292 } 293 294 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo, 295 const MCSubtargetInfo &STI, 296 raw_ostream &O) { 297 } 298 299 void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI, 300 const MCSubtargetInfo &STI, 301 raw_ostream &O) { 302 using namespace llvm::AMDGPU::MTBUFFormat; 303 304 int OpNo = 305 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format); 306 assert(OpNo != -1); 307 308 unsigned Val = MI->getOperand(OpNo).getImm(); 309 if (AMDGPU::isGFX10Plus(STI)) { 310 if (Val == UFMT_DEFAULT) 311 return; 312 if (isValidUnifiedFormat(Val)) { 313 O << " format:[" << getUnifiedFormatName(Val) << ']'; 314 } else { 315 O << " format:" << Val; 316 } 317 } else { 318 if (Val == DFMT_NFMT_DEFAULT) 319 return; 320 if (isValidDfmtNfmt(Val, STI)) { 321 unsigned Dfmt; 322 unsigned Nfmt; 323 decodeDfmtNfmt(Val, Dfmt, Nfmt); 324 O << " format:["; 325 if (Dfmt != DFMT_DEFAULT) { 326 O << getDfmtName(Dfmt); 327 if (Nfmt != NFMT_DEFAULT) { 328 O << ','; 329 } 330 } 331 if (Nfmt != NFMT_DEFAULT) { 332 O << getNfmtName(Nfmt, STI); 333 } 334 O << ']'; 335 } else { 336 O << " format:" << Val; 337 } 338 } 339 } 340 341 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O, 342 const MCRegisterInfo &MRI) { 343 #if !defined(NDEBUG) 344 switch (RegNo) { 345 case AMDGPU::FP_REG: 346 case AMDGPU::SP_REG: 347 case AMDGPU::PRIVATE_RSRC_REG: 348 llvm_unreachable("pseudo-register should not ever be emitted"); 349 case AMDGPU::SCC: 350 llvm_unreachable("pseudo scc should not ever be emitted"); 351 default: 352 break; 353 } 354 #endif 355 356 StringRef RegName(getRegisterName(RegNo)); 357 if (!Keep16BitSuffixes) 358 if (!RegName.consume_back(".l")) 359 RegName.consume_back(".h"); 360 361 O << RegName; 362 } 363 364 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo, 365 const MCSubtargetInfo &STI, raw_ostream &O) { 366 if (OpNo == 0) { 367 if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3) 368 O << "_e64 "; 369 else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP) 370 O << "_dpp "; 371 else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA) 372 O << "_sdwa "; 373 else 374 O << "_e32 "; 375 } 376 377 printOperand(MI, OpNo, STI, O); 378 379 // Print default vcc/vcc_lo operand. 380 switch (MI->getOpcode()) { 381 default: break; 382 383 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10: 384 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10: 385 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: 386 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10: 387 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10: 388 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10: 389 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10: 390 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10: 391 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10: 392 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10: 393 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10: 394 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10: 395 printDefaultVccOperand(1, STI, O); 396 break; 397 } 398 } 399 400 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo, 401 const MCSubtargetInfo &STI, raw_ostream &O) { 402 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI)) 403 O << " "; 404 else 405 O << "_e32 "; 406 407 printOperand(MI, OpNo, STI, O); 408 } 409 410 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm, 411 const MCSubtargetInfo &STI, 412 raw_ostream &O) { 413 int16_t SImm = static_cast<int16_t>(Imm); 414 if (isInlinableIntLiteral(SImm)) { 415 O << SImm; 416 } else { 417 uint64_t Imm16 = static_cast<uint16_t>(Imm); 418 O << formatHex(Imm16); 419 } 420 } 421 422 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm, 423 const MCSubtargetInfo &STI, 424 raw_ostream &O) { 425 int16_t SImm = static_cast<int16_t>(Imm); 426 if (isInlinableIntLiteral(SImm)) { 427 O << SImm; 428 return; 429 } 430 431 if (Imm == 0x3C00) 432 O<< "1.0"; 433 else if (Imm == 0xBC00) 434 O<< "-1.0"; 435 else if (Imm == 0x3800) 436 O<< "0.5"; 437 else if (Imm == 0xB800) 438 O<< "-0.5"; 439 else if (Imm == 0x4000) 440 O<< "2.0"; 441 else if (Imm == 0xC000) 442 O<< "-2.0"; 443 else if (Imm == 0x4400) 444 O<< "4.0"; 445 else if (Imm == 0xC400) 446 O<< "-4.0"; 447 else if (Imm == 0x3118 && 448 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) { 449 O << "0.15915494"; 450 } else { 451 uint64_t Imm16 = static_cast<uint16_t>(Imm); 452 O << formatHex(Imm16); 453 } 454 } 455 456 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm, 457 const MCSubtargetInfo &STI, 458 raw_ostream &O) { 459 uint16_t Lo16 = static_cast<uint16_t>(Imm); 460 printImmediate16(Lo16, STI, O); 461 } 462 463 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, 464 const MCSubtargetInfo &STI, 465 raw_ostream &O) { 466 int32_t SImm = static_cast<int32_t>(Imm); 467 if (SImm >= -16 && SImm <= 64) { 468 O << SImm; 469 return; 470 } 471 472 if (Imm == FloatToBits(0.0f)) 473 O << "0.0"; 474 else if (Imm == FloatToBits(1.0f)) 475 O << "1.0"; 476 else if (Imm == FloatToBits(-1.0f)) 477 O << "-1.0"; 478 else if (Imm == FloatToBits(0.5f)) 479 O << "0.5"; 480 else if (Imm == FloatToBits(-0.5f)) 481 O << "-0.5"; 482 else if (Imm == FloatToBits(2.0f)) 483 O << "2.0"; 484 else if (Imm == FloatToBits(-2.0f)) 485 O << "-2.0"; 486 else if (Imm == FloatToBits(4.0f)) 487 O << "4.0"; 488 else if (Imm == FloatToBits(-4.0f)) 489 O << "-4.0"; 490 else if (Imm == 0x3e22f983 && 491 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) 492 O << "0.15915494"; 493 else 494 O << formatHex(static_cast<uint64_t>(Imm)); 495 } 496 497 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm, 498 const MCSubtargetInfo &STI, 499 raw_ostream &O) { 500 int64_t SImm = static_cast<int64_t>(Imm); 501 if (SImm >= -16 && SImm <= 64) { 502 O << SImm; 503 return; 504 } 505 506 if (Imm == DoubleToBits(0.0)) 507 O << "0.0"; 508 else if (Imm == DoubleToBits(1.0)) 509 O << "1.0"; 510 else if (Imm == DoubleToBits(-1.0)) 511 O << "-1.0"; 512 else if (Imm == DoubleToBits(0.5)) 513 O << "0.5"; 514 else if (Imm == DoubleToBits(-0.5)) 515 O << "-0.5"; 516 else if (Imm == DoubleToBits(2.0)) 517 O << "2.0"; 518 else if (Imm == DoubleToBits(-2.0)) 519 O << "-2.0"; 520 else if (Imm == DoubleToBits(4.0)) 521 O << "4.0"; 522 else if (Imm == DoubleToBits(-4.0)) 523 O << "-4.0"; 524 else if (Imm == 0x3fc45f306dc9c882 && 525 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) 526 O << "0.15915494309189532"; 527 else { 528 assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882); 529 530 // In rare situations, we will have a 32-bit literal in a 64-bit 531 // operand. This is technically allowed for the encoding of s_mov_b64. 532 O << formatHex(static_cast<uint64_t>(Imm)); 533 } 534 } 535 536 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo, 537 const MCSubtargetInfo &STI, 538 raw_ostream &O) { 539 unsigned Imm = MI->getOperand(OpNo).getImm(); 540 if (!Imm) 541 return; 542 543 O << " blgp:" << Imm; 544 } 545 546 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo, 547 const MCSubtargetInfo &STI, 548 raw_ostream &O) { 549 unsigned Imm = MI->getOperand(OpNo).getImm(); 550 if (!Imm) 551 return; 552 553 O << " cbsz:" << Imm; 554 } 555 556 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo, 557 const MCSubtargetInfo &STI, 558 raw_ostream &O) { 559 unsigned Imm = MI->getOperand(OpNo).getImm(); 560 if (!Imm) 561 return; 562 563 O << " abid:" << Imm; 564 } 565 566 void AMDGPUInstPrinter::printDefaultVccOperand(unsigned OpNo, 567 const MCSubtargetInfo &STI, 568 raw_ostream &O) { 569 if (OpNo > 0) 570 O << ", "; 571 printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 572 AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI); 573 if (OpNo == 0) 574 O << ", "; 575 } 576 577 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 578 const MCSubtargetInfo &STI, 579 raw_ostream &O) { 580 // Print default vcc/vcc_lo operand of VOPC. 581 const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 582 if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) && 583 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) || 584 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO))) 585 printDefaultVccOperand(OpNo, STI, O); 586 587 if (OpNo >= MI->getNumOperands()) { 588 O << "/*Missing OP" << OpNo << "*/"; 589 return; 590 } 591 592 const MCOperand &Op = MI->getOperand(OpNo); 593 if (Op.isReg()) { 594 printRegOperand(Op.getReg(), O, MRI); 595 } else if (Op.isImm()) { 596 const uint8_t OpTy = Desc.OpInfo[OpNo].OperandType; 597 switch (OpTy) { 598 case AMDGPU::OPERAND_REG_IMM_INT32: 599 case AMDGPU::OPERAND_REG_IMM_FP32: 600 case AMDGPU::OPERAND_REG_INLINE_C_INT32: 601 case AMDGPU::OPERAND_REG_INLINE_C_FP32: 602 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: 603 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: 604 case MCOI::OPERAND_IMMEDIATE: 605 printImmediate32(Op.getImm(), STI, O); 606 break; 607 case AMDGPU::OPERAND_REG_IMM_INT64: 608 case AMDGPU::OPERAND_REG_IMM_FP64: 609 case AMDGPU::OPERAND_REG_INLINE_C_INT64: 610 case AMDGPU::OPERAND_REG_INLINE_C_FP64: 611 printImmediate64(Op.getImm(), STI, O); 612 break; 613 case AMDGPU::OPERAND_REG_INLINE_C_INT16: 614 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: 615 case AMDGPU::OPERAND_REG_IMM_INT16: 616 printImmediateInt16(Op.getImm(), STI, O); 617 break; 618 case AMDGPU::OPERAND_REG_INLINE_C_FP16: 619 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: 620 case AMDGPU::OPERAND_REG_IMM_FP16: 621 printImmediate16(Op.getImm(), STI, O); 622 break; 623 case AMDGPU::OPERAND_REG_IMM_V2INT16: 624 case AMDGPU::OPERAND_REG_IMM_V2FP16: 625 if (!isUInt<16>(Op.getImm()) && 626 STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) { 627 printImmediate32(Op.getImm(), STI, O); 628 break; 629 } 630 631 // Deal with 16-bit FP inline immediates not working. 632 if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) { 633 printImmediate16(static_cast<uint16_t>(Op.getImm()), STI, O); 634 break; 635 } 636 LLVM_FALLTHROUGH; 637 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: 638 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: 639 printImmediateInt16(static_cast<uint16_t>(Op.getImm()), STI, O); 640 break; 641 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: 642 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: 643 printImmediateV216(Op.getImm(), STI, O); 644 break; 645 case MCOI::OPERAND_UNKNOWN: 646 case MCOI::OPERAND_PCREL: 647 O << formatDec(Op.getImm()); 648 break; 649 case MCOI::OPERAND_REGISTER: 650 // FIXME: This should be removed and handled somewhere else. Seems to come 651 // from a disassembler bug. 652 O << "/*invalid immediate*/"; 653 break; 654 default: 655 // We hit this for the immediate instruction bits that don't yet have a 656 // custom printer. 657 llvm_unreachable("unexpected immediate operand type"); 658 } 659 } else if (Op.isFPImm()) { 660 // We special case 0.0 because otherwise it will be printed as an integer. 661 if (Op.getFPImm() == 0.0) 662 O << "0.0"; 663 else { 664 const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 665 int RCID = Desc.OpInfo[OpNo].RegClass; 666 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); 667 if (RCBits == 32) 668 printImmediate32(FloatToBits(Op.getFPImm()), STI, O); 669 else if (RCBits == 64) 670 printImmediate64(DoubleToBits(Op.getFPImm()), STI, O); 671 else 672 llvm_unreachable("Invalid register class size"); 673 } 674 } else if (Op.isExpr()) { 675 const MCExpr *Exp = Op.getExpr(); 676 Exp->print(O, &MAI); 677 } else { 678 O << "/*INV_OP*/"; 679 } 680 681 // Print default vcc/vcc_lo operand of v_cndmask_b32_e32. 682 switch (MI->getOpcode()) { 683 default: break; 684 685 case AMDGPU::V_CNDMASK_B32_e32_gfx10: 686 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10: 687 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10: 688 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: 689 case AMDGPU::V_CNDMASK_B32_dpp_gfx10: 690 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10: 691 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10: 692 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10: 693 case AMDGPU::V_CNDMASK_B32_dpp8_gfx10: 694 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10: 695 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10: 696 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10: 697 698 case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7: 699 case AMDGPU::V_CNDMASK_B32_e32_vi: 700 if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(), 701 AMDGPU::OpName::src1)) 702 printDefaultVccOperand(OpNo, STI, O); 703 break; 704 } 705 706 if (Desc.TSFlags & SIInstrFlags::MTBUF) { 707 int SOffsetIdx = 708 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset); 709 assert(SOffsetIdx != -1); 710 if ((int)OpNo == SOffsetIdx) 711 printSymbolicFormat(MI, STI, O); 712 } 713 } 714 715 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI, 716 unsigned OpNo, 717 const MCSubtargetInfo &STI, 718 raw_ostream &O) { 719 unsigned InputModifiers = MI->getOperand(OpNo).getImm(); 720 721 // Use 'neg(...)' instead of '-' to avoid ambiguity. 722 // This is important for integer literals because 723 // -1 is not the same value as neg(1). 724 bool NegMnemo = false; 725 726 if (InputModifiers & SISrcMods::NEG) { 727 if (OpNo + 1 < MI->getNumOperands() && 728 (InputModifiers & SISrcMods::ABS) == 0) { 729 const MCOperand &Op = MI->getOperand(OpNo + 1); 730 NegMnemo = Op.isImm() || Op.isFPImm(); 731 } 732 if (NegMnemo) { 733 O << "neg("; 734 } else { 735 O << '-'; 736 } 737 } 738 739 if (InputModifiers & SISrcMods::ABS) 740 O << '|'; 741 printOperand(MI, OpNo + 1, STI, O); 742 if (InputModifiers & SISrcMods::ABS) 743 O << '|'; 744 745 if (NegMnemo) { 746 O << ')'; 747 } 748 } 749 750 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI, 751 unsigned OpNo, 752 const MCSubtargetInfo &STI, 753 raw_ostream &O) { 754 unsigned InputModifiers = MI->getOperand(OpNo).getImm(); 755 if (InputModifiers & SISrcMods::SEXT) 756 O << "sext("; 757 printOperand(MI, OpNo + 1, STI, O); 758 if (InputModifiers & SISrcMods::SEXT) 759 O << ')'; 760 761 // Print default vcc/vcc_lo operand of VOP2b. 762 switch (MI->getOpcode()) { 763 default: break; 764 765 case AMDGPU::V_CNDMASK_B32_sdwa_gfx10: 766 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10: 767 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10: 768 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10: 769 if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(), 770 AMDGPU::OpName::src1)) 771 printDefaultVccOperand(OpNo, STI, O); 772 break; 773 } 774 } 775 776 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo, 777 const MCSubtargetInfo &STI, 778 raw_ostream &O) { 779 if (!AMDGPU::isGFX10Plus(STI)) 780 llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10"); 781 782 unsigned Imm = MI->getOperand(OpNo).getImm(); 783 O << "dpp8:[" << formatDec(Imm & 0x7); 784 for (size_t i = 1; i < 8; ++i) { 785 O << ',' << formatDec((Imm >> (3 * i)) & 0x7); 786 } 787 O << ']'; 788 } 789 790 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo, 791 const MCSubtargetInfo &STI, 792 raw_ostream &O) { 793 using namespace AMDGPU::DPP; 794 795 unsigned Imm = MI->getOperand(OpNo).getImm(); 796 if (Imm <= DppCtrl::QUAD_PERM_LAST) { 797 O << "quad_perm:["; 798 O << formatDec(Imm & 0x3) << ','; 799 O << formatDec((Imm & 0xc) >> 2) << ','; 800 O << formatDec((Imm & 0x30) >> 4) << ','; 801 O << formatDec((Imm & 0xc0) >> 6) << ']'; 802 } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) && 803 (Imm <= DppCtrl::ROW_SHL_LAST)) { 804 O << "row_shl:"; 805 printU4ImmDecOperand(MI, OpNo, O); 806 } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) && 807 (Imm <= DppCtrl::ROW_SHR_LAST)) { 808 O << "row_shr:"; 809 printU4ImmDecOperand(MI, OpNo, O); 810 } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) && 811 (Imm <= DppCtrl::ROW_ROR_LAST)) { 812 O << "row_ror:"; 813 printU4ImmDecOperand(MI, OpNo, O); 814 } else if (Imm == DppCtrl::WAVE_SHL1) { 815 if (AMDGPU::isGFX10Plus(STI)) { 816 O << "/* wave_shl is not supported starting from GFX10 */"; 817 return; 818 } 819 O << "wave_shl:1"; 820 } else if (Imm == DppCtrl::WAVE_ROL1) { 821 if (AMDGPU::isGFX10Plus(STI)) { 822 O << "/* wave_rol is not supported starting from GFX10 */"; 823 return; 824 } 825 O << "wave_rol:1"; 826 } else if (Imm == DppCtrl::WAVE_SHR1) { 827 if (AMDGPU::isGFX10Plus(STI)) { 828 O << "/* wave_shr is not supported starting from GFX10 */"; 829 return; 830 } 831 O << "wave_shr:1"; 832 } else if (Imm == DppCtrl::WAVE_ROR1) { 833 if (AMDGPU::isGFX10Plus(STI)) { 834 O << "/* wave_ror is not supported starting from GFX10 */"; 835 return; 836 } 837 O << "wave_ror:1"; 838 } else if (Imm == DppCtrl::ROW_MIRROR) { 839 O << "row_mirror"; 840 } else if (Imm == DppCtrl::ROW_HALF_MIRROR) { 841 O << "row_half_mirror"; 842 } else if (Imm == DppCtrl::BCAST15) { 843 if (AMDGPU::isGFX10Plus(STI)) { 844 O << "/* row_bcast is not supported starting from GFX10 */"; 845 return; 846 } 847 O << "row_bcast:15"; 848 } else if (Imm == DppCtrl::BCAST31) { 849 if (AMDGPU::isGFX10Plus(STI)) { 850 O << "/* row_bcast is not supported starting from GFX10 */"; 851 return; 852 } 853 O << "row_bcast:31"; 854 } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) && 855 (Imm <= DppCtrl::ROW_SHARE_LAST)) { 856 if (!AMDGPU::isGFX10Plus(STI)) { 857 O << "/* row_share is not supported on ASICs earlier than GFX10 */"; 858 return; 859 } 860 O << "row_share:"; 861 printU4ImmDecOperand(MI, OpNo, O); 862 } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) && 863 (Imm <= DppCtrl::ROW_XMASK_LAST)) { 864 if (!AMDGPU::isGFX10Plus(STI)) { 865 O << "/* row_xmask is not supported on ASICs earlier than GFX10 */"; 866 return; 867 } 868 O << "row_xmask:"; 869 printU4ImmDecOperand(MI, OpNo, O); 870 } else { 871 O << "/* Invalid dpp_ctrl value */"; 872 } 873 } 874 875 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo, 876 const MCSubtargetInfo &STI, 877 raw_ostream &O) { 878 O << " row_mask:"; 879 printU4ImmOperand(MI, OpNo, STI, O); 880 } 881 882 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo, 883 const MCSubtargetInfo &STI, 884 raw_ostream &O) { 885 O << " bank_mask:"; 886 printU4ImmOperand(MI, OpNo, STI, O); 887 } 888 889 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo, 890 const MCSubtargetInfo &STI, 891 raw_ostream &O) { 892 unsigned Imm = MI->getOperand(OpNo).getImm(); 893 if (Imm) { 894 O << " bound_ctrl:0"; // XXX - this syntax is used in sp3 895 } 896 } 897 898 void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo, 899 const MCSubtargetInfo &STI, 900 raw_ostream &O) { 901 using namespace llvm::AMDGPU::DPP; 902 unsigned Imm = MI->getOperand(OpNo).getImm(); 903 if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) { 904 O << " fi:1"; 905 } 906 } 907 908 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo, 909 raw_ostream &O) { 910 using namespace llvm::AMDGPU::SDWA; 911 912 unsigned Imm = MI->getOperand(OpNo).getImm(); 913 switch (Imm) { 914 case SdwaSel::BYTE_0: O << "BYTE_0"; break; 915 case SdwaSel::BYTE_1: O << "BYTE_1"; break; 916 case SdwaSel::BYTE_2: O << "BYTE_2"; break; 917 case SdwaSel::BYTE_3: O << "BYTE_3"; break; 918 case SdwaSel::WORD_0: O << "WORD_0"; break; 919 case SdwaSel::WORD_1: O << "WORD_1"; break; 920 case SdwaSel::DWORD: O << "DWORD"; break; 921 default: llvm_unreachable("Invalid SDWA data select operand"); 922 } 923 } 924 925 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo, 926 const MCSubtargetInfo &STI, 927 raw_ostream &O) { 928 O << "dst_sel:"; 929 printSDWASel(MI, OpNo, O); 930 } 931 932 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo, 933 const MCSubtargetInfo &STI, 934 raw_ostream &O) { 935 O << "src0_sel:"; 936 printSDWASel(MI, OpNo, O); 937 } 938 939 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo, 940 const MCSubtargetInfo &STI, 941 raw_ostream &O) { 942 O << "src1_sel:"; 943 printSDWASel(MI, OpNo, O); 944 } 945 946 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo, 947 const MCSubtargetInfo &STI, 948 raw_ostream &O) { 949 using namespace llvm::AMDGPU::SDWA; 950 951 O << "dst_unused:"; 952 unsigned Imm = MI->getOperand(OpNo).getImm(); 953 switch (Imm) { 954 case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break; 955 case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break; 956 case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break; 957 default: llvm_unreachable("Invalid SDWA dest_unused operand"); 958 } 959 } 960 961 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo, 962 const MCSubtargetInfo &STI, raw_ostream &O, 963 unsigned N) { 964 unsigned Opc = MI->getOpcode(); 965 int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); 966 unsigned En = MI->getOperand(EnIdx).getImm(); 967 968 int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); 969 970 // If compr is set, print as src0, src0, src1, src1 971 if (MI->getOperand(ComprIdx).getImm()) 972 OpNo = OpNo - N + N / 2; 973 974 if (En & (1 << N)) 975 printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI); 976 else 977 O << "off"; 978 } 979 980 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo, 981 const MCSubtargetInfo &STI, 982 raw_ostream &O) { 983 printExpSrcN(MI, OpNo, STI, O, 0); 984 } 985 986 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo, 987 const MCSubtargetInfo &STI, 988 raw_ostream &O) { 989 printExpSrcN(MI, OpNo, STI, O, 1); 990 } 991 992 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo, 993 const MCSubtargetInfo &STI, 994 raw_ostream &O) { 995 printExpSrcN(MI, OpNo, STI, O, 2); 996 } 997 998 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo, 999 const MCSubtargetInfo &STI, 1000 raw_ostream &O) { 1001 printExpSrcN(MI, OpNo, STI, O, 3); 1002 } 1003 1004 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo, 1005 const MCSubtargetInfo &STI, 1006 raw_ostream &O) { 1007 using namespace llvm::AMDGPU::Exp; 1008 1009 // This is really a 6 bit field. 1010 unsigned Id = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1); 1011 1012 int Index; 1013 StringRef TgtName; 1014 if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) { 1015 O << ' ' << TgtName; 1016 if (Index >= 0) 1017 O << Index; 1018 } else { 1019 O << " invalid_target_" << Id; 1020 } 1021 } 1022 1023 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod, 1024 bool IsPacked, bool HasDstSel) { 1025 int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1); 1026 1027 for (int I = 0; I < NumOps; ++I) { 1028 if (!!(Ops[I] & Mod) != DefaultValue) 1029 return false; 1030 } 1031 1032 if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0) 1033 return false; 1034 1035 return true; 1036 } 1037 1038 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI, 1039 StringRef Name, 1040 unsigned Mod, 1041 raw_ostream &O) { 1042 unsigned Opc = MI->getOpcode(); 1043 int NumOps = 0; 1044 int Ops[3]; 1045 1046 for (int OpName : { AMDGPU::OpName::src0_modifiers, 1047 AMDGPU::OpName::src1_modifiers, 1048 AMDGPU::OpName::src2_modifiers }) { 1049 int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName); 1050 if (Idx == -1) 1051 break; 1052 1053 Ops[NumOps++] = MI->getOperand(Idx).getImm(); 1054 } 1055 1056 const bool HasDstSel = 1057 NumOps > 0 && 1058 Mod == SISrcMods::OP_SEL_0 && 1059 MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL; 1060 1061 const bool IsPacked = 1062 MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked; 1063 1064 if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel)) 1065 return; 1066 1067 O << Name; 1068 for (int I = 0; I < NumOps; ++I) { 1069 if (I != 0) 1070 O << ','; 1071 1072 O << !!(Ops[I] & Mod); 1073 } 1074 1075 if (HasDstSel) { 1076 O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL); 1077 } 1078 1079 O << ']'; 1080 } 1081 1082 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned, 1083 const MCSubtargetInfo &STI, 1084 raw_ostream &O) { 1085 unsigned Opc = MI->getOpcode(); 1086 if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 || 1087 Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) { 1088 auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); 1089 auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers); 1090 unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0); 1091 unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0); 1092 if (FI || BC) 1093 O << " op_sel:[" << FI << ',' << BC << ']'; 1094 return; 1095 } 1096 1097 printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O); 1098 } 1099 1100 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo, 1101 const MCSubtargetInfo &STI, 1102 raw_ostream &O) { 1103 printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O); 1104 } 1105 1106 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo, 1107 const MCSubtargetInfo &STI, 1108 raw_ostream &O) { 1109 printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O); 1110 } 1111 1112 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo, 1113 const MCSubtargetInfo &STI, 1114 raw_ostream &O) { 1115 printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O); 1116 } 1117 1118 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum, 1119 const MCSubtargetInfo &STI, 1120 raw_ostream &O) { 1121 unsigned Imm = MI->getOperand(OpNum).getImm(); 1122 switch (Imm) { 1123 case 0: 1124 O << "p10"; 1125 break; 1126 case 1: 1127 O << "p20"; 1128 break; 1129 case 2: 1130 O << "p0"; 1131 break; 1132 default: 1133 O << "invalid_param_" << Imm; 1134 } 1135 } 1136 1137 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum, 1138 const MCSubtargetInfo &STI, 1139 raw_ostream &O) { 1140 unsigned Attr = MI->getOperand(OpNum).getImm(); 1141 O << "attr" << Attr; 1142 } 1143 1144 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum, 1145 const MCSubtargetInfo &STI, 1146 raw_ostream &O) { 1147 unsigned Chan = MI->getOperand(OpNum).getImm(); 1148 O << '.' << "xyzw"[Chan & 0x3]; 1149 } 1150 1151 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo, 1152 const MCSubtargetInfo &STI, 1153 raw_ostream &O) { 1154 using namespace llvm::AMDGPU::VGPRIndexMode; 1155 unsigned Val = MI->getOperand(OpNo).getImm(); 1156 1157 if ((Val & ~ENABLE_MASK) != 0) { 1158 O << formatHex(static_cast<uint64_t>(Val)); 1159 } else { 1160 O << "gpr_idx("; 1161 bool NeedComma = false; 1162 for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) { 1163 if (Val & (1 << ModeId)) { 1164 if (NeedComma) 1165 O << ','; 1166 O << IdSymbolic[ModeId]; 1167 NeedComma = true; 1168 } 1169 } 1170 O << ')'; 1171 } 1172 } 1173 1174 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, 1175 const MCSubtargetInfo &STI, 1176 raw_ostream &O) { 1177 printOperand(MI, OpNo, STI, O); 1178 O << ", "; 1179 printOperand(MI, OpNo + 1, STI, O); 1180 } 1181 1182 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo, 1183 raw_ostream &O, StringRef Asm, 1184 StringRef Default) { 1185 const MCOperand &Op = MI->getOperand(OpNo); 1186 assert(Op.isImm()); 1187 if (Op.getImm() == 1) { 1188 O << Asm; 1189 } else { 1190 O << Default; 1191 } 1192 } 1193 1194 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo, 1195 raw_ostream &O, char Asm) { 1196 const MCOperand &Op = MI->getOperand(OpNo); 1197 assert(Op.isImm()); 1198 if (Op.getImm() == 1) 1199 O << Asm; 1200 } 1201 1202 void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo, 1203 const MCSubtargetInfo &STI, 1204 raw_ostream &O) { 1205 printNamedBit(MI, OpNo, O, "high"); 1206 } 1207 1208 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo, 1209 const MCSubtargetInfo &STI, 1210 raw_ostream &O) { 1211 printNamedBit(MI, OpNo, O, "clamp"); 1212 } 1213 1214 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo, 1215 const MCSubtargetInfo &STI, 1216 raw_ostream &O) { 1217 int Imm = MI->getOperand(OpNo).getImm(); 1218 if (Imm == SIOutMods::MUL2) 1219 O << " mul:2"; 1220 else if (Imm == SIOutMods::MUL4) 1221 O << " mul:4"; 1222 else if (Imm == SIOutMods::DIV2) 1223 O << " div:2"; 1224 } 1225 1226 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo, 1227 const MCSubtargetInfo &STI, 1228 raw_ostream &O) { 1229 using namespace llvm::AMDGPU::SendMsg; 1230 1231 const unsigned Imm16 = MI->getOperand(OpNo).getImm(); 1232 1233 uint16_t MsgId; 1234 uint16_t OpId; 1235 uint16_t StreamId; 1236 decodeMsg(Imm16, MsgId, OpId, StreamId); 1237 1238 if (isValidMsgId(MsgId, STI) && 1239 isValidMsgOp(MsgId, OpId) && 1240 isValidMsgStream(MsgId, OpId, StreamId)) { 1241 O << "sendmsg(" << getMsgName(MsgId); 1242 if (msgRequiresOp(MsgId)) { 1243 O << ", " << getMsgOpName(MsgId, OpId); 1244 if (msgSupportsStream(MsgId, OpId)) { 1245 O << ", " << StreamId; 1246 } 1247 } 1248 O << ')'; 1249 } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) { 1250 O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')'; 1251 } else { 1252 O << Imm16; // Unknown imm16 code. 1253 } 1254 } 1255 1256 static void printSwizzleBitmask(const uint16_t AndMask, 1257 const uint16_t OrMask, 1258 const uint16_t XorMask, 1259 raw_ostream &O) { 1260 using namespace llvm::AMDGPU::Swizzle; 1261 1262 uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask; 1263 uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask; 1264 1265 O << "\""; 1266 1267 for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) { 1268 uint16_t p0 = Probe0 & Mask; 1269 uint16_t p1 = Probe1 & Mask; 1270 1271 if (p0 == p1) { 1272 if (p0 == 0) { 1273 O << "0"; 1274 } else { 1275 O << "1"; 1276 } 1277 } else { 1278 if (p0 == 0) { 1279 O << "p"; 1280 } else { 1281 O << "i"; 1282 } 1283 } 1284 } 1285 1286 O << "\""; 1287 } 1288 1289 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo, 1290 const MCSubtargetInfo &STI, 1291 raw_ostream &O) { 1292 using namespace llvm::AMDGPU::Swizzle; 1293 1294 uint16_t Imm = MI->getOperand(OpNo).getImm(); 1295 if (Imm == 0) { 1296 return; 1297 } 1298 1299 O << " offset:"; 1300 1301 if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) { 1302 1303 O << "swizzle(" << IdSymbolic[ID_QUAD_PERM]; 1304 for (unsigned I = 0; I < LANE_NUM; ++I) { 1305 O << ","; 1306 O << formatDec(Imm & LANE_MASK); 1307 Imm >>= LANE_SHIFT; 1308 } 1309 O << ")"; 1310 1311 } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) { 1312 1313 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK; 1314 uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK; 1315 uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK; 1316 1317 if (AndMask == BITMASK_MAX && 1318 OrMask == 0 && 1319 countPopulation(XorMask) == 1) { 1320 1321 O << "swizzle(" << IdSymbolic[ID_SWAP]; 1322 O << ","; 1323 O << formatDec(XorMask); 1324 O << ")"; 1325 1326 } else if (AndMask == BITMASK_MAX && 1327 OrMask == 0 && XorMask > 0 && 1328 isPowerOf2_64(XorMask + 1)) { 1329 1330 O << "swizzle(" << IdSymbolic[ID_REVERSE]; 1331 O << ","; 1332 O << formatDec(XorMask + 1); 1333 O << ")"; 1334 1335 } else { 1336 1337 uint16_t GroupSize = BITMASK_MAX - AndMask + 1; 1338 if (GroupSize > 1 && 1339 isPowerOf2_64(GroupSize) && 1340 OrMask < GroupSize && 1341 XorMask == 0) { 1342 1343 O << "swizzle(" << IdSymbolic[ID_BROADCAST]; 1344 O << ","; 1345 O << formatDec(GroupSize); 1346 O << ","; 1347 O << formatDec(OrMask); 1348 O << ")"; 1349 1350 } else { 1351 O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM]; 1352 O << ","; 1353 printSwizzleBitmask(AndMask, OrMask, XorMask, O); 1354 O << ")"; 1355 } 1356 } 1357 } else { 1358 printU16ImmDecOperand(MI, OpNo, O); 1359 } 1360 } 1361 1362 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo, 1363 const MCSubtargetInfo &STI, 1364 raw_ostream &O) { 1365 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU()); 1366 1367 unsigned SImm16 = MI->getOperand(OpNo).getImm(); 1368 unsigned Vmcnt, Expcnt, Lgkmcnt; 1369 decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt); 1370 1371 bool NeedSpace = false; 1372 1373 if (Vmcnt != getVmcntBitMask(ISA)) { 1374 O << "vmcnt(" << Vmcnt << ')'; 1375 NeedSpace = true; 1376 } 1377 1378 if (Expcnt != getExpcntBitMask(ISA)) { 1379 if (NeedSpace) 1380 O << ' '; 1381 O << "expcnt(" << Expcnt << ')'; 1382 NeedSpace = true; 1383 } 1384 1385 if (Lgkmcnt != getLgkmcntBitMask(ISA)) { 1386 if (NeedSpace) 1387 O << ' '; 1388 O << "lgkmcnt(" << Lgkmcnt << ')'; 1389 } 1390 } 1391 1392 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo, 1393 const MCSubtargetInfo &STI, raw_ostream &O) { 1394 unsigned Id; 1395 unsigned Offset; 1396 unsigned Width; 1397 1398 using namespace llvm::AMDGPU::Hwreg; 1399 unsigned Val = MI->getOperand(OpNo).getImm(); 1400 decodeHwreg(Val, Id, Offset, Width); 1401 StringRef HwRegName = getHwreg(Id, STI); 1402 1403 O << "hwreg("; 1404 if (!HwRegName.empty()) { 1405 O << HwRegName; 1406 } else { 1407 O << Id; 1408 } 1409 if (Width != WIDTH_DEFAULT_ || Offset != OFFSET_DEFAULT_) { 1410 O << ", " << Offset << ", " << Width; 1411 } 1412 O << ')'; 1413 } 1414 1415 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo, 1416 const MCSubtargetInfo &STI, 1417 raw_ostream &O) { 1418 uint16_t Imm = MI->getOperand(OpNo).getImm(); 1419 if (Imm == 0) { 1420 return; 1421 } 1422 1423 O << ' ' << formatDec(Imm); 1424 } 1425 1426 #include "AMDGPUGenAsmWriter.inc" 1427 1428 void R600InstPrinter::printInst(const MCInst *MI, uint64_t Address, 1429 StringRef Annot, const MCSubtargetInfo &STI, 1430 raw_ostream &O) { 1431 O.flush(); 1432 printInstruction(MI, Address, O); 1433 printAnnotation(O, Annot); 1434 } 1435 1436 void R600InstPrinter::printAbs(const MCInst *MI, unsigned OpNo, 1437 raw_ostream &O) { 1438 AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '|'); 1439 } 1440 1441 void R600InstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo, 1442 raw_ostream &O) { 1443 int BankSwizzle = MI->getOperand(OpNo).getImm(); 1444 switch (BankSwizzle) { 1445 case 1: 1446 O << "BS:VEC_021/SCL_122"; 1447 break; 1448 case 2: 1449 O << "BS:VEC_120/SCL_212"; 1450 break; 1451 case 3: 1452 O << "BS:VEC_102/SCL_221"; 1453 break; 1454 case 4: 1455 O << "BS:VEC_201"; 1456 break; 1457 case 5: 1458 O << "BS:VEC_210"; 1459 break; 1460 default: 1461 break; 1462 } 1463 } 1464 1465 void R600InstPrinter::printClamp(const MCInst *MI, unsigned OpNo, 1466 raw_ostream &O) { 1467 AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "_SAT"); 1468 } 1469 1470 void R600InstPrinter::printCT(const MCInst *MI, unsigned OpNo, 1471 raw_ostream &O) { 1472 unsigned CT = MI->getOperand(OpNo).getImm(); 1473 switch (CT) { 1474 case 0: 1475 O << 'U'; 1476 break; 1477 case 1: 1478 O << 'N'; 1479 break; 1480 default: 1481 break; 1482 } 1483 } 1484 1485 void R600InstPrinter::printKCache(const MCInst *MI, unsigned OpNo, 1486 raw_ostream &O) { 1487 int KCacheMode = MI->getOperand(OpNo).getImm(); 1488 if (KCacheMode > 0) { 1489 int KCacheBank = MI->getOperand(OpNo - 2).getImm(); 1490 O << "CB" << KCacheBank << ':'; 1491 int KCacheAddr = MI->getOperand(OpNo + 2).getImm(); 1492 int LineSize = (KCacheMode == 1) ? 16 : 32; 1493 O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize; 1494 } 1495 } 1496 1497 void R600InstPrinter::printLast(const MCInst *MI, unsigned OpNo, 1498 raw_ostream &O) { 1499 AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "*", " "); 1500 } 1501 1502 void R600InstPrinter::printLiteral(const MCInst *MI, unsigned OpNo, 1503 raw_ostream &O) { 1504 const MCOperand &Op = MI->getOperand(OpNo); 1505 assert(Op.isImm() || Op.isExpr()); 1506 if (Op.isImm()) { 1507 int64_t Imm = Op.getImm(); 1508 O << Imm << '(' << BitsToFloat(Imm) << ')'; 1509 } 1510 if (Op.isExpr()) { 1511 Op.getExpr()->print(O << '@', &MAI); 1512 } 1513 } 1514 1515 void R600InstPrinter::printNeg(const MCInst *MI, unsigned OpNo, 1516 raw_ostream &O) { 1517 AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '-'); 1518 } 1519 1520 void R600InstPrinter::printOMOD(const MCInst *MI, unsigned OpNo, 1521 raw_ostream &O) { 1522 switch (MI->getOperand(OpNo).getImm()) { 1523 default: break; 1524 case 1: 1525 O << " * 2.0"; 1526 break; 1527 case 2: 1528 O << " * 4.0"; 1529 break; 1530 case 3: 1531 O << " / 2.0"; 1532 break; 1533 } 1534 } 1535 1536 void R600InstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, 1537 raw_ostream &O) { 1538 printOperand(MI, OpNo, O); 1539 O << ", "; 1540 printOperand(MI, OpNo + 1, O); 1541 } 1542 1543 void R600InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 1544 raw_ostream &O) { 1545 if (OpNo >= MI->getNumOperands()) { 1546 O << "/*Missing OP" << OpNo << "*/"; 1547 return; 1548 } 1549 1550 const MCOperand &Op = MI->getOperand(OpNo); 1551 if (Op.isReg()) { 1552 switch (Op.getReg()) { 1553 // This is the default predicate state, so we don't need to print it. 1554 case R600::PRED_SEL_OFF: 1555 break; 1556 1557 default: 1558 O << getRegisterName(Op.getReg()); 1559 break; 1560 } 1561 } else if (Op.isImm()) { 1562 O << Op.getImm(); 1563 } else if (Op.isFPImm()) { 1564 // We special case 0.0 because otherwise it will be printed as an integer. 1565 if (Op.getFPImm() == 0.0) 1566 O << "0.0"; 1567 else { 1568 O << Op.getFPImm(); 1569 } 1570 } else if (Op.isExpr()) { 1571 const MCExpr *Exp = Op.getExpr(); 1572 Exp->print(O, &MAI); 1573 } else { 1574 O << "/*INV_OP*/"; 1575 } 1576 } 1577 1578 void R600InstPrinter::printRel(const MCInst *MI, unsigned OpNo, 1579 raw_ostream &O) { 1580 AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '+'); 1581 } 1582 1583 void R600InstPrinter::printRSel(const MCInst *MI, unsigned OpNo, 1584 raw_ostream &O) { 1585 unsigned Sel = MI->getOperand(OpNo).getImm(); 1586 switch (Sel) { 1587 case 0: 1588 O << 'X'; 1589 break; 1590 case 1: 1591 O << 'Y'; 1592 break; 1593 case 2: 1594 O << 'Z'; 1595 break; 1596 case 3: 1597 O << 'W'; 1598 break; 1599 case 4: 1600 O << '0'; 1601 break; 1602 case 5: 1603 O << '1'; 1604 break; 1605 case 7: 1606 O << '_'; 1607 break; 1608 default: 1609 break; 1610 } 1611 } 1612 1613 void R600InstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo, 1614 raw_ostream &O) { 1615 AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "ExecMask,"); 1616 } 1617 1618 void R600InstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo, 1619 raw_ostream &O) { 1620 AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "Pred,"); 1621 } 1622 1623 void R600InstPrinter::printWrite(const MCInst *MI, unsigned OpNo, 1624 raw_ostream &O) { 1625 const MCOperand &Op = MI->getOperand(OpNo); 1626 if (Op.getImm() == 0) { 1627 O << " (MASKED)"; 1628 } 1629 } 1630 1631 #include "R600GenAsmWriter.inc" 1632