1 //===-- AMDGPUAsmBackend.cpp - AMDGPU Assembler Backend -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/AMDGPUFixupKinds.h" 11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 12 #include "Utils/AMDGPUBaseInfo.h" 13 #include "llvm/MC/MCAsmBackend.h" 14 #include "llvm/MC/MCAssembler.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCFixupKindInfo.h" 17 #include "llvm/MC/MCObjectWriter.h" 18 #include "llvm/MC/TargetRegistry.h" 19 #include "llvm/Support/EndianStream.h" 20 21 using namespace llvm; 22 using namespace llvm::AMDGPU; 23 24 namespace { 25 26 class AMDGPUAsmBackend : public MCAsmBackend { 27 public: 28 AMDGPUAsmBackend(const Target &T) : MCAsmBackend(support::little) {} 29 30 unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; }; 31 32 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 33 const MCValue &Target, MutableArrayRef<char> Data, 34 uint64_t Value, bool IsResolved, 35 const MCSubtargetInfo *STI) const override; 36 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 37 const MCRelaxableFragment *DF, 38 const MCAsmLayout &Layout) const override; 39 40 void relaxInstruction(MCInst &Inst, 41 const MCSubtargetInfo &STI) const override; 42 43 bool mayNeedRelaxation(const MCInst &Inst, 44 const MCSubtargetInfo &STI) const override; 45 46 unsigned getMinimumNopSize() const override; 47 bool writeNopData(raw_ostream &OS, uint64_t Count, 48 const MCSubtargetInfo *STI) const override; 49 50 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override; 51 }; 52 53 } //End anonymous namespace 54 55 void AMDGPUAsmBackend::relaxInstruction(MCInst &Inst, 56 const MCSubtargetInfo &STI) const { 57 MCInst Res; 58 unsigned RelaxedOpcode = AMDGPU::getSOPPWithRelaxation(Inst.getOpcode()); 59 Res.setOpcode(RelaxedOpcode); 60 Res.addOperand(Inst.getOperand(0)); 61 Inst = std::move(Res); 62 } 63 64 bool AMDGPUAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 65 uint64_t Value, 66 const MCRelaxableFragment *DF, 67 const MCAsmLayout &Layout) const { 68 // if the branch target has an offset of x3f this needs to be relaxed to 69 // add a s_nop 0 immediately after branch to effectively increment offset 70 // for hardware workaround in gfx1010 71 return (((int64_t(Value)/4)-1) == 0x3f); 72 } 73 74 bool AMDGPUAsmBackend::mayNeedRelaxation(const MCInst &Inst, 75 const MCSubtargetInfo &STI) const { 76 if (!STI.getFeatureBits()[AMDGPU::FeatureOffset3fBug]) 77 return false; 78 79 if (AMDGPU::getSOPPWithRelaxation(Inst.getOpcode()) >= 0) 80 return true; 81 82 return false; 83 } 84 85 static unsigned getFixupKindNumBytes(unsigned Kind) { 86 switch (Kind) { 87 case AMDGPU::fixup_si_sopp_br: 88 return 2; 89 case FK_SecRel_1: 90 case FK_Data_1: 91 return 1; 92 case FK_SecRel_2: 93 case FK_Data_2: 94 return 2; 95 case FK_SecRel_4: 96 case FK_Data_4: 97 case FK_PCRel_4: 98 return 4; 99 case FK_SecRel_8: 100 case FK_Data_8: 101 return 8; 102 default: 103 llvm_unreachable("Unknown fixup kind!"); 104 } 105 } 106 107 static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 108 MCContext *Ctx) { 109 int64_t SignedValue = static_cast<int64_t>(Value); 110 111 switch (Fixup.getTargetKind()) { 112 case AMDGPU::fixup_si_sopp_br: { 113 int64_t BrImm = (SignedValue - 4) / 4; 114 115 if (Ctx && !isInt<16>(BrImm)) 116 Ctx->reportError(Fixup.getLoc(), "branch size exceeds simm16"); 117 118 return BrImm; 119 } 120 case FK_Data_1: 121 case FK_Data_2: 122 case FK_Data_4: 123 case FK_Data_8: 124 case FK_PCRel_4: 125 case FK_SecRel_4: 126 return Value; 127 default: 128 llvm_unreachable("unhandled fixup kind"); 129 } 130 } 131 132 void AMDGPUAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 133 const MCValue &Target, 134 MutableArrayRef<char> Data, uint64_t Value, 135 bool IsResolved, 136 const MCSubtargetInfo *STI) const { 137 Value = adjustFixupValue(Fixup, Value, &Asm.getContext()); 138 if (!Value) 139 return; // Doesn't change encoding. 140 141 MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind()); 142 143 // Shift the value into position. 144 Value <<= Info.TargetOffset; 145 146 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 147 uint32_t Offset = Fixup.getOffset(); 148 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!"); 149 150 // For each byte of the fragment that the fixup touches, mask in the bits from 151 // the fixup value. 152 for (unsigned i = 0; i != NumBytes; ++i) 153 Data[Offset + i] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff); 154 } 155 156 const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo( 157 MCFixupKind Kind) const { 158 const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = { 159 // name offset bits flags 160 { "fixup_si_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 161 }; 162 163 if (Kind < FirstTargetFixupKind) 164 return MCAsmBackend::getFixupKindInfo(Kind); 165 166 return Infos[Kind - FirstTargetFixupKind]; 167 } 168 169 unsigned AMDGPUAsmBackend::getMinimumNopSize() const { 170 return 4; 171 } 172 173 bool AMDGPUAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count, 174 const MCSubtargetInfo *STI) const { 175 // If the count is not 4-byte aligned, we must be writing data into the text 176 // section (otherwise we have unaligned instructions, and thus have far 177 // bigger problems), so just write zeros instead. 178 OS.write_zeros(Count % 4); 179 180 // We are properly aligned, so write NOPs as requested. 181 Count /= 4; 182 183 // FIXME: R600 support. 184 // s_nop 0 185 const uint32_t Encoded_S_NOP_0 = 0xbf800000; 186 187 for (uint64_t I = 0; I != Count; ++I) 188 support::endian::write<uint32_t>(OS, Encoded_S_NOP_0, Endian); 189 190 return true; 191 } 192 193 //===----------------------------------------------------------------------===// 194 // ELFAMDGPUAsmBackend class 195 //===----------------------------------------------------------------------===// 196 197 namespace { 198 199 class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend { 200 bool Is64Bit; 201 bool HasRelocationAddend; 202 uint8_t OSABI = ELF::ELFOSABI_NONE; 203 uint8_t ABIVersion = 0; 204 205 public: 206 ELFAMDGPUAsmBackend(const Target &T, const Triple &TT, uint8_t ABIVersion) : 207 AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn), 208 HasRelocationAddend(TT.getOS() == Triple::AMDHSA), 209 ABIVersion(ABIVersion) { 210 switch (TT.getOS()) { 211 case Triple::AMDHSA: 212 OSABI = ELF::ELFOSABI_AMDGPU_HSA; 213 break; 214 case Triple::AMDPAL: 215 OSABI = ELF::ELFOSABI_AMDGPU_PAL; 216 break; 217 case Triple::Mesa3D: 218 OSABI = ELF::ELFOSABI_AMDGPU_MESA3D; 219 break; 220 default: 221 break; 222 } 223 } 224 225 std::unique_ptr<MCObjectTargetWriter> 226 createObjectTargetWriter() const override { 227 return createAMDGPUELFObjectWriter(Is64Bit, OSABI, HasRelocationAddend, 228 ABIVersion); 229 } 230 }; 231 232 } // end anonymous namespace 233 234 MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, 235 const MCSubtargetInfo &STI, 236 const MCRegisterInfo &MRI, 237 const MCTargetOptions &Options) { 238 return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple(), 239 getHsaAbiVersion(&STI).getValueOr(0)); 240 } 241