1//===-- EvergreenInstructions.td - EG Instruction defs ----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// TableGen definitions for instructions which are: 10// - Available to Evergreen and newer VLIW4/VLIW5 GPUs 11// - Available only on Evergreen family GPUs. 12// 13//===----------------------------------------------------------------------===// 14 15def isEG : Predicate< 16 "Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && " 17 "!Subtarget->hasCaymanISA()" 18>; 19 20def isEGorCayman : Predicate< 21 "Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||" 22 "Subtarget->getGeneration() == AMDGPUSubtarget::NORTHERN_ISLANDS" 23>; 24 25class EGPat<dag pattern, dag result> : AMDGPUPat<pattern, result> { 26 let SubtargetPredicate = isEG; 27} 28 29class EGOrCaymanPat<dag pattern, dag result> : AMDGPUPat<pattern, result> { 30 let SubtargetPredicate = isEGorCayman; 31} 32 33def IMMZeroBasedBitfieldMask : ImmLeaf <i32, [{ 34 return isMask_32(Imm); 35}]>; 36 37def IMMPopCount : SDNodeXForm<imm, [{ 38 return CurDAG->getTargetConstant(countPopulation(N->getZExtValue()), SDLoc(N), 39 MVT::i32); 40}]>; 41 42//===----------------------------------------------------------------------===// 43// Evergreen / Cayman store instructions 44//===----------------------------------------------------------------------===// 45 46let SubtargetPredicate = isEGorCayman in { 47 48class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins, 49 string name, list<dag> pattern> 50 : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins, 51 "MEM_RAT_CACHELESS "#name, pattern>; 52 53class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins, 54 dag outs, string name, list<dag> pattern> 55 : EG_CF_RAT <0x56, rat_inst, rat_id, mask, outs, ins, 56 "MEM_RAT "#name, pattern>; 57 58class CF_MEM_RAT_STORE_TYPED<bits<1> has_eop> 59 : CF_MEM_RAT <0x1, ?, 0xf, (ins R600_Reg128:$rw_gpr, R600_Reg128:$index_gpr, 60 i32imm:$rat_id, InstFlag:$eop), (outs), 61 "STORE_TYPED RAT($rat_id) $rw_gpr, $index_gpr" 62 #!if(has_eop, ", $eop", ""), 63 [(int_r600_rat_store_typed R600_Reg128:$rw_gpr, 64 R600_Reg128:$index_gpr, 65 (i32 imm:$rat_id))]>; 66 67def RAT_MSKOR : CF_MEM_RAT <0x11, 0, 0xf, 68 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), (outs), 69 "MSKOR $rw_gpr.XW, $index_gpr", 70 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)] 71> { 72 let eop = 0; 73} 74 75 76multiclass RAT_ATOMIC<bits<6> op_ret, bits<6> op_noret, string name> { 77 let Constraints = "$rw_gpr = $out_gpr", eop = 0, mayStore = 1 in { 78 def _RTN: CF_MEM_RAT <op_ret, 0, 0xf, 79 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), 80 (outs R600_Reg128:$out_gpr), 81 name # "_RTN $rw_gpr, $index_gpr", [] >; 82 def _NORET: CF_MEM_RAT <op_noret, 0, 0xf, 83 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), 84 (outs R600_Reg128:$out_gpr), 85 name # " $rw_gpr, $index_gpr", [] >; 86 } 87} 88 89// Swap no-ret is just store. Raw store to cached target 90// can only store on dword, which exactly matches swap_no_ret. 91defm RAT_ATOMIC_XCHG_INT : RAT_ATOMIC<1, 34, "ATOMIC_XCHG_INT">; 92defm RAT_ATOMIC_CMPXCHG_INT : RAT_ATOMIC<4, 36, "ATOMIC_CMPXCHG_INT">; 93defm RAT_ATOMIC_ADD : RAT_ATOMIC<7, 39, "ATOMIC_ADD">; 94defm RAT_ATOMIC_SUB : RAT_ATOMIC<8, 40, "ATOMIC_SUB">; 95defm RAT_ATOMIC_RSUB : RAT_ATOMIC<9, 41, "ATOMIC_RSUB">; 96defm RAT_ATOMIC_MIN_INT : RAT_ATOMIC<10, 42, "ATOMIC_MIN_INT">; 97defm RAT_ATOMIC_MIN_UINT : RAT_ATOMIC<11, 43, "ATOMIC_MIN_UINT">; 98defm RAT_ATOMIC_MAX_INT : RAT_ATOMIC<12, 44, "ATOMIC_MAX_INT">; 99defm RAT_ATOMIC_MAX_UINT : RAT_ATOMIC<13, 45, "ATOMIC_MAX_UINT">; 100defm RAT_ATOMIC_AND : RAT_ATOMIC<14, 46, "ATOMIC_AND">; 101defm RAT_ATOMIC_OR : RAT_ATOMIC<15, 47, "ATOMIC_OR">; 102defm RAT_ATOMIC_XOR : RAT_ATOMIC<16, 48, "ATOMIC_XOR">; 103defm RAT_ATOMIC_INC_UINT : RAT_ATOMIC<18, 50, "ATOMIC_INC_UINT">; 104defm RAT_ATOMIC_DEC_UINT : RAT_ATOMIC<19, 51, "ATOMIC_DEC_UINT">; 105 106} // End SubtargetPredicate = isEGorCayman 107 108//===----------------------------------------------------------------------===// 109// Evergreen Only instructions 110//===----------------------------------------------------------------------===// 111 112let SubtargetPredicate = isEG in { 113 114def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>; 115defm DIV_eg : DIV_Common<RECIP_IEEE_eg>; 116 117def MULLO_INT_eg : MULLO_INT_Common<0x8F>; 118def MULHI_INT_eg : MULHI_INT_Common<0x90>; 119def MULLO_UINT_eg : MULLO_UINT_Common<0x91>; 120def MULHI_UINT_eg : MULHI_UINT_Common<0x92>; 121def MULHI_UINT24_eg : MULHI_UINT24_Common<0xb2>; 122 123def RECIP_UINT_eg : RECIP_UINT_Common<0x94>; 124def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>; 125def EXP_IEEE_eg : EXP_IEEE_Common<0x81>; 126def LOG_IEEE_eg : LOG_IEEE_Common<0x83>; 127def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>; 128def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>; 129def : SqrtPat<RECIPSQRT_IEEE_eg, RECIP_IEEE_eg>; 130 131def SIN_eg : SIN_Common<0x8D>; 132def COS_eg : COS_Common<0x8E>; 133 134def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>; 135} // End SubtargetPredicate = isEG 136 137//===----------------------------------------------------------------------===// 138// Memory read/write instructions 139//===----------------------------------------------------------------------===// 140 141let usesCustomInserter = 1 in { 142 143// 32-bit store 144def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1, 145 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 146 "STORE_RAW $rw_gpr, $index_gpr, $eop", 147 [(store_global i32:$rw_gpr, i32:$index_gpr)] 148>; 149 150// 64-bit store 151def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3, 152 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 153 "STORE_RAW $rw_gpr.XY, $index_gpr, $eop", 154 [(store_global v2i32:$rw_gpr, i32:$index_gpr)] 155>; 156 157//128-bit store 158def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf, 159 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 160 "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop", 161 [(store_global v4i32:$rw_gpr, i32:$index_gpr)] 162>; 163 164def RAT_STORE_TYPED_eg: CF_MEM_RAT_STORE_TYPED<1>; 165 166} // End usesCustomInserter = 1 167 168class VTX_READ_eg <string name, dag outs> 169 : VTX_WORD0_eg, VTX_READ<name, outs, []> { 170 171 // Static fields 172 let VC_INST = 0; 173 let FETCH_TYPE = 2; 174 let FETCH_WHOLE_QUAD = 0; 175 let SRC_REL = 0; 176 // XXX: We can infer this field based on the SRC_GPR. This would allow us 177 // to store vertex addresses in any channel, not just X. 178 let SRC_SEL_X = 0; 179 180 let Inst{31-0} = Word0; 181} 182 183def VTX_READ_8_eg 184 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", 185 (outs R600_TReg32_X:$dst_gpr)> { 186 187 let MEGA_FETCH_COUNT = 1; 188 let DST_SEL_X = 0; 189 let DST_SEL_Y = 7; // Masked 190 let DST_SEL_Z = 7; // Masked 191 let DST_SEL_W = 7; // Masked 192 let DATA_FORMAT = 1; // FMT_8 193} 194 195def VTX_READ_16_eg 196 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", 197 (outs R600_TReg32_X:$dst_gpr)> { 198 let MEGA_FETCH_COUNT = 2; 199 let DST_SEL_X = 0; 200 let DST_SEL_Y = 7; // Masked 201 let DST_SEL_Z = 7; // Masked 202 let DST_SEL_W = 7; // Masked 203 let DATA_FORMAT = 5; // FMT_16 204 205} 206 207def VTX_READ_32_eg 208 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", 209 (outs R600_TReg32_X:$dst_gpr)> { 210 211 let MEGA_FETCH_COUNT = 4; 212 let DST_SEL_X = 0; 213 let DST_SEL_Y = 7; // Masked 214 let DST_SEL_Z = 7; // Masked 215 let DST_SEL_W = 7; // Masked 216 let DATA_FORMAT = 0xD; // COLOR_32 217 218 // This is not really necessary, but there were some GPU hangs that appeared 219 // to be caused by ALU instructions in the next instruction group that wrote 220 // to the $src_gpr registers of the VTX_READ. 221 // e.g. 222 // %t3_x = VTX_READ_PARAM_32_eg killed %t2_x, 24 223 // %t2_x = MOV %zero 224 //Adding this constraint prevents this from happening. 225 let Constraints = "$src_gpr.ptr = $dst_gpr"; 226} 227 228def VTX_READ_64_eg 229 : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr", 230 (outs R600_Reg64:$dst_gpr)> { 231 232 let MEGA_FETCH_COUNT = 8; 233 let DST_SEL_X = 0; 234 let DST_SEL_Y = 1; 235 let DST_SEL_Z = 7; 236 let DST_SEL_W = 7; 237 let DATA_FORMAT = 0x1D; // COLOR_32_32 238} 239 240def VTX_READ_128_eg 241 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", 242 (outs R600_Reg128:$dst_gpr)> { 243 244 let MEGA_FETCH_COUNT = 16; 245 let DST_SEL_X = 0; 246 let DST_SEL_Y = 1; 247 let DST_SEL_Z = 2; 248 let DST_SEL_W = 3; 249 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 250 251 // XXX: Need to force VTX_READ_128 instructions to write to the same register 252 // that holds its buffer address to avoid potential hangs. We can't use 253 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst 254 // registers are different sizes. 255} 256 257//===----------------------------------------------------------------------===// 258// VTX Read from parameter memory space 259//===----------------------------------------------------------------------===// 260def : EGPat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)), 261 (VTX_READ_8_eg MEMxi:$src_gpr, 3)>; 262def : EGPat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)), 263 (VTX_READ_16_eg MEMxi:$src_gpr, 3)>; 264def : EGPat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), 265 (VTX_READ_32_eg MEMxi:$src_gpr, 3)>; 266def : EGPat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), 267 (VTX_READ_64_eg MEMxi:$src_gpr, 3)>; 268def : EGPat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), 269 (VTX_READ_128_eg MEMxi:$src_gpr, 3)>; 270 271//===----------------------------------------------------------------------===// 272// VTX Read from constant memory space 273//===----------------------------------------------------------------------===// 274def : EGPat<(i32:$dst_gpr (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr)), 275 (VTX_READ_8_eg MEMxi:$src_gpr, 2)>; 276def : EGPat<(i32:$dst_gpr (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr)), 277 (VTX_READ_16_eg MEMxi:$src_gpr, 2)>; 278def : EGPat<(i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), 279 (VTX_READ_32_eg MEMxi:$src_gpr, 2)>; 280def : EGPat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), 281 (VTX_READ_64_eg MEMxi:$src_gpr, 2)>; 282def : EGPat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), 283 (VTX_READ_128_eg MEMxi:$src_gpr, 2)>; 284 285//===----------------------------------------------------------------------===// 286// VTX Read from global memory space 287//===----------------------------------------------------------------------===// 288def : EGPat<(i32:$dst_gpr (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr)), 289 (VTX_READ_8_eg MEMxi:$src_gpr, 1)>; 290def : EGPat<(i32:$dst_gpr (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr)), 291 (VTX_READ_16_eg MEMxi:$src_gpr, 1)>; 292def : EGPat<(i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), 293 (VTX_READ_32_eg MEMxi:$src_gpr, 1)>; 294def : EGPat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), 295 (VTX_READ_64_eg MEMxi:$src_gpr, 1)>; 296def : EGPat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), 297 (VTX_READ_128_eg MEMxi:$src_gpr, 1)>; 298 299//===----------------------------------------------------------------------===// 300// Evergreen / Cayman Instructions 301//===----------------------------------------------------------------------===// 302 303let SubtargetPredicate = isEGorCayman in { 304 305multiclass AtomicPat<Instruction inst_noret, 306 SDPatternOperator node_noret> { 307 // FIXME: Add _RTN version. We need per WI scratch location to store the old value 308 // EXTRACT_SUBREG here is dummy, we know the node has no uses 309 def : EGOrCaymanPat<(i32 (node_noret i32:$ptr, i32:$data)), 310 (EXTRACT_SUBREG (inst_noret 311 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $data, sub0), $ptr), sub1)>; 312} 313multiclass AtomicIncDecPat<Instruction inst_noret, 314 SDPatternOperator node_noret, int C> { 315 // FIXME: Add _RTN version. We need per WI scratch location to store the old value 316 // EXTRACT_SUBREG here is dummy, we know the node has no uses 317 def : EGOrCaymanPat<(i32 (node_noret i32:$ptr, C)), 318 (EXTRACT_SUBREG (inst_noret 319 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (MOV_IMM_I32 -1), sub0), $ptr), sub1)>; 320} 321 322// CMPSWAP is pattern is special 323// EXTRACT_SUBREG here is dummy, we know the node has no uses 324// FIXME: Add _RTN version. We need per WI scratch location to store the old value 325def : EGOrCaymanPat<(i32 (atomic_cmp_swap_global_noret i32:$ptr, i32:$cmp, i32:$data)), 326 (EXTRACT_SUBREG (RAT_ATOMIC_CMPXCHG_INT_NORET 327 (INSERT_SUBREG 328 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $cmp, sub3), 329 $data, sub0), 330 $ptr), sub1)>; 331 332defm AtomicSwapPat : AtomicPat <RAT_ATOMIC_XCHG_INT_NORET, 333 atomic_swap_global_noret_32>; 334defm AtomicAddPat : AtomicPat <RAT_ATOMIC_ADD_NORET, 335 atomic_load_add_global_noret_32>; 336defm AtomicSubPat : AtomicPat <RAT_ATOMIC_SUB_NORET, 337 atomic_load_sub_global_noret_32>; 338defm AtomicMinPat : AtomicPat <RAT_ATOMIC_MIN_INT_NORET, 339 atomic_load_min_global_noret_32>; 340defm AtomicUMinPat : AtomicPat <RAT_ATOMIC_MIN_UINT_NORET, 341 atomic_load_umin_global_noret_32>; 342defm AtomicMaxPat : AtomicPat <RAT_ATOMIC_MAX_INT_NORET, 343 atomic_load_max_global_noret_32>; 344defm AtomicUMaxPat : AtomicPat <RAT_ATOMIC_MAX_UINT_NORET, 345 atomic_load_umax_global_noret_32>; 346defm AtomicAndPat : AtomicPat <RAT_ATOMIC_AND_NORET, 347 atomic_load_and_global_noret_32>; 348defm AtomicOrPat : AtomicPat <RAT_ATOMIC_OR_NORET, 349 atomic_load_or_global_noret_32>; 350defm AtomicXorPat : AtomicPat <RAT_ATOMIC_XOR_NORET, 351 atomic_load_xor_global_noret_32>; 352defm AtomicIncAddPat : AtomicIncDecPat <RAT_ATOMIC_INC_UINT_NORET, 353 atomic_load_add_global_noret_32, 1>; 354defm AtomicIncSubPat : AtomicIncDecPat <RAT_ATOMIC_INC_UINT_NORET, 355 atomic_load_sub_global_noret_32, -1>; 356defm AtomicDecAddPat : AtomicIncDecPat <RAT_ATOMIC_DEC_UINT_NORET, 357 atomic_load_add_global_noret_32, -1>; 358defm AtomicDecSubPat : AtomicIncDecPat <RAT_ATOMIC_DEC_UINT_NORET, 359 atomic_load_sub_global_noret_32, 1>; 360 361// Should be predicated on FeatureFP64 362// def FMA_64 : R600_3OP < 363// 0xA, "FMA_64", 364// [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))] 365// >; 366 367// BFE_UINT - bit_extract, an optimization for mask and shift 368// Src0 = Input 369// Src1 = Offset 370// Src2 = Width 371// 372// bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width) 373// 374// Example Usage: 375// (Offset, Width) 376// 377// (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0 378// (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8 379// (16, 8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16 380// (24, 8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24 381def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT", 382 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))], 383 VecALU 384>; 385 386def BFE_INT_eg : R600_3OP <0x5, "BFE_INT", 387 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))], 388 VecALU 389>; 390 391// Bitfield extract patterns 392 393def : AMDGPUPat < 394 (and (i32 (srl i32:$src, i32:$rshift)), IMMZeroBasedBitfieldMask:$mask), 395 (BFE_UINT_eg $src, $rshift, (MOV_IMM_I32 (i32 (IMMPopCount $mask)))) 396>; 397 398// x & ((1 << y) - 1) 399def : AMDGPUPat < 400 (and i32:$src, (add_oneuse (shl_oneuse 1, i32:$width), -1)), 401 (BFE_UINT_eg $src, (MOV_IMM_I32 (i32 0)), $width) 402>; 403 404// x & ~(-1 << y) 405def : AMDGPUPat < 406 (and i32:$src, (xor_oneuse (shl_oneuse -1, i32:$width), -1)), 407 (BFE_UINT_eg $src, (MOV_IMM_I32 (i32 0)), $width) 408>; 409 410// x & (-1 >> (bitwidth - y)) 411def : AMDGPUPat < 412 (and i32:$src, (srl_oneuse -1, (sub 32, i32:$width))), 413 (BFE_UINT_eg $src, (MOV_IMM_I32 (i32 0)), $width) 414>; 415 416// x << (bitwidth - y) >> (bitwidth - y) 417def : AMDGPUPat < 418 (srl (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)), 419 (BFE_UINT_eg $src, (MOV_IMM_I32 (i32 0)), $width) 420>; 421 422def : AMDGPUPat < 423 (sra (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)), 424 (BFE_INT_eg $src, (MOV_IMM_I32 (i32 0)), $width) 425>; 426 427def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", 428 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))], 429 VecALU 430>; 431 432def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i1)), 433 (BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>; 434def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i8)), 435 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>; 436def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i16)), 437 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>; 438 439// BFI patterns 440 441// Definition from ISA doc: 442// (y & x) | (z & ~x) 443def : AMDGPUPat < 444 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))), 445 (BFI_INT_eg $x, $y, $z) 446>; 447 448// 64-bit version 449def : AMDGPUPat < 450 (or (and i64:$y, i64:$x), (and i64:$z, (not i64:$x))), 451 (REG_SEQUENCE R600_Reg64, 452 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub0)), 453 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub0)), 454 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub0))), sub0, 455 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)), 456 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1)), 457 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1))), sub1) 458>; 459 460// SHA-256 Ch function 461// z ^ (x & (y ^ z)) 462def : AMDGPUPat < 463 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))), 464 (BFI_INT_eg $x, $y, $z) 465>; 466 467// 64-bit version 468def : AMDGPUPat < 469 (xor i64:$z, (and i64:$x, (xor i64:$y, i64:$z))), 470 (REG_SEQUENCE R600_Reg64, 471 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub0)), 472 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub0)), 473 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub0))), sub0, 474 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)), 475 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1)), 476 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1))), sub1) 477>; 478 479def : AMDGPUPat < 480 (fcopysign f32:$src0, f32:$src1), 481 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), $src0, $src1) 482>; 483 484def : AMDGPUPat < 485 (fcopysign f32:$src0, f64:$src1), 486 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), $src0, 487 (i32 (EXTRACT_SUBREG R600_Reg64:$src1, sub1))) 488>; 489 490def : AMDGPUPat < 491 (fcopysign f64:$src0, f64:$src1), 492 (REG_SEQUENCE R600_Reg64, 493 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0, 494 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), 495 (i32 (EXTRACT_SUBREG R600_Reg64:$src0, sub1)), 496 (i32 (EXTRACT_SUBREG R600_Reg64:$src1, sub1))), sub1) 497>; 498 499def : AMDGPUPat < 500 (fcopysign f64:$src0, f32:$src1), 501 (REG_SEQUENCE R600_Reg64, 502 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0, 503 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), 504 (i32 (EXTRACT_SUBREG R600_Reg64:$src0, sub1)), 505 $src1), sub1) 506>; 507 508def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT", 509 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))], 510 VecALU 511>; 512 513def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24", 514 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU 515>; 516 517def : UMad24Pat<MULADD_UINT24_eg>; 518 519def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>; 520def : AMDGPUPat < 521 (fshr i32:$src0, i32:$src1, i32:$src2), 522 (BIT_ALIGN_INT_eg $src0, $src1, $src2) 523>; 524def : ROTRPattern <BIT_ALIGN_INT_eg>; 525def MULADD_eg : MULADD_Common<0x14>; 526def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>; 527def FMA_eg : FMA_Common<0x7>; 528def ASHR_eg : ASHR_Common<0x15>; 529def LSHR_eg : LSHR_Common<0x16>; 530def LSHL_eg : LSHL_Common<0x17>; 531def CNDE_eg : CNDE_Common<0x19>; 532def CNDGT_eg : CNDGT_Common<0x1A>; 533def CNDGE_eg : CNDGE_Common<0x1B>; 534def MUL_LIT_eg : MUL_LIT_Common<0x1F>; 535def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>; 536def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24", 537 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU 538>; 539def DOT4_eg : DOT4_Common<0xBE>; 540defm CUBE_eg : CUBE_Common<0xC0>; 541 542 543def ADDC_UINT : R600_2OP_Helper <0x52, "ADDC_UINT", AMDGPUcarry>; 544def SUBB_UINT : R600_2OP_Helper <0x53, "SUBB_UINT", AMDGPUborrow>; 545 546def FLT32_TO_FLT16 : R600_1OP_Helper <0xA2, "FLT32_TO_FLT16", AMDGPUfp_to_f16, VecALU>; 547def FLT16_TO_FLT32 : R600_1OP_Helper <0xA3, "FLT16_TO_FLT32", f16_to_fp, VecALU>; 548def BCNT_INT : R600_1OP_Helper <0xAA, "BCNT_INT", ctpop, VecALU>; 549def FFBH_UINT : R600_1OP_Helper <0xAB, "FFBH_UINT", AMDGPUffbh_u32, VecALU>; 550def FFBL_INT : R600_1OP_Helper <0xAC, "FFBL_INT", AMDGPUffbl_b32, VecALU>; 551 552let hasSideEffects = 1 in { 553 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>; 554} 555 556def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> { 557 let Pattern = []; 558 let Itinerary = AnyALU; 559} 560 561def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>; 562 563def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> { 564 let Pattern = []; 565} 566 567def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>; 568 569def GROUP_BARRIER : InstR600 < 570 (outs), (ins), " GROUP_BARRIER", [(int_r600_group_barrier)], AnyALU>, 571 R600ALU_Word0, 572 R600ALU_Word1_OP2 <0x54> { 573 574 let dst = 0; 575 let dst_rel = 0; 576 let src0 = 0; 577 let src0_rel = 0; 578 let src0_neg = 0; 579 let src0_abs = 0; 580 let src1 = 0; 581 let src1_rel = 0; 582 let src1_neg = 0; 583 let src1_abs = 0; 584 let write = 0; 585 let omod = 0; 586 let clamp = 0; 587 let last = 1; 588 let bank_swizzle = 0; 589 let pred_sel = 0; 590 let update_exec_mask = 0; 591 let update_pred = 0; 592 593 let Inst{31-0} = Word0; 594 let Inst{63-32} = Word1; 595 596 let ALUInst = 1; 597} 598 599//===----------------------------------------------------------------------===// 600// LDS Instructions 601//===----------------------------------------------------------------------===// 602class R600_LDS <bits<6> op, dag outs, dag ins, string asm, 603 list<dag> pattern = []> : 604 605 InstR600 <outs, ins, asm, pattern, XALU>, 606 R600_ALU_LDS_Word0, 607 R600LDS_Word1 { 608 609 bits<6> offset = 0; 610 let lds_op = op; 611 612 let Word1{27} = offset{0}; 613 let Word1{12} = offset{1}; 614 let Word1{28} = offset{2}; 615 let Word1{31} = offset{3}; 616 let Word0{12} = offset{4}; 617 let Word0{25} = offset{5}; 618 619 620 let Inst{31-0} = Word0; 621 let Inst{63-32} = Word1; 622 623 let ALUInst = 1; 624 let HasNativeOperands = 1; 625 let UseNamedOperandTable = 1; 626} 627 628class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS < 629 lds_op, 630 (outs R600_Reg32:$dst), 631 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 632 LAST:$last, R600_Pred:$pred_sel, 633 BANK_SWIZZLE:$bank_swizzle), 634 " "#name#" $last OQAP, $src0$src0_rel $pred_sel", 635 pattern 636 > { 637 638 let src1 = 0; 639 let src1_rel = 0; 640 let src2 = 0; 641 let src2_rel = 0; 642 643 let usesCustomInserter = 1; 644 let LDS_1A = 1; 645 let DisableEncoding = "$dst"; 646} 647 648class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern, 649 string dst =""> : 650 R600_LDS < 651 lds_op, outs, 652 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 653 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel, 654 LAST:$last, R600_Pred:$pred_sel, 655 BANK_SWIZZLE:$bank_swizzle), 656 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel", 657 pattern 658 > { 659 660 field string BaseOp; 661 662 let src2 = 0; 663 let src2_rel = 0; 664 let LDS_1A1D = 1; 665} 666 667class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> : 668 R600_LDS_1A1D <lds_op, (outs), name, pattern> { 669 let BaseOp = name; 670} 671 672class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> : 673 R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name#"_RET", pattern, "OQAP, "> { 674 675 let BaseOp = name; 676 let usesCustomInserter = 1; 677 let DisableEncoding = "$dst"; 678} 679 680class R600_LDS_1A2D <bits<6> lds_op, dag outs, string name, list<dag> pattern, 681 string dst =""> : 682 R600_LDS < 683 lds_op, outs, 684 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 685 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel, 686 R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel, 687 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle), 688 " "#name# "$last "#dst#"$src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel", 689 pattern> { 690 691 field string BaseOp; 692 693 let LDS_1A1D = 0; 694 let LDS_1A2D = 1; 695} 696 697class R600_LDS_1A2D_NORET <bits<6> lds_op, string name, list<dag> pattern> : 698 R600_LDS_1A2D <lds_op, (outs), name, pattern> { 699 let BaseOp = name; 700} 701 702class R600_LDS_1A2D_RET <bits<6> lds_op, string name, list<dag> pattern> : 703 R600_LDS_1A2D <lds_op, (outs R600_Reg32:$dst), name, pattern> { 704 705 let BaseOp = name; 706 let usesCustomInserter = 1; 707 let DisableEncoding = "$dst"; 708} 709 710def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >; 711def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >; 712def LDS_AND : R600_LDS_1A1D_NORET <0x9, "LDS_AND", [] >; 713def LDS_OR : R600_LDS_1A1D_NORET <0xa, "LDS_OR", [] >; 714def LDS_XOR : R600_LDS_1A1D_NORET <0xb, "LDS_XOR", [] >; 715def LDS_WRXCHG: R600_LDS_1A1D_NORET <0xd, "LDS_WRXCHG", [] >; 716def LDS_CMPST: R600_LDS_1A2D_NORET <0x10, "LDS_CMPST", [] >; 717def LDS_MIN_INT : R600_LDS_1A1D_NORET <0x5, "LDS_MIN_INT", [] >; 718def LDS_MAX_INT : R600_LDS_1A1D_NORET <0x6, "LDS_MAX_INT", [] >; 719def LDS_MIN_UINT : R600_LDS_1A1D_NORET <0x7, "LDS_MIN_UINT", [] >; 720def LDS_MAX_UINT : R600_LDS_1A1D_NORET <0x8, "LDS_MAX_UINT", [] >; 721def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE", 722 [(store_local (i32 R600_Reg32:$src1), R600_Reg32:$src0)] 723>; 724def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE", 725 [(truncstorei8_local i32:$src1, i32:$src0)] 726>; 727def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE", 728 [(truncstorei16_local i32:$src1, i32:$src0)] 729>; 730def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD", 731 [(set i32:$dst, (atomic_load_add_local_32 i32:$src0, i32:$src1))] 732>; 733def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB", 734 [(set i32:$dst, (atomic_load_sub_local_32 i32:$src0, i32:$src1))] 735>; 736def LDS_AND_RET : R600_LDS_1A1D_RET <0x29, "LDS_AND", 737 [(set i32:$dst, (atomic_load_and_local_32 i32:$src0, i32:$src1))] 738>; 739def LDS_OR_RET : R600_LDS_1A1D_RET <0x2a, "LDS_OR", 740 [(set i32:$dst, (atomic_load_or_local_32 i32:$src0, i32:$src1))] 741>; 742def LDS_XOR_RET : R600_LDS_1A1D_RET <0x2b, "LDS_XOR", 743 [(set i32:$dst, (atomic_load_xor_local_32 i32:$src0, i32:$src1))] 744>; 745def LDS_MIN_INT_RET : R600_LDS_1A1D_RET <0x25, "LDS_MIN_INT", 746 [(set i32:$dst, (atomic_load_min_local_32 i32:$src0, i32:$src1))] 747>; 748def LDS_MAX_INT_RET : R600_LDS_1A1D_RET <0x26, "LDS_MAX_INT", 749 [(set i32:$dst, (atomic_load_max_local_32 i32:$src0, i32:$src1))] 750>; 751def LDS_MIN_UINT_RET : R600_LDS_1A1D_RET <0x27, "LDS_MIN_UINT", 752 [(set i32:$dst, (atomic_load_umin_local_32 i32:$src0, i32:$src1))] 753>; 754def LDS_MAX_UINT_RET : R600_LDS_1A1D_RET <0x28, "LDS_MAX_UINT", 755 [(set i32:$dst, (atomic_load_umax_local_32 i32:$src0, i32:$src1))] 756>; 757def LDS_WRXCHG_RET : R600_LDS_1A1D_RET <0x2d, "LDS_WRXCHG", 758 [(set i32:$dst, (atomic_swap_local_32 i32:$src0, i32:$src1))] 759>; 760def LDS_CMPST_RET : R600_LDS_1A2D_RET <0x30, "LDS_CMPST", 761 [(set i32:$dst, (atomic_cmp_swap_local_32 i32:$src0, i32:$src1, i32:$src2))] 762>; 763def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET", 764 [(set (i32 R600_Reg32:$dst), (load_local R600_Reg32:$src0))] 765>; 766def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET", 767 [(set i32:$dst, (sextloadi8_local i32:$src0))] 768>; 769def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET", 770 [(set i32:$dst, (az_extloadi8_local i32:$src0))] 771>; 772def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET", 773 [(set i32:$dst, (sextloadi16_local i32:$src0))] 774>; 775def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET", 776 [(set i32:$dst, (az_extloadi16_local i32:$src0))] 777>; 778 779// TRUNC is used for the FLT_TO_INT instructions to work around a 780// perceived problem where the rounding modes are applied differently 781// depending on the instruction and the slot they are in. 782// See: 783// https://bugs.freedesktop.org/show_bug.cgi?id=50232 784// Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c 785// 786// XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes, 787// which do not need to be truncated since the fp values are 0.0f or 1.0f. 788// We should look into handling these cases separately. 789def : EGOrCaymanPat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>; 790 791def : EGOrCaymanPat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>; 792 793// SHA-256 Ma patterns 794 795// ((x & z) | (y & (x | z))) -> BFI (XOR x, y), z, y 796def : AMDGPUPat < 797 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))), 798 (BFI_INT_eg (XOR_INT i32:$x, i32:$y), i32:$z, i32:$y) 799>; 800 801def : AMDGPUPat < 802 (or (and i64:$x, i64:$z), (and i64:$y, (or i64:$x, i64:$z))), 803 (REG_SEQUENCE R600_Reg64, 804 (BFI_INT_eg (XOR_INT (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub0)), 805 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub0))), 806 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub0)), 807 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub0))), sub0, 808 (BFI_INT_eg (XOR_INT (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)), 809 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1))), 810 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1)), 811 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1))), sub1) 812>; 813 814def EG_ExportSwz : ExportSwzInst { 815 let Word1{19-16} = 0; // BURST_COUNT 816 let Word1{20} = 0; // VALID_PIXEL_MODE 817 let Word1{21} = eop; 818 let Word1{29-22} = inst; 819 let Word1{30} = 0; // MARK 820 let Word1{31} = 1; // BARRIER 821} 822defm : ExportPattern<EG_ExportSwz, 83>; 823 824def EG_ExportBuf : ExportBufInst { 825 let Word1{19-16} = 0; // BURST_COUNT 826 let Word1{20} = 0; // VALID_PIXEL_MODE 827 let Word1{21} = eop; 828 let Word1{29-22} = inst; 829 let Word1{30} = 0; // MARK 830 let Word1{31} = 1; // BARRIER 831} 832defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>; 833 834def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT), 835 "TEX $COUNT @$ADDR"> { 836 let POP_COUNT = 0; 837} 838def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT), 839 "VTX $COUNT @$ADDR"> { 840 let POP_COUNT = 0; 841} 842def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR), 843 "LOOP_START_DX10 @$ADDR"> { 844 let POP_COUNT = 0; 845 let COUNT = 0; 846} 847def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> { 848 let POP_COUNT = 0; 849 let COUNT = 0; 850} 851def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR), 852 "LOOP_BREAK @$ADDR"> { 853 let POP_COUNT = 0; 854 let COUNT = 0; 855} 856def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR), 857 "CONTINUE @$ADDR"> { 858 let POP_COUNT = 0; 859 let COUNT = 0; 860} 861def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 862 "JUMP @$ADDR POP:$POP_COUNT"> { 863 let COUNT = 0; 864} 865def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 866 "PUSH @$ADDR POP:$POP_COUNT"> { 867 let COUNT = 0; 868} 869def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 870 "ELSE @$ADDR POP:$POP_COUNT"> { 871 let COUNT = 0; 872} 873def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> { 874 let ADDR = 0; 875 let COUNT = 0; 876 let POP_COUNT = 0; 877} 878def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 879 "POP @$ADDR POP:$POP_COUNT"> { 880 let COUNT = 0; 881} 882def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> { 883 let COUNT = 0; 884 let POP_COUNT = 0; 885 let ADDR = 0; 886 let END_OF_PROGRAM = 1; 887} 888 889} // End Predicates = [isEGorCayman] 890