xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/EvergreenInstructions.td (revision 2f513db72b034fd5ef7f080b11be5c711c15186a)
1//===-- EvergreenInstructions.td - EG Instruction defs  ----*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// TableGen definitions for instructions which are:
10// - Available to Evergreen and newer VLIW4/VLIW5 GPUs
11// - Available only on Evergreen family GPUs.
12//
13//===----------------------------------------------------------------------===//
14
15def isEG : Predicate<
16  "Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && "
17  "!Subtarget->hasCaymanISA()"
18>;
19
20def isEGorCayman : Predicate<
21  "Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||"
22  "Subtarget->getGeneration() == AMDGPUSubtarget::NORTHERN_ISLANDS"
23>;
24
25class EGPat<dag pattern, dag result> : AMDGPUPat<pattern, result> {
26  let SubtargetPredicate = isEG;
27}
28
29class EGOrCaymanPat<dag pattern, dag result> : AMDGPUPat<pattern, result> {
30  let SubtargetPredicate = isEGorCayman;
31}
32
33//===----------------------------------------------------------------------===//
34// Evergreen / Cayman store instructions
35//===----------------------------------------------------------------------===//
36
37let SubtargetPredicate = isEGorCayman in {
38
39class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins,
40                           string name, list<dag> pattern>
41    : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins,
42                 "MEM_RAT_CACHELESS "#name, pattern>;
43
44class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins,
45                  dag outs, string name, list<dag> pattern>
46    : EG_CF_RAT <0x56, rat_inst, rat_id, mask, outs, ins,
47                 "MEM_RAT "#name, pattern>;
48
49class CF_MEM_RAT_STORE_TYPED<bits<1> has_eop>
50    : CF_MEM_RAT <0x1, ?, 0xf, (ins R600_Reg128:$rw_gpr, R600_Reg128:$index_gpr,
51                           i32imm:$rat_id, InstFlag:$eop), (outs),
52                  "STORE_TYPED RAT($rat_id) $rw_gpr, $index_gpr"
53                               #!if(has_eop, ", $eop", ""),
54                  [(int_r600_rat_store_typed R600_Reg128:$rw_gpr,
55                                             R600_Reg128:$index_gpr,
56                                             (i32 imm:$rat_id))]>;
57
58def RAT_MSKOR : CF_MEM_RAT <0x11, 0, 0xf,
59  (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), (outs),
60  "MSKOR $rw_gpr.XW, $index_gpr",
61  [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)]
62> {
63  let eop = 0;
64}
65
66
67multiclass RAT_ATOMIC<bits<6> op_ret, bits<6> op_noret, string name> {
68  let Constraints = "$rw_gpr = $out_gpr", eop = 0, mayStore = 1 in {
69  def  _RTN: CF_MEM_RAT <op_ret, 0, 0xf,
70             (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
71             (outs R600_Reg128:$out_gpr),
72             name ## "_RTN" ## " $rw_gpr, $index_gpr", [] >;
73  def _NORET: CF_MEM_RAT <op_noret, 0, 0xf,
74              (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
75              (outs R600_Reg128:$out_gpr),
76              name ## " $rw_gpr, $index_gpr", [] >;
77  }
78}
79
80// Swap no-ret is just store. Raw store to cached target
81// can only store on dword, which exactly matches swap_no_ret.
82defm RAT_ATOMIC_XCHG_INT : RAT_ATOMIC<1, 34, "ATOMIC_XCHG_INT">;
83defm RAT_ATOMIC_CMPXCHG_INT : RAT_ATOMIC<4, 36, "ATOMIC_CMPXCHG_INT">;
84defm RAT_ATOMIC_ADD : RAT_ATOMIC<7, 39, "ATOMIC_ADD">;
85defm RAT_ATOMIC_SUB : RAT_ATOMIC<8, 40, "ATOMIC_SUB">;
86defm RAT_ATOMIC_RSUB : RAT_ATOMIC<9, 41, "ATOMIC_RSUB">;
87defm RAT_ATOMIC_MIN_INT : RAT_ATOMIC<10, 42, "ATOMIC_MIN_INT">;
88defm RAT_ATOMIC_MIN_UINT : RAT_ATOMIC<11, 43, "ATOMIC_MIN_UINT">;
89defm RAT_ATOMIC_MAX_INT : RAT_ATOMIC<12, 44, "ATOMIC_MAX_INT">;
90defm RAT_ATOMIC_MAX_UINT : RAT_ATOMIC<13, 45, "ATOMIC_MAX_UINT">;
91defm RAT_ATOMIC_AND : RAT_ATOMIC<14, 46, "ATOMIC_AND">;
92defm RAT_ATOMIC_OR : RAT_ATOMIC<15, 47, "ATOMIC_OR">;
93defm RAT_ATOMIC_XOR : RAT_ATOMIC<16, 48, "ATOMIC_XOR">;
94defm RAT_ATOMIC_INC_UINT : RAT_ATOMIC<18, 50, "ATOMIC_INC_UINT">;
95defm RAT_ATOMIC_DEC_UINT : RAT_ATOMIC<19, 51, "ATOMIC_DEC_UINT">;
96
97} // End SubtargetPredicate = isEGorCayman
98
99//===----------------------------------------------------------------------===//
100// Evergreen Only instructions
101//===----------------------------------------------------------------------===//
102
103let SubtargetPredicate = isEG in {
104
105def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
106defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
107
108def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
109def MULHI_INT_eg : MULHI_INT_Common<0x90>;
110def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
111def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
112def MULHI_UINT24_eg : MULHI_UINT24_Common<0xb2>;
113
114def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
115def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
116def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
117def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
118def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
119def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
120def : RsqPat<RECIPSQRT_IEEE_eg, f32>;
121def SIN_eg : SIN_Common<0x8D>;
122def COS_eg : COS_Common<0x8E>;
123
124def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
125def : EGPat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>;
126} // End SubtargetPredicate = isEG
127
128//===----------------------------------------------------------------------===//
129// Memory read/write instructions
130//===----------------------------------------------------------------------===//
131
132let usesCustomInserter = 1 in {
133
134// 32-bit store
135def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1,
136  (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
137  "STORE_RAW $rw_gpr, $index_gpr, $eop",
138  [(store_global i32:$rw_gpr, i32:$index_gpr)]
139>;
140
141// 64-bit store
142def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3,
143  (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
144  "STORE_RAW $rw_gpr.XY, $index_gpr, $eop",
145  [(store_global v2i32:$rw_gpr, i32:$index_gpr)]
146>;
147
148//128-bit store
149def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf,
150  (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
151  "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop",
152  [(store_global v4i32:$rw_gpr, i32:$index_gpr)]
153>;
154
155def RAT_STORE_TYPED_eg: CF_MEM_RAT_STORE_TYPED<1>;
156
157} // End usesCustomInserter = 1
158
159class VTX_READ_eg <string name, dag outs>
160    : VTX_WORD0_eg, VTX_READ<name, outs, []> {
161
162  // Static fields
163  let VC_INST = 0;
164  let FETCH_TYPE = 2;
165  let FETCH_WHOLE_QUAD = 0;
166  let SRC_REL = 0;
167  // XXX: We can infer this field based on the SRC_GPR.  This would allow us
168  // to store vertex addresses in any channel, not just X.
169  let SRC_SEL_X = 0;
170
171  let Inst{31-0} = Word0;
172}
173
174def VTX_READ_8_eg
175    : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr",
176                   (outs R600_TReg32_X:$dst_gpr)> {
177
178  let MEGA_FETCH_COUNT = 1;
179  let DST_SEL_X = 0;
180  let DST_SEL_Y = 7;   // Masked
181  let DST_SEL_Z = 7;   // Masked
182  let DST_SEL_W = 7;   // Masked
183  let DATA_FORMAT = 1; // FMT_8
184}
185
186def VTX_READ_16_eg
187    : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr",
188                   (outs R600_TReg32_X:$dst_gpr)> {
189  let MEGA_FETCH_COUNT = 2;
190  let DST_SEL_X = 0;
191  let DST_SEL_Y = 7;   // Masked
192  let DST_SEL_Z = 7;   // Masked
193  let DST_SEL_W = 7;   // Masked
194  let DATA_FORMAT = 5; // FMT_16
195
196}
197
198def VTX_READ_32_eg
199    : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr",
200                   (outs R600_TReg32_X:$dst_gpr)> {
201
202  let MEGA_FETCH_COUNT = 4;
203  let DST_SEL_X        = 0;
204  let DST_SEL_Y        = 7;   // Masked
205  let DST_SEL_Z        = 7;   // Masked
206  let DST_SEL_W        = 7;   // Masked
207  let DATA_FORMAT      = 0xD; // COLOR_32
208
209  // This is not really necessary, but there were some GPU hangs that appeared
210  // to be caused by ALU instructions in the next instruction group that wrote
211  // to the $src_gpr registers of the VTX_READ.
212  // e.g.
213  // %t3_x = VTX_READ_PARAM_32_eg killed %t2_x, 24
214  // %t2_x = MOV %zero
215  //Adding this constraint prevents this from happening.
216  let Constraints = "$src_gpr.ptr = $dst_gpr";
217}
218
219def VTX_READ_64_eg
220    : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr",
221                   (outs R600_Reg64:$dst_gpr)> {
222
223  let MEGA_FETCH_COUNT = 8;
224  let DST_SEL_X        = 0;
225  let DST_SEL_Y        = 1;
226  let DST_SEL_Z        = 7;
227  let DST_SEL_W        = 7;
228  let DATA_FORMAT      = 0x1D; // COLOR_32_32
229}
230
231def VTX_READ_128_eg
232    : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr",
233                   (outs R600_Reg128:$dst_gpr)> {
234
235  let MEGA_FETCH_COUNT = 16;
236  let DST_SEL_X        =  0;
237  let DST_SEL_Y        =  1;
238  let DST_SEL_Z        =  2;
239  let DST_SEL_W        =  3;
240  let DATA_FORMAT      =  0x22; // COLOR_32_32_32_32
241
242  // XXX: Need to force VTX_READ_128 instructions to write to the same register
243  // that holds its buffer address to avoid potential hangs.  We can't use
244  // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
245  // registers are different sizes.
246}
247
248//===----------------------------------------------------------------------===//
249// VTX Read from parameter memory space
250//===----------------------------------------------------------------------===//
251def : EGPat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)),
252          (VTX_READ_8_eg MEMxi:$src_gpr, 3)>;
253def : EGPat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)),
254          (VTX_READ_16_eg MEMxi:$src_gpr, 3)>;
255def : EGPat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
256          (VTX_READ_32_eg MEMxi:$src_gpr, 3)>;
257def : EGPat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
258          (VTX_READ_64_eg MEMxi:$src_gpr, 3)>;
259def : EGPat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
260          (VTX_READ_128_eg MEMxi:$src_gpr, 3)>;
261
262//===----------------------------------------------------------------------===//
263// VTX Read from constant memory space
264//===----------------------------------------------------------------------===//
265def : EGPat<(i32:$dst_gpr (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr)),
266          (VTX_READ_8_eg MEMxi:$src_gpr, 2)>;
267def : EGPat<(i32:$dst_gpr (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr)),
268          (VTX_READ_16_eg MEMxi:$src_gpr, 2)>;
269def : EGPat<(i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
270          (VTX_READ_32_eg MEMxi:$src_gpr, 2)>;
271def : EGPat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
272          (VTX_READ_64_eg MEMxi:$src_gpr, 2)>;
273def : EGPat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
274          (VTX_READ_128_eg MEMxi:$src_gpr, 2)>;
275
276//===----------------------------------------------------------------------===//
277// VTX Read from global memory space
278//===----------------------------------------------------------------------===//
279def : EGPat<(i32:$dst_gpr (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr)),
280          (VTX_READ_8_eg MEMxi:$src_gpr, 1)>;
281def : EGPat<(i32:$dst_gpr (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr)),
282          (VTX_READ_16_eg MEMxi:$src_gpr, 1)>;
283def : EGPat<(i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
284          (VTX_READ_32_eg MEMxi:$src_gpr, 1)>;
285def : EGPat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
286          (VTX_READ_64_eg MEMxi:$src_gpr, 1)>;
287def : EGPat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
288          (VTX_READ_128_eg MEMxi:$src_gpr, 1)>;
289
290//===----------------------------------------------------------------------===//
291// Evergreen / Cayman Instructions
292//===----------------------------------------------------------------------===//
293
294let SubtargetPredicate = isEGorCayman in {
295
296multiclass AtomicPat<Instruction inst_ret, Instruction inst_noret,
297                     SDPatternOperator node_ret, SDPatternOperator node_noret> {
298  // FIXME: Add _RTN version. We need per WI scratch location to store the old value
299  // EXTRACT_SUBREG here is dummy, we know the node has no uses
300  def : EGOrCaymanPat<(i32 (node_noret i32:$ptr, i32:$data)),
301            (EXTRACT_SUBREG (inst_noret
302              (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $data, sub0), $ptr), sub1)>;
303}
304multiclass AtomicIncDecPat<Instruction inst_ret, Instruction inst_noret,
305                     SDPatternOperator node_ret, SDPatternOperator node_noret, int C> {
306  // FIXME: Add _RTN version. We need per WI scratch location to store the old value
307  // EXTRACT_SUBREG here is dummy, we know the node has no uses
308  def : EGOrCaymanPat<(i32 (node_noret i32:$ptr, C)),
309            (EXTRACT_SUBREG (inst_noret
310              (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (MOV_IMM_I32 -1), sub0), $ptr), sub1)>;
311}
312
313// CMPSWAP is pattern is special
314// EXTRACT_SUBREG here is dummy, we know the node has no uses
315// FIXME: Add _RTN version. We need per WI scratch location to store the old value
316def : EGOrCaymanPat<(i32 (atomic_cmp_swap_global_noret i32:$ptr, i32:$cmp, i32:$data)),
317          (EXTRACT_SUBREG (RAT_ATOMIC_CMPXCHG_INT_NORET
318            (INSERT_SUBREG
319              (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $cmp, sub3),
320            $data, sub0),
321          $ptr), sub1)>;
322
323defm AtomicSwapPat : AtomicPat <RAT_ATOMIC_XCHG_INT_RTN,
324                                RAT_ATOMIC_XCHG_INT_NORET,
325                                atomic_swap_global_ret,
326                                atomic_swap_global_noret>;
327defm AtomicAddPat : AtomicPat <RAT_ATOMIC_ADD_RTN, RAT_ATOMIC_ADD_NORET,
328                               atomic_add_global_ret, atomic_add_global_noret>;
329defm AtomicSubPat : AtomicPat <RAT_ATOMIC_SUB_RTN, RAT_ATOMIC_SUB_NORET,
330                               atomic_sub_global_ret, atomic_sub_global_noret>;
331defm AtomicMinPat : AtomicPat <RAT_ATOMIC_MIN_INT_RTN,
332                               RAT_ATOMIC_MIN_INT_NORET,
333                               atomic_min_global_ret, atomic_min_global_noret>;
334defm AtomicUMinPat : AtomicPat <RAT_ATOMIC_MIN_UINT_RTN,
335                                RAT_ATOMIC_MIN_UINT_NORET,
336                                atomic_umin_global_ret, atomic_umin_global_noret>;
337defm AtomicMaxPat : AtomicPat <RAT_ATOMIC_MAX_INT_RTN,
338                               RAT_ATOMIC_MAX_INT_NORET,
339                               atomic_max_global_ret, atomic_max_global_noret>;
340defm AtomicUMaxPat : AtomicPat <RAT_ATOMIC_MAX_UINT_RTN,
341                                RAT_ATOMIC_MAX_UINT_NORET,
342                                atomic_umax_global_ret, atomic_umax_global_noret>;
343defm AtomicAndPat : AtomicPat <RAT_ATOMIC_AND_RTN, RAT_ATOMIC_AND_NORET,
344                               atomic_and_global_ret, atomic_and_global_noret>;
345defm AtomicOrPat : AtomicPat <RAT_ATOMIC_OR_RTN, RAT_ATOMIC_OR_NORET,
346                              atomic_or_global_ret, atomic_or_global_noret>;
347defm AtomicXorPat : AtomicPat <RAT_ATOMIC_XOR_RTN, RAT_ATOMIC_XOR_NORET,
348                               atomic_xor_global_ret, atomic_xor_global_noret>;
349defm AtomicIncAddPat : AtomicIncDecPat <RAT_ATOMIC_INC_UINT_RTN,
350                                        RAT_ATOMIC_INC_UINT_NORET,
351                                        atomic_add_global_ret,
352                                        atomic_add_global_noret, 1>;
353defm AtomicIncSubPat : AtomicIncDecPat <RAT_ATOMIC_INC_UINT_RTN,
354                                        RAT_ATOMIC_INC_UINT_NORET,
355                                        atomic_sub_global_ret,
356                                        atomic_sub_global_noret, -1>;
357defm AtomicDecAddPat : AtomicIncDecPat <RAT_ATOMIC_DEC_UINT_RTN,
358                                        RAT_ATOMIC_DEC_UINT_NORET,
359                                        atomic_add_global_ret,
360                                        atomic_add_global_noret, -1>;
361defm AtomicDecSubPat : AtomicIncDecPat <RAT_ATOMIC_DEC_UINT_RTN,
362                                        RAT_ATOMIC_DEC_UINT_NORET,
363                                        atomic_sub_global_ret,
364                                        atomic_sub_global_noret, 1>;
365
366// Should be predicated on FeatureFP64
367// def FMA_64 : R600_3OP <
368//   0xA, "FMA_64",
369//   [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
370// >;
371
372// BFE_UINT - bit_extract, an optimization for mask and shift
373// Src0 = Input
374// Src1 = Offset
375// Src2 = Width
376//
377// bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
378//
379// Example Usage:
380// (Offset, Width)
381//
382// (0, 8)  = (Input << 24) >> 24 = (Input &  0xff)       >> 0
383// (8, 8)  = (Input << 16) >> 24 = (Input &  0xffff)     >> 8
384// (16, 8) = (Input <<  8) >> 24 = (Input &  0xffffff)   >> 16
385// (24, 8) = (Input <<  0) >> 24 = (Input &  0xffffffff) >> 24
386def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
387  [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))],
388  VecALU
389>;
390
391def BFE_INT_eg : R600_3OP <0x5, "BFE_INT",
392  [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))],
393  VecALU
394>;
395
396defm : BFEPattern <BFE_UINT_eg, BFE_INT_eg, MOV_IMM_I32>;
397
398def BFI_INT_eg : R600_3OP <0x06, "BFI_INT",
399  [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],
400  VecALU
401>;
402
403def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i1)),
404  (BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>;
405def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i8)),
406  (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>;
407def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i16)),
408  (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>;
409
410defm : BFIPatterns <BFI_INT_eg, MOV_IMM_I32, R600_Reg64>;
411
412def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT",
413  [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))],
414  VecALU
415>;
416
417def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24",
418  [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU
419>;
420
421def : UMad24Pat<MULADD_UINT24_eg>;
422
423def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;
424def : ROTRPattern <BIT_ALIGN_INT_eg>;
425def MULADD_eg : MULADD_Common<0x14>;
426def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
427def FMA_eg : FMA_Common<0x7>;
428def ASHR_eg : ASHR_Common<0x15>;
429def LSHR_eg : LSHR_Common<0x16>;
430def LSHL_eg : LSHL_Common<0x17>;
431def CNDE_eg : CNDE_Common<0x19>;
432def CNDGT_eg : CNDGT_Common<0x1A>;
433def CNDGE_eg : CNDGE_Common<0x1B>;
434def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
435def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
436def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24",
437  [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU
438>;
439def DOT4_eg : DOT4_Common<0xBE>;
440defm CUBE_eg : CUBE_Common<0xC0>;
441
442
443def ADDC_UINT : R600_2OP_Helper <0x52, "ADDC_UINT", AMDGPUcarry>;
444def SUBB_UINT : R600_2OP_Helper <0x53, "SUBB_UINT", AMDGPUborrow>;
445
446def FLT32_TO_FLT16 : R600_1OP_Helper <0xA2, "FLT32_TO_FLT16", AMDGPUfp_to_f16, VecALU>;
447def FLT16_TO_FLT32 : R600_1OP_Helper <0xA3, "FLT16_TO_FLT32", f16_to_fp, VecALU>;
448def BCNT_INT : R600_1OP_Helper <0xAA, "BCNT_INT", ctpop, VecALU>;
449def FFBH_UINT : R600_1OP_Helper <0xAB, "FFBH_UINT", AMDGPUffbh_u32, VecALU>;
450def FFBL_INT : R600_1OP_Helper <0xAC, "FFBL_INT", AMDGPUffbl_b32, VecALU>;
451
452let hasSideEffects = 1 in {
453  def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>;
454}
455
456def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
457  let Pattern = [];
458  let Itinerary = AnyALU;
459}
460
461def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
462
463def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
464  let Pattern = [];
465}
466
467def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
468
469def GROUP_BARRIER : InstR600 <
470    (outs), (ins), "  GROUP_BARRIER", [(int_r600_group_barrier)], AnyALU>,
471    R600ALU_Word0,
472    R600ALU_Word1_OP2 <0x54> {
473
474  let dst = 0;
475  let dst_rel = 0;
476  let src0 = 0;
477  let src0_rel = 0;
478  let src0_neg = 0;
479  let src0_abs = 0;
480  let src1 = 0;
481  let src1_rel = 0;
482  let src1_neg = 0;
483  let src1_abs = 0;
484  let write = 0;
485  let omod = 0;
486  let clamp = 0;
487  let last = 1;
488  let bank_swizzle = 0;
489  let pred_sel = 0;
490  let update_exec_mask = 0;
491  let update_pred = 0;
492
493  let Inst{31-0}  = Word0;
494  let Inst{63-32} = Word1;
495
496  let ALUInst = 1;
497}
498
499//===----------------------------------------------------------------------===//
500// LDS Instructions
501//===----------------------------------------------------------------------===//
502class R600_LDS  <bits<6> op, dag outs, dag ins, string asm,
503                 list<dag> pattern = []> :
504
505    InstR600 <outs, ins, asm, pattern, XALU>,
506    R600_ALU_LDS_Word0,
507    R600LDS_Word1 {
508
509  bits<6>  offset = 0;
510  let lds_op = op;
511
512  let Word1{27} = offset{0};
513  let Word1{12} = offset{1};
514  let Word1{28} = offset{2};
515  let Word1{31} = offset{3};
516  let Word0{12} = offset{4};
517  let Word0{25} = offset{5};
518
519
520  let Inst{31-0}  = Word0;
521  let Inst{63-32} = Word1;
522
523  let ALUInst = 1;
524  let HasNativeOperands = 1;
525  let UseNamedOperandTable = 1;
526}
527
528class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS <
529  lds_op,
530  (outs R600_Reg32:$dst),
531  (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
532       LAST:$last, R600_Pred:$pred_sel,
533       BANK_SWIZZLE:$bank_swizzle),
534  "  "#name#" $last OQAP, $src0$src0_rel $pred_sel",
535  pattern
536  > {
537
538  let src1 = 0;
539  let src1_rel = 0;
540  let src2 = 0;
541  let src2_rel = 0;
542
543  let usesCustomInserter = 1;
544  let LDS_1A = 1;
545  let DisableEncoding = "$dst";
546}
547
548class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
549                     string dst =""> :
550    R600_LDS <
551  lds_op, outs,
552  (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
553       R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
554       LAST:$last, R600_Pred:$pred_sel,
555       BANK_SWIZZLE:$bank_swizzle),
556  "  "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel",
557  pattern
558  > {
559
560  field string BaseOp;
561
562  let src2 = 0;
563  let src2_rel = 0;
564  let LDS_1A1D = 1;
565}
566
567class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> :
568    R600_LDS_1A1D <lds_op, (outs), name, pattern> {
569  let BaseOp = name;
570}
571
572class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> :
573    R600_LDS_1A1D <lds_op,  (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> {
574
575  let BaseOp = name;
576  let usesCustomInserter = 1;
577  let DisableEncoding = "$dst";
578}
579
580class R600_LDS_1A2D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
581                     string dst =""> :
582    R600_LDS <
583  lds_op, outs,
584  (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
585       R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
586       R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel,
587       LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),
588  "  "#name# "$last "#dst#"$src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel",
589  pattern> {
590
591  field string BaseOp;
592
593  let LDS_1A1D = 0;
594  let LDS_1A2D = 1;
595}
596
597class R600_LDS_1A2D_NORET <bits<6> lds_op, string name, list<dag> pattern> :
598    R600_LDS_1A2D <lds_op, (outs), name, pattern> {
599  let BaseOp = name;
600}
601
602class R600_LDS_1A2D_RET <bits<6> lds_op, string name, list<dag> pattern> :
603    R600_LDS_1A2D <lds_op, (outs R600_Reg32:$dst), name, pattern> {
604
605  let BaseOp = name;
606  let usesCustomInserter = 1;
607  let DisableEncoding = "$dst";
608}
609
610def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >;
611def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >;
612def LDS_AND : R600_LDS_1A1D_NORET <0x9, "LDS_AND", [] >;
613def LDS_OR : R600_LDS_1A1D_NORET <0xa, "LDS_OR", [] >;
614def LDS_XOR : R600_LDS_1A1D_NORET <0xb, "LDS_XOR", [] >;
615def LDS_WRXCHG: R600_LDS_1A1D_NORET <0xd, "LDS_WRXCHG", [] >;
616def LDS_CMPST: R600_LDS_1A2D_NORET <0x10, "LDS_CMPST", [] >;
617def LDS_MIN_INT : R600_LDS_1A1D_NORET <0x5, "LDS_MIN_INT", [] >;
618def LDS_MAX_INT : R600_LDS_1A1D_NORET <0x6, "LDS_MAX_INT", [] >;
619def LDS_MIN_UINT : R600_LDS_1A1D_NORET <0x7, "LDS_MIN_UINT", [] >;
620def LDS_MAX_UINT : R600_LDS_1A1D_NORET <0x8, "LDS_MAX_UINT", [] >;
621def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE",
622  [(store_local (i32 R600_Reg32:$src1), R600_Reg32:$src0)]
623>;
624def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE",
625  [(truncstorei8_local i32:$src1, i32:$src0)]
626>;
627def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE",
628  [(truncstorei16_local i32:$src1, i32:$src0)]
629>;
630def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD",
631  [(set i32:$dst, (atomic_load_add_local i32:$src0, i32:$src1))]
632>;
633def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB",
634  [(set i32:$dst, (atomic_load_sub_local i32:$src0, i32:$src1))]
635>;
636def LDS_AND_RET : R600_LDS_1A1D_RET <0x29, "LDS_AND",
637  [(set i32:$dst, (atomic_load_and_local i32:$src0, i32:$src1))]
638>;
639def LDS_OR_RET : R600_LDS_1A1D_RET <0x2a, "LDS_OR",
640  [(set i32:$dst, (atomic_load_or_local i32:$src0, i32:$src1))]
641>;
642def LDS_XOR_RET : R600_LDS_1A1D_RET <0x2b, "LDS_XOR",
643  [(set i32:$dst, (atomic_load_xor_local i32:$src0, i32:$src1))]
644>;
645def LDS_MIN_INT_RET : R600_LDS_1A1D_RET <0x25, "LDS_MIN_INT",
646  [(set i32:$dst, (atomic_load_min_local i32:$src0, i32:$src1))]
647>;
648def LDS_MAX_INT_RET : R600_LDS_1A1D_RET <0x26, "LDS_MAX_INT",
649  [(set i32:$dst, (atomic_load_max_local i32:$src0, i32:$src1))]
650>;
651def LDS_MIN_UINT_RET : R600_LDS_1A1D_RET <0x27, "LDS_MIN_UINT",
652  [(set i32:$dst, (atomic_load_umin_local i32:$src0, i32:$src1))]
653>;
654def LDS_MAX_UINT_RET : R600_LDS_1A1D_RET <0x28, "LDS_MAX_UINT",
655  [(set i32:$dst, (atomic_load_umax_local i32:$src0, i32:$src1))]
656>;
657def LDS_WRXCHG_RET : R600_LDS_1A1D_RET <0x2d, "LDS_WRXCHG",
658  [(set i32:$dst, (atomic_swap_local i32:$src0, i32:$src1))]
659>;
660def LDS_CMPST_RET : R600_LDS_1A2D_RET <0x30, "LDS_CMPST",
661  [(set i32:$dst, (atomic_cmp_swap_local i32:$src0, i32:$src1, i32:$src2))]
662>;
663def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET",
664  [(set (i32 R600_Reg32:$dst), (load_local R600_Reg32:$src0))]
665>;
666def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET",
667  [(set i32:$dst, (sextloadi8_local i32:$src0))]
668>;
669def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET",
670  [(set i32:$dst, (az_extloadi8_local i32:$src0))]
671>;
672def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET",
673  [(set i32:$dst, (sextloadi16_local i32:$src0))]
674>;
675def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET",
676  [(set i32:$dst, (az_extloadi16_local i32:$src0))]
677>;
678
679// TRUNC is used for the FLT_TO_INT instructions to work around a
680// perceived problem where the rounding modes are applied differently
681// depending on the instruction and the slot they are in.
682// See:
683// https://bugs.freedesktop.org/show_bug.cgi?id=50232
684// Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
685//
686// XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
687// which do not need to be truncated since the fp values are 0.0f or 1.0f.
688// We should look into handling these cases separately.
689def : EGOrCaymanPat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
690
691def : EGOrCaymanPat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>;
692
693// SHA-256 Patterns
694defm : SHA256MaPattern <BFI_INT_eg, XOR_INT, R600_Reg64>;
695
696def EG_ExportSwz : ExportSwzInst {
697  let Word1{19-16} = 0; // BURST_COUNT
698  let Word1{20} = 0; // VALID_PIXEL_MODE
699  let Word1{21} = eop;
700  let Word1{29-22} = inst;
701  let Word1{30} = 0; // MARK
702  let Word1{31} = 1; // BARRIER
703}
704defm : ExportPattern<EG_ExportSwz, 83>;
705
706def EG_ExportBuf : ExportBufInst {
707  let Word1{19-16} = 0; // BURST_COUNT
708  let Word1{20} = 0; // VALID_PIXEL_MODE
709  let Word1{21} = eop;
710  let Word1{29-22} = inst;
711  let Word1{30} = 0; // MARK
712  let Word1{31} = 1; // BARRIER
713}
714defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
715
716def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
717  "TEX $COUNT @$ADDR"> {
718  let POP_COUNT = 0;
719}
720def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
721  "VTX $COUNT @$ADDR"> {
722  let POP_COUNT = 0;
723}
724def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
725  "LOOP_START_DX10 @$ADDR"> {
726  let POP_COUNT = 0;
727  let COUNT = 0;
728}
729def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
730  let POP_COUNT = 0;
731  let COUNT = 0;
732}
733def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
734  "LOOP_BREAK @$ADDR"> {
735  let POP_COUNT = 0;
736  let COUNT = 0;
737}
738def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
739  "CONTINUE @$ADDR"> {
740  let POP_COUNT = 0;
741  let COUNT = 0;
742}
743def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
744  "JUMP @$ADDR POP:$POP_COUNT"> {
745  let COUNT = 0;
746}
747def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
748                              "PUSH @$ADDR POP:$POP_COUNT"> {
749  let COUNT = 0;
750}
751def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
752  "ELSE @$ADDR POP:$POP_COUNT"> {
753  let COUNT = 0;
754}
755def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
756  let ADDR = 0;
757  let COUNT = 0;
758  let POP_COUNT = 0;
759}
760def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
761  "POP @$ADDR POP:$POP_COUNT"> {
762  let COUNT = 0;
763}
764def CF_END_EG :  CF_CLAUSE_EG<0, (ins), "CF_END"> {
765  let COUNT = 0;
766  let POP_COUNT = 0;
767  let ADDR = 0;
768  let END_OF_PROGRAM = 1;
769}
770
771} // End Predicates = [isEGorCayman]
772