xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/EXPInstructions.td (revision 1db9f3b21e39176dd5b67cf8ac378633b172463e) 
1//===-- EXPInstructions.td - Export Instruction Definitions ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// EXP classes
11//===----------------------------------------------------------------------===//
12
13class EXPCommon<bit row, bit done, string asm = ""> : InstSI<
14  (outs),
15  (ins exp_tgt:$tgt,
16       ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
17       exp_vm:$vm, exp_compr:$compr, i32imm:$en),
18  asm> {
19  let EXP = 1;
20  let EXP_CNT = 1;
21  let mayLoad = done;
22  let mayStore = 1;
23  let maybeAtomic = 0;
24  let UseNamedOperandTable = 1;
25  let Uses = !if(row, [EXEC, M0], [EXEC]);
26  let SchedRW = [WriteExport];
27  let DisableWQM = 1;
28}
29
30class EXP_Pseudo<bit row, bit done>
31  : EXPCommon<row, done>, SIMCInstr<NAME, SIEncodingFamily.NONE> {
32  let isPseudo = 1;
33  let isCodeGenOnly = 1;
34}
35
36// Real instruction with optional asm operands "compr" and "vm".
37class EXP_Real_ComprVM<bit done, string pseudo, int subtarget>
38  : EXPCommon<0, done, "exp$tgt $src0, $src1, $src2, $src3"
39                       #!if(done, " done", "")#"$compr$vm">,
40    SIMCInstr<pseudo, subtarget> {
41  let AsmMatchConverter = "cvtExp";
42}
43
44// Real instruction with optional asm operand "row_en".
45class EXP_Real_Row<bit row, bit done, string pseudo, int subtarget, string name = "exp">
46  : EXPCommon<row, done, name#"$tgt $src0, $src1, $src2, $src3"
47                         #!if(done, " done", "")#!if(row, " row_en", "")>,
48    SIMCInstr<pseudo, subtarget> {
49  let AsmMatchConverter = "cvtExp";
50}
51
52//===----------------------------------------------------------------------===//
53// EXP Instructions
54//===----------------------------------------------------------------------===//
55
56// DONE variants have mayLoad = 1.
57// ROW variants have an implicit use of M0.
58let SubtargetPredicate = isNotGFX90APlus in {
59def EXP          : EXP_Pseudo<0, 0>;
60def EXP_DONE     : EXP_Pseudo<0, 1>;
61def EXP_ROW      : EXP_Pseudo<1, 0>;
62def EXP_ROW_DONE : EXP_Pseudo<1, 1>;
63} // let SubtargetPredicate = isNotGFX90APlus
64
65//===----------------------------------------------------------------------===//
66// SI
67//===----------------------------------------------------------------------===//
68
69class EXP_Real_si<bit _done, string pseudo>
70  : EXP_Real_ComprVM<_done, pseudo, SIEncodingFamily.SI>, EXPe_ComprVM {
71  let AssemblerPredicate = isGFX6GFX7;
72  let DecoderNamespace = "GFX6GFX7";
73  let done = _done;
74}
75
76def EXP_si      : EXP_Real_si<0, "EXP">;
77def EXP_DONE_si : EXP_Real_si<1, "EXP_DONE">;
78
79//===----------------------------------------------------------------------===//
80// VI
81//===----------------------------------------------------------------------===//
82
83class EXP_Real_vi<bit _done, string pseudo>
84  : EXP_Real_ComprVM<_done, pseudo, SIEncodingFamily.VI>, EXPe_vi {
85  let AssemblerPredicate = isGFX8GFX9;
86  let SubtargetPredicate = isNotGFX90APlus;
87  let DecoderNamespace = "GFX8";
88  let done = _done;
89}
90
91def EXP_vi      : EXP_Real_vi<0, "EXP">;
92def EXP_DONE_vi : EXP_Real_vi<1, "EXP_DONE">;
93
94//===----------------------------------------------------------------------===//
95// GFX10
96//===----------------------------------------------------------------------===//
97
98class EXP_Real_gfx10<bit _done, string pseudo>
99  : EXP_Real_ComprVM<_done, pseudo, SIEncodingFamily.GFX10>, EXPe_ComprVM {
100  let AssemblerPredicate = isGFX10Only;
101  let DecoderNamespace = "GFX10";
102  let done = _done;
103}
104
105def EXP_gfx10      : EXP_Real_gfx10<0, "EXP">;
106def EXP_DONE_gfx10 : EXP_Real_gfx10<1, "EXP_DONE">;
107
108//===----------------------------------------------------------------------===//
109// GFX11
110//===----------------------------------------------------------------------===//
111
112class EXP_Real_gfx11<bit _row, bit _done, string pseudo>
113  : EXP_Real_Row<_row, _done, pseudo, SIEncodingFamily.GFX11>, EXPe_Row {
114  let AssemblerPredicate = isGFX11Only;
115  let DecoderNamespace = "GFX11";
116  let row = _row;
117  let done = _done;
118}
119
120def EXP_gfx11          : EXP_Real_gfx11<0, 0, "EXP">;
121def EXP_DONE_gfx11     : EXP_Real_gfx11<0, 1, "EXP_DONE">;
122def EXP_ROW_gfx11      : EXP_Real_gfx11<1, 0, "EXP_ROW">;
123def EXP_ROW_DONE_gfx11 : EXP_Real_gfx11<1, 1, "EXP_ROW_DONE">;
124
125//===----------------------------------------------------------------------===//
126// GFX12+
127//===----------------------------------------------------------------------===//
128
129class VEXPORT_Real_gfx12<bit _row, bit _done, string pseudo>
130  : EXP_Real_Row<_row, _done, pseudo, SIEncodingFamily.GFX12, "export">,
131    EXPe_Row, MnemonicAlias<"exp", "export">, Requires<[isGFX12Plus]> {
132  let AssemblerPredicate = isGFX12Plus;
133  let DecoderNamespace = "GFX12";
134  let row = _row;
135  let done = _done;
136}
137
138def EXPORT_gfx12          : VEXPORT_Real_gfx12<0, 0, "EXP">;
139def EXPORT_DONE_gfx12     : VEXPORT_Real_gfx12<0, 1, "EXP_DONE">;
140def EXPORT_ROW_gfx12      : VEXPORT_Real_gfx12<1, 0, "EXP_ROW">;
141def EXPORT_ROW_DONE_gfx12 : VEXPORT_Real_gfx12<1, 1, "EXP_ROW_DONE">;
142
143//===----------------------------------------------------------------------===//
144// EXP Patterns
145//===----------------------------------------------------------------------===//
146
147class ExpPattern<ValueType vt, Instruction Inst, int done_val> : GCNPat<
148  (int_amdgcn_exp timm:$tgt, timm:$en,
149                  (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
150                  (vt ExpSrc2:$src2), (vt ExpSrc3:$src3),
151                  done_val, timm:$vm),
152  (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
153        ExpSrc2:$src2, ExpSrc3:$src3, timm:$vm, 0, timm:$en)
154>;
155
156class ExpRowPattern<ValueType vt, Instruction Inst, int done_val> : GCNPat<
157  (int_amdgcn_exp_row timm:$tgt, timm:$en,
158                      (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
159                      (vt ExpSrc2:$src2), (vt ExpSrc3:$src3),
160                      done_val, M0),
161  (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
162        ExpSrc2:$src2, ExpSrc3:$src3, 0, 0, timm:$en)
163>;
164
165class ExpComprPattern<ValueType vt, Instruction Inst, int done_val> : GCNPat<
166  (int_amdgcn_exp_compr timm:$tgt, timm:$en,
167                        (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
168                        done_val, timm:$vm),
169  (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
170        (IMPLICIT_DEF), (IMPLICIT_DEF), timm:$vm, 1, timm:$en)
171>;
172
173// FIXME: The generated DAG matcher seems to have strange behavior
174// with a 1-bit literal to match, so use a -1 for checking a true
175// 1-bit value.
176def : ExpPattern<i32, EXP, 0>;
177def : ExpPattern<i32, EXP_DONE, -1>;
178def : ExpPattern<f32, EXP, 0>;
179def : ExpPattern<f32, EXP_DONE, -1>;
180
181def : ExpRowPattern<i32, EXP_ROW, 0>;
182def : ExpRowPattern<i32, EXP_ROW_DONE, -1>;
183def : ExpRowPattern<f32, EXP_ROW, 0>;
184def : ExpRowPattern<f32, EXP_ROW_DONE, -1>;
185
186def : ExpComprPattern<v2i16, EXP, 0>;
187def : ExpComprPattern<v2i16, EXP_DONE, -1>;
188def : ExpComprPattern<v2f16, EXP, 0>;
189def : ExpComprPattern<v2f16, EXP_DONE, -1>;
190