xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71) 
1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //===----------------------------------------------------------------------===//
10 //
11 /// \file
12 ///
13 /// This file contains definition for AMDGPU ISA disassembler
14 //
15 //===----------------------------------------------------------------------===//
16 
17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
18 
19 #include "Disassembler/AMDGPUDisassembler.h"
20 #include "AMDGPU.h"
21 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
22 #include "SIDefines.h"
23 #include "TargetInfo/AMDGPUTargetInfo.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 #include "llvm-c/Disassembler.h"
26 #include "llvm/ADT/APInt.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/BinaryFormat/ELF.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
33 #include "llvm/MC/MCExpr.h"
34 #include "llvm/MC/MCFixedLenDisassembler.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSubtargetInfo.h"
37 #include "llvm/Support/Endian.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include <algorithm>
43 #include <cassert>
44 #include <cstddef>
45 #include <cstdint>
46 #include <iterator>
47 #include <tuple>
48 #include <vector>
49 
50 using namespace llvm;
51 
52 #define DEBUG_TYPE "amdgpu-disassembler"
53 
54 #define SGPR_MAX (isGFX10() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
55                             : AMDGPU::EncValues::SGPR_MAX_SI)
56 
57 using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
58 
59 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
60                                        MCContext &Ctx,
61                                        MCInstrInfo const *MCII) :
62   MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
63   TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
64 
65   // ToDo: AMDGPUDisassembler supports only VI ISA.
66   if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10())
67     report_fatal_error("Disassembly not yet supported for subtarget");
68 }
69 
70 inline static MCDisassembler::DecodeStatus
71 addOperand(MCInst &Inst, const MCOperand& Opnd) {
72   Inst.addOperand(Opnd);
73   return Opnd.isValid() ?
74     MCDisassembler::Success :
75     MCDisassembler::Fail;
76 }
77 
78 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
79                                 uint16_t NameIdx) {
80   int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
81   if (OpIdx != -1) {
82     auto I = MI.begin();
83     std::advance(I, OpIdx);
84     MI.insert(I, Op);
85   }
86   return OpIdx;
87 }
88 
89 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
90                                        uint64_t Addr, const void *Decoder) {
91   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
92 
93   // Our branches take a simm16, but we need two extra bits to account for the
94   // factor of 4.
95   APInt SignedOffset(18, Imm * 4, true);
96   int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
97 
98   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
99     return MCDisassembler::Success;
100   return addOperand(Inst, MCOperand::createImm(Imm));
101 }
102 
103 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm,
104                                      uint64_t Addr, const void *Decoder) {
105   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
106   int64_t Offset;
107   if (DAsm->isVI()) {         // VI supports 20-bit unsigned offsets.
108     Offset = Imm & 0xFFFFF;
109   } else {                    // GFX9+ supports 21-bit signed offsets.
110     Offset = SignExtend64<21>(Imm);
111   }
112   return addOperand(Inst, MCOperand::createImm(Offset));
113 }
114 
115 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val,
116                                   uint64_t Addr, const void *Decoder) {
117   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
118   return addOperand(Inst, DAsm->decodeBoolReg(Val));
119 }
120 
121 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
122 static DecodeStatus StaticDecoderName(MCInst &Inst, \
123                                        unsigned Imm, \
124                                        uint64_t /*Addr*/, \
125                                        const void *Decoder) { \
126   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
127   return addOperand(Inst, DAsm->DecoderName(Imm)); \
128 }
129 
130 #define DECODE_OPERAND_REG(RegClass) \
131 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
132 
133 DECODE_OPERAND_REG(VGPR_32)
134 DECODE_OPERAND_REG(VRegOrLds_32)
135 DECODE_OPERAND_REG(VS_32)
136 DECODE_OPERAND_REG(VS_64)
137 DECODE_OPERAND_REG(VS_128)
138 
139 DECODE_OPERAND_REG(VReg_64)
140 DECODE_OPERAND_REG(VReg_96)
141 DECODE_OPERAND_REG(VReg_128)
142 
143 DECODE_OPERAND_REG(SReg_32)
144 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
145 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
146 DECODE_OPERAND_REG(SRegOrLds_32)
147 DECODE_OPERAND_REG(SReg_64)
148 DECODE_OPERAND_REG(SReg_64_XEXEC)
149 DECODE_OPERAND_REG(SReg_128)
150 DECODE_OPERAND_REG(SReg_256)
151 DECODE_OPERAND_REG(SReg_512)
152 
153 DECODE_OPERAND_REG(AGPR_32)
154 DECODE_OPERAND_REG(AReg_128)
155 DECODE_OPERAND_REG(AReg_512)
156 DECODE_OPERAND_REG(AReg_1024)
157 DECODE_OPERAND_REG(AV_32)
158 DECODE_OPERAND_REG(AV_64)
159 
160 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst,
161                                          unsigned Imm,
162                                          uint64_t Addr,
163                                          const void *Decoder) {
164   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
165   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
166 }
167 
168 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,
169                                          unsigned Imm,
170                                          uint64_t Addr,
171                                          const void *Decoder) {
172   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
173   return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
174 }
175 
176 static DecodeStatus decodeOperand_VS_16(MCInst &Inst,
177                                         unsigned Imm,
178                                         uint64_t Addr,
179                                         const void *Decoder) {
180   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
181   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
182 }
183 
184 static DecodeStatus decodeOperand_VS_32(MCInst &Inst,
185                                         unsigned Imm,
186                                         uint64_t Addr,
187                                         const void *Decoder) {
188   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
189   return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm));
190 }
191 
192 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst,
193                                            unsigned Imm,
194                                            uint64_t Addr,
195                                            const void *Decoder) {
196   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
197   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512));
198 }
199 
200 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst,
201                                            unsigned Imm,
202                                            uint64_t Addr,
203                                            const void *Decoder) {
204   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
205   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512));
206 }
207 
208 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst,
209                                             unsigned Imm,
210                                             uint64_t Addr,
211                                             const void *Decoder) {
212   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
213   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512));
214 }
215 
216 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst,
217                                           unsigned Imm,
218                                           uint64_t Addr,
219                                           const void *Decoder) {
220   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
221   return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm));
222 }
223 
224 static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst,
225                                          unsigned Imm,
226                                          uint64_t Addr,
227                                          const void *Decoder) {
228   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
229   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm));
230 }
231 
232 #define DECODE_SDWA(DecName) \
233 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
234 
235 DECODE_SDWA(Src32)
236 DECODE_SDWA(Src16)
237 DECODE_SDWA(VopcDst)
238 
239 #include "AMDGPUGenDisassemblerTables.inc"
240 
241 //===----------------------------------------------------------------------===//
242 //
243 //===----------------------------------------------------------------------===//
244 
245 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
246   assert(Bytes.size() >= sizeof(T));
247   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
248   Bytes = Bytes.slice(sizeof(T));
249   return Res;
250 }
251 
252 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
253                                                MCInst &MI,
254                                                uint64_t Inst,
255                                                uint64_t Address) const {
256   assert(MI.getOpcode() == 0);
257   assert(MI.getNumOperands() == 0);
258   MCInst TmpInst;
259   HasLiteral = false;
260   const auto SavedBytes = Bytes;
261   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
262     MI = TmpInst;
263     return MCDisassembler::Success;
264   }
265   Bytes = SavedBytes;
266   return MCDisassembler::Fail;
267 }
268 
269 static bool isValidDPP8(const MCInst &MI) {
270   using namespace llvm::AMDGPU::DPP;
271   int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
272   assert(FiIdx != -1);
273   if ((unsigned)FiIdx >= MI.getNumOperands())
274     return false;
275   unsigned Fi = MI.getOperand(FiIdx).getImm();
276   return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
277 }
278 
279 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
280                                                 ArrayRef<uint8_t> Bytes_,
281                                                 uint64_t Address,
282                                                 raw_ostream &CS) const {
283   CommentStream = &CS;
284   bool IsSDWA = false;
285 
286   unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
287   Bytes = Bytes_.slice(0, MaxInstBytesNum);
288 
289   DecodeStatus Res = MCDisassembler::Fail;
290   do {
291     // ToDo: better to switch encoding length using some bit predicate
292     // but it is unknown yet, so try all we can
293 
294     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
295     // encodings
296     if (Bytes.size() >= 8) {
297       const uint64_t QW = eatBytes<uint64_t>(Bytes);
298 
299       if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) {
300         Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address);
301         if (Res) {
302           if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8)
303               == -1)
304             break;
305           if (convertDPP8Inst(MI) == MCDisassembler::Success)
306             break;
307           MI = MCInst(); // clear
308         }
309       }
310 
311       Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address);
312       if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
313         break;
314 
315       MI = MCInst(); // clear
316 
317       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
318       if (Res) break;
319 
320       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
321       if (Res) { IsSDWA = true;  break; }
322 
323       Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
324       if (Res) { IsSDWA = true;  break; }
325 
326       Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
327       if (Res) { IsSDWA = true;  break; }
328 
329       if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
330         Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
331         if (Res)
332           break;
333       }
334 
335       // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
336       // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
337       // table first so we print the correct name.
338       if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
339         Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
340         if (Res)
341           break;
342       }
343     }
344 
345     // Reinitialize Bytes as DPP64 could have eaten too much
346     Bytes = Bytes_.slice(0, MaxInstBytesNum);
347 
348     // Try decode 32-bit instruction
349     if (Bytes.size() < 4) break;
350     const uint32_t DW = eatBytes<uint32_t>(Bytes);
351     Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
352     if (Res) break;
353 
354     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
355     if (Res) break;
356 
357     Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
358     if (Res) break;
359 
360     if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) {
361       Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address);
362       if (Res) break;
363     }
364 
365     Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address);
366     if (Res) break;
367 
368     if (Bytes.size() < 4) break;
369     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
370     Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
371     if (Res) break;
372 
373     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
374     if (Res) break;
375 
376     Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
377     if (Res) break;
378 
379     Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
380   } while (false);
381 
382   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
383               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
384               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
385               MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
386               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
387               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
388               MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
389     // Insert dummy unused src2_modifiers.
390     insertNamedMCOperand(MI, MCOperand::createImm(0),
391                          AMDGPU::OpName::src2_modifiers);
392   }
393 
394   if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
395     int VAddr0Idx =
396         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
397     int RsrcIdx =
398         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
399     unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
400     if (VAddr0Idx >= 0 && NSAArgs > 0) {
401       unsigned NSAWords = (NSAArgs + 3) / 4;
402       if (Bytes.size() < 4 * NSAWords) {
403         Res = MCDisassembler::Fail;
404       } else {
405         for (unsigned i = 0; i < NSAArgs; ++i) {
406           MI.insert(MI.begin() + VAddr0Idx + 1 + i,
407                     decodeOperand_VGPR_32(Bytes[i]));
408         }
409         Bytes = Bytes.slice(4 * NSAWords);
410       }
411     }
412 
413     if (Res)
414       Res = convertMIMGInst(MI);
415   }
416 
417   if (Res && IsSDWA)
418     Res = convertSDWAInst(MI);
419 
420   int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
421                                               AMDGPU::OpName::vdst_in);
422   if (VDstIn_Idx != -1) {
423     int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
424                            MCOI::OperandConstraint::TIED_TO);
425     if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
426          !MI.getOperand(VDstIn_Idx).isReg() ||
427          MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
428       if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
429         MI.erase(&MI.getOperand(VDstIn_Idx));
430       insertNamedMCOperand(MI,
431         MCOperand::createReg(MI.getOperand(Tied).getReg()),
432         AMDGPU::OpName::vdst_in);
433     }
434   }
435 
436   // if the opcode was not recognized we'll assume a Size of 4 bytes
437   // (unless there are fewer bytes left)
438   Size = Res ? (MaxInstBytesNum - Bytes.size())
439              : std::min((size_t)4, Bytes_.size());
440   return Res;
441 }
442 
443 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
444   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
445       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
446     if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
447       // VOPC - insert clamp
448       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
449   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
450     int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
451     if (SDst != -1) {
452       // VOPC - insert VCC register as sdst
453       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
454                            AMDGPU::OpName::sdst);
455     } else {
456       // VOP1/2 - insert omod if present in instruction
457       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
458     }
459   }
460   return MCDisassembler::Success;
461 }
462 
463 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
464   unsigned Opc = MI.getOpcode();
465   unsigned DescNumOps = MCII->get(Opc).getNumOperands();
466 
467   // Insert dummy unused src modifiers.
468   if (MI.getNumOperands() < DescNumOps &&
469       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
470     insertNamedMCOperand(MI, MCOperand::createImm(0),
471                          AMDGPU::OpName::src0_modifiers);
472 
473   if (MI.getNumOperands() < DescNumOps &&
474       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
475     insertNamedMCOperand(MI, MCOperand::createImm(0),
476                          AMDGPU::OpName::src1_modifiers);
477 
478   return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail;
479 }
480 
481 // Note that before gfx10, the MIMG encoding provided no information about
482 // VADDR size. Consequently, decoded instructions always show address as if it
483 // has 1 dword, which could be not really so.
484 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
485 
486   int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
487                                            AMDGPU::OpName::vdst);
488 
489   int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
490                                             AMDGPU::OpName::vdata);
491   int VAddr0Idx =
492       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
493   int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
494                                             AMDGPU::OpName::dmask);
495 
496   int TFEIdx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
497                                             AMDGPU::OpName::tfe);
498   int D16Idx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
499                                             AMDGPU::OpName::d16);
500 
501   assert(VDataIdx != -1);
502   assert(DMaskIdx != -1);
503   assert(TFEIdx != -1);
504 
505   const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
506   bool IsAtomic = (VDstIdx != -1);
507   bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
508 
509   bool IsNSA = false;
510   unsigned AddrSize = Info->VAddrDwords;
511 
512   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
513     unsigned DimIdx =
514         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
515     const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
516         AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
517     const AMDGPU::MIMGDimInfo *Dim =
518         AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm());
519 
520     AddrSize = BaseOpcode->NumExtraArgs +
521                (BaseOpcode->Gradients ? Dim->NumGradients : 0) +
522                (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
523                (BaseOpcode->LodOrClampOrMip ? 1 : 0);
524     IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA;
525     if (!IsNSA) {
526       if (AddrSize > 8)
527         AddrSize = 16;
528       else if (AddrSize > 4)
529         AddrSize = 8;
530     } else {
531       if (AddrSize > Info->VAddrDwords) {
532         // The NSA encoding does not contain enough operands for the combination
533         // of base opcode / dimension. Should this be an error?
534         return MCDisassembler::Success;
535       }
536     }
537   }
538 
539   unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
540   unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u);
541 
542   bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
543   if (D16 && AMDGPU::hasPackedD16(STI)) {
544     DstSize = (DstSize + 1) / 2;
545   }
546 
547   // FIXME: Add tfe support
548   if (MI.getOperand(TFEIdx).getImm())
549     return MCDisassembler::Success;
550 
551   if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
552     return MCDisassembler::Success;
553 
554   int NewOpcode =
555       AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
556   if (NewOpcode == -1)
557     return MCDisassembler::Success;
558 
559   // Widen the register to the correct number of enabled channels.
560   unsigned NewVdata = AMDGPU::NoRegister;
561   if (DstSize != Info->VDataDwords) {
562     auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
563 
564     // Get first subregister of VData
565     unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
566     unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
567     Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
568 
569     NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
570                                        &MRI.getRegClass(DataRCID));
571     if (NewVdata == AMDGPU::NoRegister) {
572       // It's possible to encode this such that the low register + enabled
573       // components exceeds the register count.
574       return MCDisassembler::Success;
575     }
576   }
577 
578   unsigned NewVAddr0 = AMDGPU::NoRegister;
579   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA &&
580       AddrSize != Info->VAddrDwords) {
581     unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg();
582     unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0);
583     VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
584 
585     auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
586     NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0,
587                                         &MRI.getRegClass(AddrRCID));
588     if (NewVAddr0 == AMDGPU::NoRegister)
589       return MCDisassembler::Success;
590   }
591 
592   MI.setOpcode(NewOpcode);
593 
594   if (NewVdata != AMDGPU::NoRegister) {
595     MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
596 
597     if (IsAtomic) {
598       // Atomic operations have an additional operand (a copy of data)
599       MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
600     }
601   }
602 
603   if (NewVAddr0 != AMDGPU::NoRegister) {
604     MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
605   } else if (IsNSA) {
606     assert(AddrSize <= Info->VAddrDwords);
607     MI.erase(MI.begin() + VAddr0Idx + AddrSize,
608              MI.begin() + VAddr0Idx + Info->VAddrDwords);
609   }
610 
611   return MCDisassembler::Success;
612 }
613 
614 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
615   return getContext().getRegisterInfo()->
616     getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
617 }
618 
619 inline
620 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
621                                          const Twine& ErrMsg) const {
622   *CommentStream << "Error: " + ErrMsg;
623 
624   // ToDo: add support for error operands to MCInst.h
625   // return MCOperand::createError(V);
626   return MCOperand();
627 }
628 
629 inline
630 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
631   return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
632 }
633 
634 inline
635 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
636                                                unsigned Val) const {
637   const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
638   if (Val >= RegCl.getNumRegs())
639     return errOperand(Val, Twine(getRegClassName(RegClassID)) +
640                            ": unknown register " + Twine(Val));
641   return createRegOperand(RegCl.getRegister(Val));
642 }
643 
644 inline
645 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
646                                                 unsigned Val) const {
647   // ToDo: SI/CI have 104 SGPRs, VI - 102
648   // Valery: here we accepting as much as we can, let assembler sort it out
649   int shift = 0;
650   switch (SRegClassID) {
651   case AMDGPU::SGPR_32RegClassID:
652   case AMDGPU::TTMP_32RegClassID:
653     break;
654   case AMDGPU::SGPR_64RegClassID:
655   case AMDGPU::TTMP_64RegClassID:
656     shift = 1;
657     break;
658   case AMDGPU::SGPR_128RegClassID:
659   case AMDGPU::TTMP_128RegClassID:
660   // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
661   // this bundle?
662   case AMDGPU::SGPR_256RegClassID:
663   case AMDGPU::TTMP_256RegClassID:
664     // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
665   // this bundle?
666   case AMDGPU::SGPR_512RegClassID:
667   case AMDGPU::TTMP_512RegClassID:
668     shift = 2;
669     break;
670   // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
671   // this bundle?
672   default:
673     llvm_unreachable("unhandled register class");
674   }
675 
676   if (Val % (1 << shift)) {
677     *CommentStream << "Warning: " << getRegClassName(SRegClassID)
678                    << ": scalar reg isn't aligned " << Val;
679   }
680 
681   return createRegOperand(SRegClassID, Val >> shift);
682 }
683 
684 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
685   return decodeSrcOp(OPW32, Val);
686 }
687 
688 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
689   return decodeSrcOp(OPW64, Val);
690 }
691 
692 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const {
693   return decodeSrcOp(OPW128, Val);
694 }
695 
696 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const {
697   return decodeSrcOp(OPW16, Val);
698 }
699 
700 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const {
701   return decodeSrcOp(OPWV216, Val);
702 }
703 
704 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
705   // Some instructions have operand restrictions beyond what the encoding
706   // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
707   // high bit.
708   Val &= 255;
709 
710   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
711 }
712 
713 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const {
714   return decodeSrcOp(OPW32, Val);
715 }
716 
717 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const {
718   return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255);
719 }
720 
721 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const {
722   return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255);
723 }
724 
725 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const {
726   return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255);
727 }
728 
729 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const {
730   return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255);
731 }
732 
733 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const {
734   return decodeSrcOp(OPW32, Val);
735 }
736 
737 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const {
738   return decodeSrcOp(OPW64, Val);
739 }
740 
741 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
742   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
743 }
744 
745 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
746   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
747 }
748 
749 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
750   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
751 }
752 
753 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const {
754   return createRegOperand(AMDGPU::VReg_256RegClassID, Val);
755 }
756 
757 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const {
758   return createRegOperand(AMDGPU::VReg_512RegClassID, Val);
759 }
760 
761 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
762   // table-gen generated disassembler doesn't care about operand types
763   // leaving only registry class so SSrc_32 operand turns into SReg_32
764   // and therefore we accept immediates and literals here as well
765   return decodeSrcOp(OPW32, Val);
766 }
767 
768 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC(
769   unsigned Val) const {
770   // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
771   return decodeOperand_SReg_32(Val);
772 }
773 
774 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI(
775   unsigned Val) const {
776   // SReg_32_XM0 is SReg_32 without EXEC_HI
777   return decodeOperand_SReg_32(Val);
778 }
779 
780 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const {
781   // table-gen generated disassembler doesn't care about operand types
782   // leaving only registry class so SSrc_32 operand turns into SReg_32
783   // and therefore we accept immediates and literals here as well
784   return decodeSrcOp(OPW32, Val);
785 }
786 
787 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
788   return decodeSrcOp(OPW64, Val);
789 }
790 
791 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const {
792   return decodeSrcOp(OPW64, Val);
793 }
794 
795 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
796   return decodeSrcOp(OPW128, Val);
797 }
798 
799 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
800   return decodeDstOp(OPW256, Val);
801 }
802 
803 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
804   return decodeDstOp(OPW512, Val);
805 }
806 
807 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
808   // For now all literal constants are supposed to be unsigned integer
809   // ToDo: deal with signed/unsigned 64-bit integer constants
810   // ToDo: deal with float/double constants
811   if (!HasLiteral) {
812     if (Bytes.size() < 4) {
813       return errOperand(0, "cannot read literal, inst bytes left " +
814                         Twine(Bytes.size()));
815     }
816     HasLiteral = true;
817     Literal = eatBytes<uint32_t>(Bytes);
818   }
819   return MCOperand::createImm(Literal);
820 }
821 
822 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
823   using namespace AMDGPU::EncValues;
824 
825   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
826   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
827     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
828     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
829       // Cast prevents negative overflow.
830 }
831 
832 static int64_t getInlineImmVal32(unsigned Imm) {
833   switch (Imm) {
834   case 240:
835     return FloatToBits(0.5f);
836   case 241:
837     return FloatToBits(-0.5f);
838   case 242:
839     return FloatToBits(1.0f);
840   case 243:
841     return FloatToBits(-1.0f);
842   case 244:
843     return FloatToBits(2.0f);
844   case 245:
845     return FloatToBits(-2.0f);
846   case 246:
847     return FloatToBits(4.0f);
848   case 247:
849     return FloatToBits(-4.0f);
850   case 248: // 1 / (2 * PI)
851     return 0x3e22f983;
852   default:
853     llvm_unreachable("invalid fp inline imm");
854   }
855 }
856 
857 static int64_t getInlineImmVal64(unsigned Imm) {
858   switch (Imm) {
859   case 240:
860     return DoubleToBits(0.5);
861   case 241:
862     return DoubleToBits(-0.5);
863   case 242:
864     return DoubleToBits(1.0);
865   case 243:
866     return DoubleToBits(-1.0);
867   case 244:
868     return DoubleToBits(2.0);
869   case 245:
870     return DoubleToBits(-2.0);
871   case 246:
872     return DoubleToBits(4.0);
873   case 247:
874     return DoubleToBits(-4.0);
875   case 248: // 1 / (2 * PI)
876     return 0x3fc45f306dc9c882;
877   default:
878     llvm_unreachable("invalid fp inline imm");
879   }
880 }
881 
882 static int64_t getInlineImmVal16(unsigned Imm) {
883   switch (Imm) {
884   case 240:
885     return 0x3800;
886   case 241:
887     return 0xB800;
888   case 242:
889     return 0x3C00;
890   case 243:
891     return 0xBC00;
892   case 244:
893     return 0x4000;
894   case 245:
895     return 0xC000;
896   case 246:
897     return 0x4400;
898   case 247:
899     return 0xC400;
900   case 248: // 1 / (2 * PI)
901     return 0x3118;
902   default:
903     llvm_unreachable("invalid fp inline imm");
904   }
905 }
906 
907 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) {
908   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN
909       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
910 
911   // ToDo: case 248: 1/(2*PI) - is allowed only on VI
912   switch (Width) {
913   case OPW32:
914   case OPW128: // splat constants
915   case OPW512:
916   case OPW1024:
917     return MCOperand::createImm(getInlineImmVal32(Imm));
918   case OPW64:
919     return MCOperand::createImm(getInlineImmVal64(Imm));
920   case OPW16:
921   case OPWV216:
922     return MCOperand::createImm(getInlineImmVal16(Imm));
923   default:
924     llvm_unreachable("implement me");
925   }
926 }
927 
928 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
929   using namespace AMDGPU;
930 
931   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
932   switch (Width) {
933   default: // fall
934   case OPW32:
935   case OPW16:
936   case OPWV216:
937     return VGPR_32RegClassID;
938   case OPW64: return VReg_64RegClassID;
939   case OPW128: return VReg_128RegClassID;
940   }
941 }
942 
943 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const {
944   using namespace AMDGPU;
945 
946   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
947   switch (Width) {
948   default: // fall
949   case OPW32:
950   case OPW16:
951   case OPWV216:
952     return AGPR_32RegClassID;
953   case OPW64: return AReg_64RegClassID;
954   case OPW128: return AReg_128RegClassID;
955   case OPW256: return AReg_256RegClassID;
956   case OPW512: return AReg_512RegClassID;
957   case OPW1024: return AReg_1024RegClassID;
958   }
959 }
960 
961 
962 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
963   using namespace AMDGPU;
964 
965   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
966   switch (Width) {
967   default: // fall
968   case OPW32:
969   case OPW16:
970   case OPWV216:
971     return SGPR_32RegClassID;
972   case OPW64: return SGPR_64RegClassID;
973   case OPW128: return SGPR_128RegClassID;
974   case OPW256: return SGPR_256RegClassID;
975   case OPW512: return SGPR_512RegClassID;
976   }
977 }
978 
979 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
980   using namespace AMDGPU;
981 
982   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
983   switch (Width) {
984   default: // fall
985   case OPW32:
986   case OPW16:
987   case OPWV216:
988     return TTMP_32RegClassID;
989   case OPW64: return TTMP_64RegClassID;
990   case OPW128: return TTMP_128RegClassID;
991   case OPW256: return TTMP_256RegClassID;
992   case OPW512: return TTMP_512RegClassID;
993   }
994 }
995 
996 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
997   using namespace AMDGPU::EncValues;
998 
999   unsigned TTmpMin =
1000       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN;
1001   unsigned TTmpMax =
1002       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX;
1003 
1004   return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
1005 }
1006 
1007 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
1008   using namespace AMDGPU::EncValues;
1009 
1010   assert(Val < 1024); // enum10
1011 
1012   bool IsAGPR = Val & 512;
1013   Val &= 511;
1014 
1015   if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
1016     return createRegOperand(IsAGPR ? getAgprClassId(Width)
1017                                    : getVgprClassId(Width), Val - VGPR_MIN);
1018   }
1019   if (Val <= SGPR_MAX) {
1020     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1021     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1022   }
1023 
1024   int TTmpIdx = getTTmpIdx(Val);
1025   if (TTmpIdx >= 0) {
1026     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1027   }
1028 
1029   if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1030     return decodeIntImmed(Val);
1031 
1032   if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1033     return decodeFPImmed(Width, Val);
1034 
1035   if (Val == LITERAL_CONST)
1036     return decodeLiteralConstant();
1037 
1038   switch (Width) {
1039   case OPW32:
1040   case OPW16:
1041   case OPWV216:
1042     return decodeSpecialReg32(Val);
1043   case OPW64:
1044     return decodeSpecialReg64(Val);
1045   default:
1046     llvm_unreachable("unexpected immediate type");
1047   }
1048 }
1049 
1050 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const {
1051   using namespace AMDGPU::EncValues;
1052 
1053   assert(Val < 128);
1054   assert(Width == OPW256 || Width == OPW512);
1055 
1056   if (Val <= SGPR_MAX) {
1057     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1058     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1059   }
1060 
1061   int TTmpIdx = getTTmpIdx(Val);
1062   if (TTmpIdx >= 0) {
1063     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1064   }
1065 
1066   llvm_unreachable("unknown dst register");
1067 }
1068 
1069 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
1070   using namespace AMDGPU;
1071 
1072   switch (Val) {
1073   case 102: return createRegOperand(FLAT_SCR_LO);
1074   case 103: return createRegOperand(FLAT_SCR_HI);
1075   case 104: return createRegOperand(XNACK_MASK_LO);
1076   case 105: return createRegOperand(XNACK_MASK_HI);
1077   case 106: return createRegOperand(VCC_LO);
1078   case 107: return createRegOperand(VCC_HI);
1079   case 108: return createRegOperand(TBA_LO);
1080   case 109: return createRegOperand(TBA_HI);
1081   case 110: return createRegOperand(TMA_LO);
1082   case 111: return createRegOperand(TMA_HI);
1083   case 124: return createRegOperand(M0);
1084   case 125: return createRegOperand(SGPR_NULL);
1085   case 126: return createRegOperand(EXEC_LO);
1086   case 127: return createRegOperand(EXEC_HI);
1087   case 235: return createRegOperand(SRC_SHARED_BASE);
1088   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1089   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1090   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1091   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1092   case 251: return createRegOperand(SRC_VCCZ);
1093   case 252: return createRegOperand(SRC_EXECZ);
1094   case 253: return createRegOperand(SRC_SCC);
1095   case 254: return createRegOperand(LDS_DIRECT);
1096   default: break;
1097   }
1098   return errOperand(Val, "unknown operand encoding " + Twine(Val));
1099 }
1100 
1101 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
1102   using namespace AMDGPU;
1103 
1104   switch (Val) {
1105   case 102: return createRegOperand(FLAT_SCR);
1106   case 104: return createRegOperand(XNACK_MASK);
1107   case 106: return createRegOperand(VCC);
1108   case 108: return createRegOperand(TBA);
1109   case 110: return createRegOperand(TMA);
1110   case 125: return createRegOperand(SGPR_NULL);
1111   case 126: return createRegOperand(EXEC);
1112   case 235: return createRegOperand(SRC_SHARED_BASE);
1113   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1114   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1115   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1116   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1117   case 251: return createRegOperand(SRC_VCCZ);
1118   case 252: return createRegOperand(SRC_EXECZ);
1119   case 253: return createRegOperand(SRC_SCC);
1120   default: break;
1121   }
1122   return errOperand(Val, "unknown operand encoding " + Twine(Val));
1123 }
1124 
1125 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
1126                                             const unsigned Val) const {
1127   using namespace AMDGPU::SDWA;
1128   using namespace AMDGPU::EncValues;
1129 
1130   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1131       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
1132     // XXX: cast to int is needed to avoid stupid warning:
1133     // compare with unsigned is always true
1134     if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
1135         Val <= SDWA9EncValues::SRC_VGPR_MAX) {
1136       return createRegOperand(getVgprClassId(Width),
1137                               Val - SDWA9EncValues::SRC_VGPR_MIN);
1138     }
1139     if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1140         Val <= (isGFX10() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
1141                           : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
1142       return createSRegOperand(getSgprClassId(Width),
1143                                Val - SDWA9EncValues::SRC_SGPR_MIN);
1144     }
1145     if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1146         Val <= SDWA9EncValues::SRC_TTMP_MAX) {
1147       return createSRegOperand(getTtmpClassId(Width),
1148                                Val - SDWA9EncValues::SRC_TTMP_MIN);
1149     }
1150 
1151     const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1152 
1153     if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1154       return decodeIntImmed(SVal);
1155 
1156     if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1157       return decodeFPImmed(Width, SVal);
1158 
1159     return decodeSpecialReg32(SVal);
1160   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
1161     return createRegOperand(getVgprClassId(Width), Val);
1162   }
1163   llvm_unreachable("unsupported target");
1164 }
1165 
1166 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {
1167   return decodeSDWASrc(OPW16, Val);
1168 }
1169 
1170 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
1171   return decodeSDWASrc(OPW32, Val);
1172 }
1173 
1174 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
1175   using namespace AMDGPU::SDWA;
1176 
1177   assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1178           STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
1179          "SDWAVopcDst should be present only on GFX9+");
1180 
1181   bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
1182 
1183   if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
1184     Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
1185 
1186     int TTmpIdx = getTTmpIdx(Val);
1187     if (TTmpIdx >= 0) {
1188       auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32);
1189       return createSRegOperand(TTmpClsId, TTmpIdx);
1190     } else if (Val > SGPR_MAX) {
1191       return IsWave64 ? decodeSpecialReg64(Val)
1192                       : decodeSpecialReg32(Val);
1193     } else {
1194       return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
1195     }
1196   } else {
1197     return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1198   }
1199 }
1200 
1201 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
1202   return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
1203     decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val);
1204 }
1205 
1206 bool AMDGPUDisassembler::isVI() const {
1207   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1208 }
1209 
1210 bool AMDGPUDisassembler::isGFX9() const {
1211   return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
1212 }
1213 
1214 bool AMDGPUDisassembler::isGFX10() const {
1215   return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
1216 }
1217 
1218 //===----------------------------------------------------------------------===//
1219 // AMDGPUSymbolizer
1220 //===----------------------------------------------------------------------===//
1221 
1222 // Try to find symbol name for specified label
1223 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
1224                                 raw_ostream &/*cStream*/, int64_t Value,
1225                                 uint64_t /*Address*/, bool IsBranch,
1226                                 uint64_t /*Offset*/, uint64_t /*InstSize*/) {
1227 
1228   if (!IsBranch) {
1229     return false;
1230   }
1231 
1232   auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
1233   if (!Symbols)
1234     return false;
1235 
1236   auto Result = std::find_if(Symbols->begin(), Symbols->end(),
1237                              [Value](const SymbolInfoTy& Val) {
1238                                 return Val.Addr == static_cast<uint64_t>(Value)
1239                                     && Val.Type == ELF::STT_NOTYPE;
1240                              });
1241   if (Result != Symbols->end()) {
1242     auto *Sym = Ctx.getOrCreateSymbol(Result->Name);
1243     const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
1244     Inst.addOperand(MCOperand::createExpr(Add));
1245     return true;
1246   }
1247   return false;
1248 }
1249 
1250 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream,
1251                                                        int64_t Value,
1252                                                        uint64_t Address) {
1253   llvm_unreachable("unimplemented");
1254 }
1255 
1256 //===----------------------------------------------------------------------===//
1257 // Initialization
1258 //===----------------------------------------------------------------------===//
1259 
1260 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
1261                               LLVMOpInfoCallback /*GetOpInfo*/,
1262                               LLVMSymbolLookupCallback /*SymbolLookUp*/,
1263                               void *DisInfo,
1264                               MCContext *Ctx,
1265                               std::unique_ptr<MCRelocationInfo> &&RelInfo) {
1266   return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
1267 }
1268 
1269 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
1270                                                 const MCSubtargetInfo &STI,
1271                                                 MCContext &Ctx) {
1272   return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
1273 }
1274 
1275 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() {
1276   TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(),
1277                                          createAMDGPUDisassembler);
1278   TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
1279                                        createAMDGPUSymbolizer);
1280 }
1281