1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, 49 MCInstrInfo const *MCII) : 50 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 51 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 52 53 // ToDo: AMDGPUDisassembler supports only VI ISA. 54 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 55 report_fatal_error("Disassembly not yet supported for subtarget"); 56 } 57 58 inline static MCDisassembler::DecodeStatus 59 addOperand(MCInst &Inst, const MCOperand& Opnd) { 60 Inst.addOperand(Opnd); 61 return Opnd.isValid() ? 62 MCDisassembler::Success : 63 MCDisassembler::Fail; 64 } 65 66 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 67 uint16_t NameIdx) { 68 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 69 if (OpIdx != -1) { 70 auto I = MI.begin(); 71 std::advance(I, OpIdx); 72 MI.insert(I, Op); 73 } 74 return OpIdx; 75 } 76 77 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 78 uint64_t Addr, 79 const MCDisassembler *Decoder) { 80 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 81 82 // Our branches take a simm16, but we need two extra bits to account for the 83 // factor of 4. 84 APInt SignedOffset(18, Imm * 4, true); 85 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 86 87 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 88 return MCDisassembler::Success; 89 return addOperand(Inst, MCOperand::createImm(Imm)); 90 } 91 92 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 93 const MCDisassembler *Decoder) { 94 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 95 int64_t Offset; 96 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 112 uint64_t /*Addr*/, \ 113 const MCDisassembler *Decoder) { \ 114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 115 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 116 } 117 118 #define DECODE_OPERAND_REG(RegClass) \ 119 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 120 121 DECODE_OPERAND_REG(VGPR_32) 122 DECODE_OPERAND_REG(VGPR_32_Lo128) 123 DECODE_OPERAND_REG(VRegOrLds_32) 124 DECODE_OPERAND_REG(VS_32) 125 DECODE_OPERAND_REG(VS_64) 126 DECODE_OPERAND_REG(VS_128) 127 128 DECODE_OPERAND_REG(VReg_64) 129 DECODE_OPERAND_REG(VReg_96) 130 DECODE_OPERAND_REG(VReg_128) 131 DECODE_OPERAND_REG(VReg_256) 132 DECODE_OPERAND_REG(VReg_288) 133 DECODE_OPERAND_REG(VReg_352) 134 DECODE_OPERAND_REG(VReg_384) 135 DECODE_OPERAND_REG(VReg_512) 136 DECODE_OPERAND_REG(VReg_1024) 137 138 DECODE_OPERAND_REG(SReg_32) 139 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 140 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 141 DECODE_OPERAND_REG(SRegOrLds_32) 142 DECODE_OPERAND_REG(SReg_64) 143 DECODE_OPERAND_REG(SReg_64_XEXEC) 144 DECODE_OPERAND_REG(SReg_128) 145 DECODE_OPERAND_REG(SReg_256) 146 DECODE_OPERAND_REG(SReg_512) 147 148 DECODE_OPERAND_REG(AGPR_32) 149 DECODE_OPERAND_REG(AReg_64) 150 DECODE_OPERAND_REG(AReg_128) 151 DECODE_OPERAND_REG(AReg_256) 152 DECODE_OPERAND_REG(AReg_512) 153 DECODE_OPERAND_REG(AReg_1024) 154 DECODE_OPERAND_REG(AV_32) 155 DECODE_OPERAND_REG(AV_64) 156 DECODE_OPERAND_REG(AV_128) 157 DECODE_OPERAND_REG(AVDst_128) 158 DECODE_OPERAND_REG(AVDst_512) 159 160 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 161 uint64_t Addr, 162 const MCDisassembler *Decoder) { 163 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 164 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 165 } 166 167 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 168 uint64_t Addr, 169 const MCDisassembler *Decoder) { 170 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 171 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 172 } 173 174 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 175 uint64_t Addr, 176 const MCDisassembler *Decoder) { 177 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 178 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 179 } 180 181 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 182 uint64_t Addr, 183 const MCDisassembler *Decoder) { 184 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 185 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 186 } 187 188 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 189 uint64_t Addr, 190 const MCDisassembler *Decoder) { 191 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 192 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 193 } 194 195 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 196 uint64_t Addr, 197 const MCDisassembler *Decoder) { 198 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 199 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 200 } 201 202 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 203 uint64_t Addr, 204 const MCDisassembler *Decoder) { 205 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 206 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 207 } 208 209 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 210 uint64_t Addr, 211 const MCDisassembler *Decoder) { 212 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 213 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 214 } 215 216 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 217 uint64_t Addr, 218 const MCDisassembler *Decoder) { 219 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 220 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 221 } 222 223 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 224 uint64_t Addr, 225 const MCDisassembler *Decoder) { 226 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 227 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 228 } 229 230 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 231 uint64_t Addr, 232 const MCDisassembler *Decoder) { 233 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 234 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 235 } 236 237 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 238 uint64_t Addr, 239 const MCDisassembler *Decoder) { 240 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 241 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 242 } 243 244 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 245 uint64_t Addr, 246 const MCDisassembler *Decoder) { 247 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 248 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 249 } 250 251 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 252 uint64_t Addr, 253 const MCDisassembler *Decoder) { 254 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 255 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 256 } 257 258 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 259 uint64_t Addr, 260 const MCDisassembler *Decoder) { 261 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 262 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 263 } 264 265 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 266 uint64_t Addr, 267 const MCDisassembler *Decoder) { 268 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 269 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 270 } 271 272 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 273 uint64_t Addr, 274 const MCDisassembler *Decoder) { 275 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 276 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 277 } 278 279 static DecodeStatus 280 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 281 const MCDisassembler *Decoder) { 282 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 283 return addOperand( 284 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 285 } 286 287 static DecodeStatus 288 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 289 const MCDisassembler *Decoder) { 290 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 291 return addOperand( 292 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 293 } 294 295 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 296 uint64_t Addr, const void *Decoder) { 297 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 298 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 299 } 300 301 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 302 const MCRegisterInfo *MRI) { 303 if (OpIdx < 0) 304 return false; 305 306 const MCOperand &Op = Inst.getOperand(OpIdx); 307 if (!Op.isReg()) 308 return false; 309 310 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 311 auto Reg = Sub ? Sub : Op.getReg(); 312 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 313 } 314 315 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 316 AMDGPUDisassembler::OpWidthTy Opw, 317 const MCDisassembler *Decoder) { 318 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 319 if (!DAsm->isGFX90A()) { 320 Imm &= 511; 321 } else { 322 // If atomic has both vdata and vdst their register classes are tied. 323 // The bit is decoded along with the vdst, first operand. We need to 324 // change register class to AGPR if vdst was AGPR. 325 // If a DS instruction has both data0 and data1 their register classes 326 // are also tied. 327 unsigned Opc = Inst.getOpcode(); 328 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 329 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 330 : AMDGPU::OpName::vdata; 331 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 332 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 333 if ((int)Inst.getNumOperands() == DataIdx) { 334 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 335 if (IsAGPROperand(Inst, DstIdx, MRI)) 336 Imm |= 512; 337 } 338 339 if (TSFlags & SIInstrFlags::DS) { 340 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 341 if ((int)Inst.getNumOperands() == Data2Idx && 342 IsAGPROperand(Inst, DataIdx, MRI)) 343 Imm |= 512; 344 } 345 } 346 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 347 } 348 349 static DecodeStatus 350 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 351 const MCDisassembler *Decoder) { 352 return decodeOperand_AVLdSt_Any(Inst, Imm, 353 AMDGPUDisassembler::OPW32, Decoder); 354 } 355 356 static DecodeStatus 357 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 358 const MCDisassembler *Decoder) { 359 return decodeOperand_AVLdSt_Any(Inst, Imm, 360 AMDGPUDisassembler::OPW64, Decoder); 361 } 362 363 static DecodeStatus 364 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 365 const MCDisassembler *Decoder) { 366 return decodeOperand_AVLdSt_Any(Inst, Imm, 367 AMDGPUDisassembler::OPW96, Decoder); 368 } 369 370 static DecodeStatus 371 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 372 const MCDisassembler *Decoder) { 373 return decodeOperand_AVLdSt_Any(Inst, Imm, 374 AMDGPUDisassembler::OPW128, Decoder); 375 } 376 377 static DecodeStatus 378 DecodeAVLdSt_160RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 379 const MCDisassembler *Decoder) { 380 return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW160, 381 Decoder); 382 } 383 384 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 385 uint64_t Addr, 386 const MCDisassembler *Decoder) { 387 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 388 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 389 } 390 391 #define DECODE_SDWA(DecName) \ 392 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 393 394 DECODE_SDWA(Src32) 395 DECODE_SDWA(Src16) 396 DECODE_SDWA(VopcDst) 397 398 #include "AMDGPUGenDisassemblerTables.inc" 399 400 //===----------------------------------------------------------------------===// 401 // 402 //===----------------------------------------------------------------------===// 403 404 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 405 assert(Bytes.size() >= sizeof(T)); 406 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 407 Bytes = Bytes.slice(sizeof(T)); 408 return Res; 409 } 410 411 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 412 assert(Bytes.size() >= 12); 413 uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>( 414 Bytes.data()); 415 Bytes = Bytes.slice(8); 416 uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>( 417 Bytes.data()); 418 Bytes = Bytes.slice(4); 419 return DecoderUInt128(Lo, Hi); 420 } 421 422 // The disassembler is greedy, so we need to check FI operand value to 423 // not parse a dpp if the correct literal is not set. For dpp16 the 424 // autogenerated decoder checks the dpp literal 425 static bool isValidDPP8(const MCInst &MI) { 426 using namespace llvm::AMDGPU::DPP; 427 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 428 assert(FiIdx != -1); 429 if ((unsigned)FiIdx >= MI.getNumOperands()) 430 return false; 431 unsigned Fi = MI.getOperand(FiIdx).getImm(); 432 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 433 } 434 435 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 436 ArrayRef<uint8_t> Bytes_, 437 uint64_t Address, 438 raw_ostream &CS) const { 439 CommentStream = &CS; 440 bool IsSDWA = false; 441 442 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 443 Bytes = Bytes_.slice(0, MaxInstBytesNum); 444 445 DecodeStatus Res = MCDisassembler::Fail; 446 do { 447 // ToDo: better to switch encoding length using some bit predicate 448 // but it is unknown yet, so try all we can 449 450 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 451 // encodings 452 if (isGFX11Plus() && Bytes.size() >= 12 ) { 453 DecoderUInt128 DecW = eat12Bytes(Bytes); 454 Res = tryDecodeInst(DecoderTableDPP8GFX1196, MI, DecW, 455 Address); 456 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 457 break; 458 MI = MCInst(); // clear 459 Res = tryDecodeInst(DecoderTableDPPGFX1196, MI, DecW, 460 Address); 461 if (Res) { 462 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 463 convertVOP3PDPPInst(MI); 464 else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) 465 convertVOPCDPPInst(MI); // Special VOP3 case 466 else { 467 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 468 convertVOP3DPPInst(MI); // Regular VOP3 case 469 } 470 break; 471 } 472 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address); 473 if (Res) 474 break; 475 } 476 // Reinitialize Bytes 477 Bytes = Bytes_.slice(0, MaxInstBytesNum); 478 479 if (Bytes.size() >= 8) { 480 const uint64_t QW = eatBytes<uint64_t>(Bytes); 481 482 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 483 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 484 if (Res) { 485 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 486 == -1) 487 break; 488 if (convertDPP8Inst(MI) == MCDisassembler::Success) 489 break; 490 MI = MCInst(); // clear 491 } 492 } 493 494 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 495 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 496 break; 497 MI = MCInst(); // clear 498 499 Res = tryDecodeInst(DecoderTableDPP8GFX1164, MI, QW, Address); 500 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 501 break; 502 MI = MCInst(); // clear 503 504 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 505 if (Res) break; 506 507 Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address); 508 if (Res) { 509 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 510 convertVOPCDPPInst(MI); 511 break; 512 } 513 514 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 515 if (Res) { IsSDWA = true; break; } 516 517 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 518 if (Res) { IsSDWA = true; break; } 519 520 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 521 if (Res) { IsSDWA = true; break; } 522 523 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 524 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 525 if (Res) 526 break; 527 } 528 529 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 530 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 531 // table first so we print the correct name. 532 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 533 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 534 if (Res) 535 break; 536 } 537 } 538 539 // Reinitialize Bytes as DPP64 could have eaten too much 540 Bytes = Bytes_.slice(0, MaxInstBytesNum); 541 542 // Try decode 32-bit instruction 543 if (Bytes.size() < 4) break; 544 const uint32_t DW = eatBytes<uint32_t>(Bytes); 545 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 546 if (Res) break; 547 548 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 549 if (Res) break; 550 551 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 552 if (Res) break; 553 554 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 555 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 556 if (Res) 557 break; 558 } 559 560 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 561 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 562 if (Res) break; 563 } 564 565 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 566 if (Res) break; 567 568 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address); 569 if (Res) break; 570 571 if (Bytes.size() < 4) break; 572 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 573 574 if (STI.getFeatureBits()[AMDGPU::FeatureGFX940Insts]) { 575 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address); 576 if (Res) 577 break; 578 } 579 580 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 581 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 582 if (Res) 583 break; 584 } 585 586 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 587 if (Res) break; 588 589 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 590 if (Res) break; 591 592 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 593 if (Res) break; 594 595 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 596 if (Res) break; 597 598 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address); 599 if (Res) 600 break; 601 602 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address); 603 } while (false); 604 605 if (Res && AMDGPU::isMAC(MI.getOpcode())) { 606 // Insert dummy unused src2_modifiers. 607 insertNamedMCOperand(MI, MCOperand::createImm(0), 608 AMDGPU::OpName::src2_modifiers); 609 } 610 611 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 612 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 613 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 614 AMDGPU::OpName::cpol); 615 if (CPolPos != -1) { 616 unsigned CPol = 617 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 618 AMDGPU::CPol::GLC : 0; 619 if (MI.getNumOperands() <= (unsigned)CPolPos) { 620 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 621 AMDGPU::OpName::cpol); 622 } else if (CPol) { 623 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 624 } 625 } 626 } 627 628 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 629 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 630 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 631 // GFX90A lost TFE, its place is occupied by ACC. 632 int TFEOpIdx = 633 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 634 if (TFEOpIdx != -1) { 635 auto TFEIter = MI.begin(); 636 std::advance(TFEIter, TFEOpIdx); 637 MI.insert(TFEIter, MCOperand::createImm(0)); 638 } 639 } 640 641 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 642 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 643 int SWZOpIdx = 644 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 645 if (SWZOpIdx != -1) { 646 auto SWZIter = MI.begin(); 647 std::advance(SWZIter, SWZOpIdx); 648 MI.insert(SWZIter, MCOperand::createImm(0)); 649 } 650 } 651 652 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 653 int VAddr0Idx = 654 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 655 int RsrcIdx = 656 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 657 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 658 if (VAddr0Idx >= 0 && NSAArgs > 0) { 659 unsigned NSAWords = (NSAArgs + 3) / 4; 660 if (Bytes.size() < 4 * NSAWords) { 661 Res = MCDisassembler::Fail; 662 } else { 663 for (unsigned i = 0; i < NSAArgs; ++i) { 664 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 665 auto VAddrRCID = 666 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; 667 MI.insert(MI.begin() + VAddrIdx, 668 createRegOperand(VAddrRCID, Bytes[i])); 669 } 670 Bytes = Bytes.slice(4 * NSAWords); 671 } 672 } 673 674 if (Res) 675 Res = convertMIMGInst(MI); 676 } 677 678 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 679 Res = convertEXPInst(MI); 680 681 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 682 Res = convertVINTERPInst(MI); 683 684 if (Res && IsSDWA) 685 Res = convertSDWAInst(MI); 686 687 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 688 AMDGPU::OpName::vdst_in); 689 if (VDstIn_Idx != -1) { 690 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 691 MCOI::OperandConstraint::TIED_TO); 692 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 693 !MI.getOperand(VDstIn_Idx).isReg() || 694 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 695 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 696 MI.erase(&MI.getOperand(VDstIn_Idx)); 697 insertNamedMCOperand(MI, 698 MCOperand::createReg(MI.getOperand(Tied).getReg()), 699 AMDGPU::OpName::vdst_in); 700 } 701 } 702 703 int ImmLitIdx = 704 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 705 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 706 if (Res && ImmLitIdx != -1 && !IsSOPK) 707 Res = convertFMAanyK(MI, ImmLitIdx); 708 709 // if the opcode was not recognized we'll assume a Size of 4 bytes 710 // (unless there are fewer bytes left) 711 Size = Res ? (MaxInstBytesNum - Bytes.size()) 712 : std::min((size_t)4, Bytes_.size()); 713 return Res; 714 } 715 716 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 717 if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) { 718 // The MCInst still has these fields even though they are no longer encoded 719 // in the GFX11 instruction. 720 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 721 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 722 } 723 return MCDisassembler::Success; 724 } 725 726 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 727 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 728 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 729 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 730 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) { 731 // The MCInst has this field that is not directly encoded in the 732 // instruction. 733 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 734 } 735 return MCDisassembler::Success; 736 } 737 738 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 739 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 740 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 741 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 742 // VOPC - insert clamp 743 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 744 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 745 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 746 if (SDst != -1) { 747 // VOPC - insert VCC register as sdst 748 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 749 AMDGPU::OpName::sdst); 750 } else { 751 // VOP1/2 - insert omod if present in instruction 752 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 753 } 754 } 755 return MCDisassembler::Success; 756 } 757 758 struct VOPModifiers { 759 unsigned OpSel = 0; 760 unsigned OpSelHi = 0; 761 unsigned NegLo = 0; 762 unsigned NegHi = 0; 763 }; 764 765 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 766 // Note that these values do not affect disassembler output, 767 // so this is only necessary for consistency with src_modifiers. 768 static VOPModifiers collectVOPModifiers(const MCInst &MI, 769 bool IsVOP3P = false) { 770 VOPModifiers Modifiers; 771 unsigned Opc = MI.getOpcode(); 772 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 773 AMDGPU::OpName::src1_modifiers, 774 AMDGPU::OpName::src2_modifiers}; 775 for (int J = 0; J < 3; ++J) { 776 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 777 if (OpIdx == -1) 778 continue; 779 780 unsigned Val = MI.getOperand(OpIdx).getImm(); 781 782 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 783 if (IsVOP3P) { 784 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 785 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 786 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 787 } else if (J == 0) { 788 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 789 } 790 } 791 792 return Modifiers; 793 } 794 795 // MAC opcodes have special old and src2 operands. 796 // src2 is tied to dst, while old is not tied (but assumed to be). 797 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 798 constexpr int DST_IDX = 0; 799 auto Opcode = MI.getOpcode(); 800 const auto &Desc = MCII->get(Opcode); 801 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 802 803 if (OldIdx != -1 && Desc.getOperandConstraint( 804 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 805 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 806 assert(Desc.getOperandConstraint( 807 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 808 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 809 (void)DST_IDX; 810 return true; 811 } 812 813 return false; 814 } 815 816 // Create dummy old operand and insert dummy unused src2_modifiers 817 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 818 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 819 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 820 insertNamedMCOperand(MI, MCOperand::createImm(0), 821 AMDGPU::OpName::src2_modifiers); 822 } 823 824 // We must check FI == literal to reject not genuine dpp8 insts, and we must 825 // first add optional MI operands to check FI 826 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 827 unsigned Opc = MI.getOpcode(); 828 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 829 convertVOP3PDPPInst(MI); 830 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 831 AMDGPU::isVOPC64DPP(Opc)) { 832 convertVOPCDPPInst(MI); 833 } else { 834 if (isMacDPP(MI)) 835 convertMacDPPInst(MI); 836 837 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 838 if (MI.getNumOperands() < DescNumOps && 839 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 840 auto Mods = collectVOPModifiers(MI); 841 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 842 AMDGPU::OpName::op_sel); 843 } else { 844 // Insert dummy unused src modifiers. 845 if (MI.getNumOperands() < DescNumOps && 846 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 847 insertNamedMCOperand(MI, MCOperand::createImm(0), 848 AMDGPU::OpName::src0_modifiers); 849 850 if (MI.getNumOperands() < DescNumOps && 851 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 852 insertNamedMCOperand(MI, MCOperand::createImm(0), 853 AMDGPU::OpName::src1_modifiers); 854 } 855 } 856 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 857 } 858 859 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 860 if (isMacDPP(MI)) 861 convertMacDPPInst(MI); 862 863 unsigned Opc = MI.getOpcode(); 864 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 865 if (MI.getNumOperands() < DescNumOps && 866 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 867 auto Mods = collectVOPModifiers(MI); 868 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 869 AMDGPU::OpName::op_sel); 870 } 871 return MCDisassembler::Success; 872 } 873 874 // Note that before gfx10, the MIMG encoding provided no information about 875 // VADDR size. Consequently, decoded instructions always show address as if it 876 // has 1 dword, which could be not really so. 877 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 878 879 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 880 AMDGPU::OpName::vdst); 881 882 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 883 AMDGPU::OpName::vdata); 884 int VAddr0Idx = 885 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 886 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 887 AMDGPU::OpName::dmask); 888 889 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 890 AMDGPU::OpName::tfe); 891 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 892 AMDGPU::OpName::d16); 893 894 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 895 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 896 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 897 898 assert(VDataIdx != -1); 899 if (BaseOpcode->BVH) { 900 // Add A16 operand for intersect_ray instructions 901 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::a16)) 902 addOperand(MI, MCOperand::createImm(1)); 903 return MCDisassembler::Success; 904 } 905 906 bool IsAtomic = (VDstIdx != -1); 907 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 908 bool IsNSA = false; 909 unsigned AddrSize = Info->VAddrDwords; 910 911 if (isGFX10Plus()) { 912 unsigned DimIdx = 913 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 914 int A16Idx = 915 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 916 const AMDGPU::MIMGDimInfo *Dim = 917 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 918 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 919 920 AddrSize = 921 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 922 923 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 924 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA; 925 if (!IsNSA) { 926 if (AddrSize > 12) 927 AddrSize = 16; 928 } else { 929 if (AddrSize > Info->VAddrDwords) { 930 // The NSA encoding does not contain enough operands for the combination 931 // of base opcode / dimension. Should this be an error? 932 return MCDisassembler::Success; 933 } 934 } 935 } 936 937 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 938 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); 939 940 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 941 if (D16 && AMDGPU::hasPackedD16(STI)) { 942 DstSize = (DstSize + 1) / 2; 943 } 944 945 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 946 DstSize += 1; 947 948 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 949 return MCDisassembler::Success; 950 951 int NewOpcode = 952 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 953 if (NewOpcode == -1) 954 return MCDisassembler::Success; 955 956 // Widen the register to the correct number of enabled channels. 957 unsigned NewVdata = AMDGPU::NoRegister; 958 if (DstSize != Info->VDataDwords) { 959 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; 960 961 // Get first subregister of VData 962 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 963 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 964 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 965 966 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 967 &MRI.getRegClass(DataRCID)); 968 if (NewVdata == AMDGPU::NoRegister) { 969 // It's possible to encode this such that the low register + enabled 970 // components exceeds the register count. 971 return MCDisassembler::Success; 972 } 973 } 974 975 // If not using NSA on GFX10+, widen address register to correct size. 976 unsigned NewVAddr0 = AMDGPU::NoRegister; 977 if (isGFX10Plus() && !IsNSA && AddrSize != Info->VAddrDwords) { 978 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 979 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 980 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 981 982 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddr0Idx].RegClass; 983 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 984 &MRI.getRegClass(AddrRCID)); 985 if (NewVAddr0 == AMDGPU::NoRegister) 986 return MCDisassembler::Success; 987 } 988 989 MI.setOpcode(NewOpcode); 990 991 if (NewVdata != AMDGPU::NoRegister) { 992 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 993 994 if (IsAtomic) { 995 // Atomic operations have an additional operand (a copy of data) 996 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 997 } 998 } 999 1000 if (NewVAddr0 != AMDGPU::NoRegister) { 1001 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 1002 } else if (IsNSA) { 1003 assert(AddrSize <= Info->VAddrDwords); 1004 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1005 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1006 } 1007 1008 return MCDisassembler::Success; 1009 } 1010 1011 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1012 // decoder only adds to src_modifiers, so manually add the bits to the other 1013 // operands. 1014 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1015 unsigned Opc = MI.getOpcode(); 1016 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1017 auto Mods = collectVOPModifiers(MI, true); 1018 1019 if (MI.getNumOperands() < DescNumOps && 1020 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1021 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1022 1023 if (MI.getNumOperands() < DescNumOps && 1024 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1025 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1026 AMDGPU::OpName::op_sel); 1027 if (MI.getNumOperands() < DescNumOps && 1028 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1029 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1030 AMDGPU::OpName::op_sel_hi); 1031 if (MI.getNumOperands() < DescNumOps && 1032 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1033 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1034 AMDGPU::OpName::neg_lo); 1035 if (MI.getNumOperands() < DescNumOps && 1036 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1037 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1038 AMDGPU::OpName::neg_hi); 1039 1040 return MCDisassembler::Success; 1041 } 1042 1043 // Create dummy old operand and insert optional operands 1044 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1045 unsigned Opc = MI.getOpcode(); 1046 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1047 1048 if (MI.getNumOperands() < DescNumOps && 1049 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1050 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1051 1052 if (MI.getNumOperands() < DescNumOps && 1053 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1054 insertNamedMCOperand(MI, MCOperand::createImm(0), 1055 AMDGPU::OpName::src0_modifiers); 1056 1057 if (MI.getNumOperands() < DescNumOps && 1058 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1059 insertNamedMCOperand(MI, MCOperand::createImm(0), 1060 AMDGPU::OpName::src1_modifiers); 1061 return MCDisassembler::Success; 1062 } 1063 1064 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1065 int ImmLitIdx) const { 1066 assert(HasLiteral && "Should have decoded a literal"); 1067 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1068 unsigned DescNumOps = Desc.getNumOperands(); 1069 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1070 AMDGPU::OpName::immDeferred); 1071 assert(DescNumOps == MI.getNumOperands()); 1072 for (unsigned I = 0; I < DescNumOps; ++I) { 1073 auto &Op = MI.getOperand(I); 1074 auto OpType = Desc.operands()[I].OperandType; 1075 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1076 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1077 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1078 IsDeferredOp) 1079 Op.setImm(Literal); 1080 } 1081 return MCDisassembler::Success; 1082 } 1083 1084 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1085 return getContext().getRegisterInfo()-> 1086 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1087 } 1088 1089 inline 1090 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1091 const Twine& ErrMsg) const { 1092 *CommentStream << "Error: " + ErrMsg; 1093 1094 // ToDo: add support for error operands to MCInst.h 1095 // return MCOperand::createError(V); 1096 return MCOperand(); 1097 } 1098 1099 inline 1100 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1101 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1102 } 1103 1104 inline 1105 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1106 unsigned Val) const { 1107 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1108 if (Val >= RegCl.getNumRegs()) 1109 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1110 ": unknown register " + Twine(Val)); 1111 return createRegOperand(RegCl.getRegister(Val)); 1112 } 1113 1114 inline 1115 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1116 unsigned Val) const { 1117 // ToDo: SI/CI have 104 SGPRs, VI - 102 1118 // Valery: here we accepting as much as we can, let assembler sort it out 1119 int shift = 0; 1120 switch (SRegClassID) { 1121 case AMDGPU::SGPR_32RegClassID: 1122 case AMDGPU::TTMP_32RegClassID: 1123 break; 1124 case AMDGPU::SGPR_64RegClassID: 1125 case AMDGPU::TTMP_64RegClassID: 1126 shift = 1; 1127 break; 1128 case AMDGPU::SGPR_128RegClassID: 1129 case AMDGPU::TTMP_128RegClassID: 1130 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1131 // this bundle? 1132 case AMDGPU::SGPR_256RegClassID: 1133 case AMDGPU::TTMP_256RegClassID: 1134 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1135 // this bundle? 1136 case AMDGPU::SGPR_288RegClassID: 1137 case AMDGPU::TTMP_288RegClassID: 1138 case AMDGPU::SGPR_320RegClassID: 1139 case AMDGPU::TTMP_320RegClassID: 1140 case AMDGPU::SGPR_352RegClassID: 1141 case AMDGPU::TTMP_352RegClassID: 1142 case AMDGPU::SGPR_384RegClassID: 1143 case AMDGPU::TTMP_384RegClassID: 1144 case AMDGPU::SGPR_512RegClassID: 1145 case AMDGPU::TTMP_512RegClassID: 1146 shift = 2; 1147 break; 1148 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1149 // this bundle? 1150 default: 1151 llvm_unreachable("unhandled register class"); 1152 } 1153 1154 if (Val % (1 << shift)) { 1155 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1156 << ": scalar reg isn't aligned " << Val; 1157 } 1158 1159 return createRegOperand(SRegClassID, Val >> shift); 1160 } 1161 1162 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 1163 return decodeSrcOp(OPW32, Val); 1164 } 1165 1166 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 1167 return decodeSrcOp(OPW64, Val); 1168 } 1169 1170 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 1171 return decodeSrcOp(OPW128, Val); 1172 } 1173 1174 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 1175 return decodeSrcOp(OPW16, Val); 1176 } 1177 1178 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 1179 return decodeSrcOp(OPWV216, Val); 1180 } 1181 1182 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 1183 return decodeSrcOp(OPWV232, Val); 1184 } 1185 1186 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32_Lo128(unsigned Val) const { 1187 return createRegOperand(AMDGPU::VGPR_32_Lo128RegClassID, Val); 1188 } 1189 1190 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 1191 // Some instructions have operand restrictions beyond what the encoding 1192 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 1193 // high bit. 1194 Val &= 255; 1195 1196 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 1197 } 1198 1199 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 1200 return decodeSrcOp(OPW32, Val); 1201 } 1202 1203 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 1204 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 1205 } 1206 1207 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 1208 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 1209 } 1210 1211 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 1212 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 1213 } 1214 1215 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 1216 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 1217 } 1218 1219 MCOperand AMDGPUDisassembler::decodeOperand_AReg_288(unsigned Val) const { 1220 return createRegOperand(AMDGPU::AReg_288RegClassID, Val & 255); 1221 } 1222 1223 MCOperand AMDGPUDisassembler::decodeOperand_AReg_320(unsigned Val) const { 1224 return createRegOperand(AMDGPU::AReg_320RegClassID, Val & 255); 1225 } 1226 1227 MCOperand AMDGPUDisassembler::decodeOperand_AReg_352(unsigned Val) const { 1228 return createRegOperand(AMDGPU::AReg_352RegClassID, Val & 255); 1229 } 1230 1231 MCOperand AMDGPUDisassembler::decodeOperand_AReg_384(unsigned Val) const { 1232 return createRegOperand(AMDGPU::AReg_384RegClassID, Val & 255); 1233 } 1234 1235 1236 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 1237 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 1238 } 1239 1240 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 1241 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 1242 } 1243 1244 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 1245 return decodeSrcOp(OPW32, Val); 1246 } 1247 1248 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 1249 return decodeSrcOp(OPW64, Val); 1250 } 1251 1252 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 1253 return decodeSrcOp(OPW128, Val); 1254 } 1255 1256 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { 1257 using namespace AMDGPU::EncValues; 1258 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1259 return decodeSrcOp(OPW128, Val | IS_VGPR); 1260 } 1261 1262 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { 1263 using namespace AMDGPU::EncValues; 1264 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1265 return decodeSrcOp(OPW512, Val | IS_VGPR); 1266 } 1267 1268 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1269 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1270 } 1271 1272 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1273 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1274 } 1275 1276 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1277 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1278 } 1279 1280 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1281 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1282 } 1283 1284 MCOperand AMDGPUDisassembler::decodeOperand_VReg_288(unsigned Val) const { 1285 return createRegOperand(AMDGPU::VReg_288RegClassID, Val); 1286 } 1287 1288 MCOperand AMDGPUDisassembler::decodeOperand_VReg_320(unsigned Val) const { 1289 return createRegOperand(AMDGPU::VReg_320RegClassID, Val); 1290 } 1291 1292 MCOperand AMDGPUDisassembler::decodeOperand_VReg_352(unsigned Val) const { 1293 return createRegOperand(AMDGPU::VReg_352RegClassID, Val); 1294 } 1295 1296 MCOperand AMDGPUDisassembler::decodeOperand_VReg_384(unsigned Val) const { 1297 return createRegOperand(AMDGPU::VReg_384RegClassID, Val); 1298 } 1299 1300 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1301 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1302 } 1303 1304 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1305 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1306 } 1307 1308 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1309 // table-gen generated disassembler doesn't care about operand types 1310 // leaving only registry class so SSrc_32 operand turns into SReg_32 1311 // and therefore we accept immediates and literals here as well 1312 return decodeSrcOp(OPW32, Val); 1313 } 1314 1315 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1316 unsigned Val) const { 1317 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1318 return decodeOperand_SReg_32(Val); 1319 } 1320 1321 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1322 unsigned Val) const { 1323 // SReg_32_XM0 is SReg_32 without EXEC_HI 1324 return decodeOperand_SReg_32(Val); 1325 } 1326 1327 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1328 // table-gen generated disassembler doesn't care about operand types 1329 // leaving only registry class so SSrc_32 operand turns into SReg_32 1330 // and therefore we accept immediates and literals here as well 1331 return decodeSrcOp(OPW32, Val); 1332 } 1333 1334 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1335 return decodeSrcOp(OPW64, Val); 1336 } 1337 1338 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1339 return decodeSrcOp(OPW64, Val); 1340 } 1341 1342 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1343 return decodeSrcOp(OPW128, Val); 1344 } 1345 1346 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1347 return decodeDstOp(OPW256, Val); 1348 } 1349 1350 MCOperand AMDGPUDisassembler::decodeOperand_SReg_288(unsigned Val) const { 1351 return decodeDstOp(OPW288, Val); 1352 } 1353 1354 MCOperand AMDGPUDisassembler::decodeOperand_SReg_320(unsigned Val) const { 1355 return decodeDstOp(OPW320, Val); 1356 } 1357 1358 MCOperand AMDGPUDisassembler::decodeOperand_SReg_352(unsigned Val) const { 1359 return decodeDstOp(OPW352, Val); 1360 } 1361 1362 MCOperand AMDGPUDisassembler::decodeOperand_SReg_384(unsigned Val) const { 1363 return decodeDstOp(OPW384, Val); 1364 } 1365 1366 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1367 return decodeDstOp(OPW512, Val); 1368 } 1369 1370 // Decode Literals for insts which always have a literal in the encoding 1371 MCOperand 1372 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1373 if (HasLiteral) { 1374 assert( 1375 AMDGPU::hasVOPD(STI) && 1376 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1377 if (Literal != Val) 1378 return errOperand(Val, "More than one unique literal is illegal"); 1379 } 1380 HasLiteral = true; 1381 Literal = Val; 1382 return MCOperand::createImm(Literal); 1383 } 1384 1385 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1386 // For now all literal constants are supposed to be unsigned integer 1387 // ToDo: deal with signed/unsigned 64-bit integer constants 1388 // ToDo: deal with float/double constants 1389 if (!HasLiteral) { 1390 if (Bytes.size() < 4) { 1391 return errOperand(0, "cannot read literal, inst bytes left " + 1392 Twine(Bytes.size())); 1393 } 1394 HasLiteral = true; 1395 Literal = eatBytes<uint32_t>(Bytes); 1396 } 1397 return MCOperand::createImm(Literal); 1398 } 1399 1400 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1401 using namespace AMDGPU::EncValues; 1402 1403 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1404 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1405 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1406 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1407 // Cast prevents negative overflow. 1408 } 1409 1410 static int64_t getInlineImmVal32(unsigned Imm) { 1411 switch (Imm) { 1412 case 240: 1413 return FloatToBits(0.5f); 1414 case 241: 1415 return FloatToBits(-0.5f); 1416 case 242: 1417 return FloatToBits(1.0f); 1418 case 243: 1419 return FloatToBits(-1.0f); 1420 case 244: 1421 return FloatToBits(2.0f); 1422 case 245: 1423 return FloatToBits(-2.0f); 1424 case 246: 1425 return FloatToBits(4.0f); 1426 case 247: 1427 return FloatToBits(-4.0f); 1428 case 248: // 1 / (2 * PI) 1429 return 0x3e22f983; 1430 default: 1431 llvm_unreachable("invalid fp inline imm"); 1432 } 1433 } 1434 1435 static int64_t getInlineImmVal64(unsigned Imm) { 1436 switch (Imm) { 1437 case 240: 1438 return DoubleToBits(0.5); 1439 case 241: 1440 return DoubleToBits(-0.5); 1441 case 242: 1442 return DoubleToBits(1.0); 1443 case 243: 1444 return DoubleToBits(-1.0); 1445 case 244: 1446 return DoubleToBits(2.0); 1447 case 245: 1448 return DoubleToBits(-2.0); 1449 case 246: 1450 return DoubleToBits(4.0); 1451 case 247: 1452 return DoubleToBits(-4.0); 1453 case 248: // 1 / (2 * PI) 1454 return 0x3fc45f306dc9c882; 1455 default: 1456 llvm_unreachable("invalid fp inline imm"); 1457 } 1458 } 1459 1460 static int64_t getInlineImmVal16(unsigned Imm) { 1461 switch (Imm) { 1462 case 240: 1463 return 0x3800; 1464 case 241: 1465 return 0xB800; 1466 case 242: 1467 return 0x3C00; 1468 case 243: 1469 return 0xBC00; 1470 case 244: 1471 return 0x4000; 1472 case 245: 1473 return 0xC000; 1474 case 246: 1475 return 0x4400; 1476 case 247: 1477 return 0xC400; 1478 case 248: // 1 / (2 * PI) 1479 return 0x3118; 1480 default: 1481 llvm_unreachable("invalid fp inline imm"); 1482 } 1483 } 1484 1485 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1486 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1487 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1488 1489 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1490 switch (Width) { 1491 case OPW32: 1492 case OPW128: // splat constants 1493 case OPW512: 1494 case OPW1024: 1495 case OPWV232: 1496 return MCOperand::createImm(getInlineImmVal32(Imm)); 1497 case OPW64: 1498 case OPW256: 1499 return MCOperand::createImm(getInlineImmVal64(Imm)); 1500 case OPW16: 1501 case OPWV216: 1502 return MCOperand::createImm(getInlineImmVal16(Imm)); 1503 default: 1504 llvm_unreachable("implement me"); 1505 } 1506 } 1507 1508 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1509 using namespace AMDGPU; 1510 1511 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1512 switch (Width) { 1513 default: // fall 1514 case OPW32: 1515 case OPW16: 1516 case OPWV216: 1517 return VGPR_32RegClassID; 1518 case OPW64: 1519 case OPWV232: return VReg_64RegClassID; 1520 case OPW96: return VReg_96RegClassID; 1521 case OPW128: return VReg_128RegClassID; 1522 case OPW160: return VReg_160RegClassID; 1523 case OPW256: return VReg_256RegClassID; 1524 case OPW288: return VReg_288RegClassID; 1525 case OPW320: return VReg_320RegClassID; 1526 case OPW352: return VReg_352RegClassID; 1527 case OPW384: return VReg_384RegClassID; 1528 case OPW512: return VReg_512RegClassID; 1529 case OPW1024: return VReg_1024RegClassID; 1530 } 1531 } 1532 1533 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1534 using namespace AMDGPU; 1535 1536 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1537 switch (Width) { 1538 default: // fall 1539 case OPW32: 1540 case OPW16: 1541 case OPWV216: 1542 return AGPR_32RegClassID; 1543 case OPW64: 1544 case OPWV232: return AReg_64RegClassID; 1545 case OPW96: return AReg_96RegClassID; 1546 case OPW128: return AReg_128RegClassID; 1547 case OPW160: return AReg_160RegClassID; 1548 case OPW256: return AReg_256RegClassID; 1549 case OPW288: return AReg_288RegClassID; 1550 case OPW320: return AReg_320RegClassID; 1551 case OPW352: return AReg_352RegClassID; 1552 case OPW384: return AReg_384RegClassID; 1553 case OPW512: return AReg_512RegClassID; 1554 case OPW1024: return AReg_1024RegClassID; 1555 } 1556 } 1557 1558 1559 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1560 using namespace AMDGPU; 1561 1562 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1563 switch (Width) { 1564 default: // fall 1565 case OPW32: 1566 case OPW16: 1567 case OPWV216: 1568 return SGPR_32RegClassID; 1569 case OPW64: 1570 case OPWV232: return SGPR_64RegClassID; 1571 case OPW96: return SGPR_96RegClassID; 1572 case OPW128: return SGPR_128RegClassID; 1573 case OPW160: return SGPR_160RegClassID; 1574 case OPW256: return SGPR_256RegClassID; 1575 case OPW288: return SGPR_288RegClassID; 1576 case OPW320: return SGPR_320RegClassID; 1577 case OPW352: return SGPR_352RegClassID; 1578 case OPW384: return SGPR_384RegClassID; 1579 case OPW512: return SGPR_512RegClassID; 1580 } 1581 } 1582 1583 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1584 using namespace AMDGPU; 1585 1586 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1587 switch (Width) { 1588 default: // fall 1589 case OPW32: 1590 case OPW16: 1591 case OPWV216: 1592 return TTMP_32RegClassID; 1593 case OPW64: 1594 case OPWV232: return TTMP_64RegClassID; 1595 case OPW128: return TTMP_128RegClassID; 1596 case OPW256: return TTMP_256RegClassID; 1597 case OPW288: return TTMP_288RegClassID; 1598 case OPW320: return TTMP_320RegClassID; 1599 case OPW352: return TTMP_352RegClassID; 1600 case OPW384: return TTMP_384RegClassID; 1601 case OPW512: return TTMP_512RegClassID; 1602 } 1603 } 1604 1605 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1606 using namespace AMDGPU::EncValues; 1607 1608 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1609 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1610 1611 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1612 } 1613 1614 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1615 bool MandatoryLiteral) const { 1616 using namespace AMDGPU::EncValues; 1617 1618 assert(Val < 1024); // enum10 1619 1620 bool IsAGPR = Val & 512; 1621 Val &= 511; 1622 1623 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1624 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1625 : getVgprClassId(Width), Val - VGPR_MIN); 1626 } 1627 if (Val <= SGPR_MAX) { 1628 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1629 static_assert(SGPR_MIN == 0); 1630 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1631 } 1632 1633 int TTmpIdx = getTTmpIdx(Val); 1634 if (TTmpIdx >= 0) { 1635 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1636 } 1637 1638 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1639 return decodeIntImmed(Val); 1640 1641 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1642 return decodeFPImmed(Width, Val); 1643 1644 if (Val == LITERAL_CONST) { 1645 if (MandatoryLiteral) 1646 // Keep a sentinel value for deferred setting 1647 return MCOperand::createImm(LITERAL_CONST); 1648 else 1649 return decodeLiteralConstant(); 1650 } 1651 1652 switch (Width) { 1653 case OPW32: 1654 case OPW16: 1655 case OPWV216: 1656 return decodeSpecialReg32(Val); 1657 case OPW64: 1658 case OPWV232: 1659 return decodeSpecialReg64(Val); 1660 default: 1661 llvm_unreachable("unexpected immediate type"); 1662 } 1663 } 1664 1665 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1666 using namespace AMDGPU::EncValues; 1667 1668 assert(Val < 128); 1669 assert(Width == OPW256 || Width == OPW512); 1670 1671 if (Val <= SGPR_MAX) { 1672 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1673 static_assert(SGPR_MIN == 0); 1674 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1675 } 1676 1677 int TTmpIdx = getTTmpIdx(Val); 1678 if (TTmpIdx >= 0) { 1679 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1680 } 1681 1682 llvm_unreachable("unknown dst register"); 1683 } 1684 1685 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1686 // opposite of bit 0 of DstX. 1687 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1688 unsigned Val) const { 1689 int VDstXInd = 1690 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1691 assert(VDstXInd != -1); 1692 assert(Inst.getOperand(VDstXInd).isReg()); 1693 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1694 Val |= ~XDstReg & 1; 1695 auto Width = llvm::AMDGPUDisassembler::OPW32; 1696 return createRegOperand(getVgprClassId(Width), Val); 1697 } 1698 1699 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1700 using namespace AMDGPU; 1701 1702 switch (Val) { 1703 // clang-format off 1704 case 102: return createRegOperand(FLAT_SCR_LO); 1705 case 103: return createRegOperand(FLAT_SCR_HI); 1706 case 104: return createRegOperand(XNACK_MASK_LO); 1707 case 105: return createRegOperand(XNACK_MASK_HI); 1708 case 106: return createRegOperand(VCC_LO); 1709 case 107: return createRegOperand(VCC_HI); 1710 case 108: return createRegOperand(TBA_LO); 1711 case 109: return createRegOperand(TBA_HI); 1712 case 110: return createRegOperand(TMA_LO); 1713 case 111: return createRegOperand(TMA_HI); 1714 case 124: 1715 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1716 case 125: 1717 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1718 case 126: return createRegOperand(EXEC_LO); 1719 case 127: return createRegOperand(EXEC_HI); 1720 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1721 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1722 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1723 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1724 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1725 case 251: return createRegOperand(SRC_VCCZ); 1726 case 252: return createRegOperand(SRC_EXECZ); 1727 case 253: return createRegOperand(SRC_SCC); 1728 case 254: return createRegOperand(LDS_DIRECT); 1729 default: break; 1730 // clang-format on 1731 } 1732 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1733 } 1734 1735 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1736 using namespace AMDGPU; 1737 1738 switch (Val) { 1739 case 102: return createRegOperand(FLAT_SCR); 1740 case 104: return createRegOperand(XNACK_MASK); 1741 case 106: return createRegOperand(VCC); 1742 case 108: return createRegOperand(TBA); 1743 case 110: return createRegOperand(TMA); 1744 case 124: 1745 if (isGFX11Plus()) 1746 return createRegOperand(SGPR_NULL); 1747 break; 1748 case 125: 1749 if (!isGFX11Plus()) 1750 return createRegOperand(SGPR_NULL); 1751 break; 1752 case 126: return createRegOperand(EXEC); 1753 case 235: return createRegOperand(SRC_SHARED_BASE); 1754 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1755 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1756 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1757 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1758 case 251: return createRegOperand(SRC_VCCZ); 1759 case 252: return createRegOperand(SRC_EXECZ); 1760 case 253: return createRegOperand(SRC_SCC); 1761 default: break; 1762 } 1763 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1764 } 1765 1766 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1767 const unsigned Val) const { 1768 using namespace AMDGPU::SDWA; 1769 using namespace AMDGPU::EncValues; 1770 1771 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1772 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1773 // XXX: cast to int is needed to avoid stupid warning: 1774 // compare with unsigned is always true 1775 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1776 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1777 return createRegOperand(getVgprClassId(Width), 1778 Val - SDWA9EncValues::SRC_VGPR_MIN); 1779 } 1780 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1781 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1782 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1783 return createSRegOperand(getSgprClassId(Width), 1784 Val - SDWA9EncValues::SRC_SGPR_MIN); 1785 } 1786 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1787 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1788 return createSRegOperand(getTtmpClassId(Width), 1789 Val - SDWA9EncValues::SRC_TTMP_MIN); 1790 } 1791 1792 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1793 1794 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1795 return decodeIntImmed(SVal); 1796 1797 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1798 return decodeFPImmed(Width, SVal); 1799 1800 return decodeSpecialReg32(SVal); 1801 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1802 return createRegOperand(getVgprClassId(Width), Val); 1803 } 1804 llvm_unreachable("unsupported target"); 1805 } 1806 1807 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1808 return decodeSDWASrc(OPW16, Val); 1809 } 1810 1811 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1812 return decodeSDWASrc(OPW32, Val); 1813 } 1814 1815 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1816 using namespace AMDGPU::SDWA; 1817 1818 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1819 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1820 "SDWAVopcDst should be present only on GFX9+"); 1821 1822 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1823 1824 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1825 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1826 1827 int TTmpIdx = getTTmpIdx(Val); 1828 if (TTmpIdx >= 0) { 1829 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1830 return createSRegOperand(TTmpClsId, TTmpIdx); 1831 } else if (Val > SGPR_MAX) { 1832 return IsWave64 ? decodeSpecialReg64(Val) 1833 : decodeSpecialReg32(Val); 1834 } else { 1835 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1836 } 1837 } else { 1838 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1839 } 1840 } 1841 1842 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1843 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1844 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1845 } 1846 1847 bool AMDGPUDisassembler::isVI() const { 1848 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1849 } 1850 1851 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1852 1853 bool AMDGPUDisassembler::isGFX90A() const { 1854 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1855 } 1856 1857 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1858 1859 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1860 1861 bool AMDGPUDisassembler::isGFX10Plus() const { 1862 return AMDGPU::isGFX10Plus(STI); 1863 } 1864 1865 bool AMDGPUDisassembler::isGFX11() const { 1866 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; 1867 } 1868 1869 bool AMDGPUDisassembler::isGFX11Plus() const { 1870 return AMDGPU::isGFX11Plus(STI); 1871 } 1872 1873 1874 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1875 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1876 } 1877 1878 //===----------------------------------------------------------------------===// 1879 // AMDGPU specific symbol handling 1880 //===----------------------------------------------------------------------===// 1881 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1882 do { \ 1883 KdStream << Indent << DIRECTIVE " " \ 1884 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1885 } while (0) 1886 1887 // NOLINTNEXTLINE(readability-identifier-naming) 1888 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1889 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1890 using namespace amdhsa; 1891 StringRef Indent = "\t"; 1892 1893 // We cannot accurately backward compute #VGPRs used from 1894 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1895 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1896 // simply calculate the inverse of what the assembler does. 1897 1898 uint32_t GranulatedWorkitemVGPRCount = 1899 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1900 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1901 1902 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1903 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1904 1905 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1906 1907 // We cannot backward compute values used to calculate 1908 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1909 // directives can't be computed: 1910 // .amdhsa_reserve_vcc 1911 // .amdhsa_reserve_flat_scratch 1912 // .amdhsa_reserve_xnack_mask 1913 // They take their respective default values if not specified in the assembly. 1914 // 1915 // GRANULATED_WAVEFRONT_SGPR_COUNT 1916 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1917 // 1918 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1919 // are set to 0. So while disassembling we consider that: 1920 // 1921 // GRANULATED_WAVEFRONT_SGPR_COUNT 1922 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1923 // 1924 // The disassembler cannot recover the original values of those 3 directives. 1925 1926 uint32_t GranulatedWavefrontSGPRCount = 1927 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1928 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1929 1930 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1931 return MCDisassembler::Fail; 1932 1933 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1934 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1935 1936 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1937 if (!hasArchitectedFlatScratch()) 1938 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1939 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1940 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1941 1942 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1943 return MCDisassembler::Fail; 1944 1945 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1946 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1947 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1948 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1949 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1950 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1951 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1952 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1953 1954 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1955 return MCDisassembler::Fail; 1956 1957 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1958 1959 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1960 return MCDisassembler::Fail; 1961 1962 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1963 1964 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1965 return MCDisassembler::Fail; 1966 1967 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1968 return MCDisassembler::Fail; 1969 1970 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1971 1972 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1973 return MCDisassembler::Fail; 1974 1975 if (isGFX10Plus()) { 1976 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1977 COMPUTE_PGM_RSRC1_WGP_MODE); 1978 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1979 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1980 } 1981 return MCDisassembler::Success; 1982 } 1983 1984 // NOLINTNEXTLINE(readability-identifier-naming) 1985 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1986 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1987 using namespace amdhsa; 1988 StringRef Indent = "\t"; 1989 if (hasArchitectedFlatScratch()) 1990 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1991 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1992 else 1993 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1994 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1995 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1996 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1997 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1998 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1999 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 2000 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 2001 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 2002 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 2003 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 2004 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 2005 2006 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 2007 return MCDisassembler::Fail; 2008 2009 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 2010 return MCDisassembler::Fail; 2011 2012 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 2013 return MCDisassembler::Fail; 2014 2015 PRINT_DIRECTIVE( 2016 ".amdhsa_exception_fp_ieee_invalid_op", 2017 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 2018 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 2019 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 2020 PRINT_DIRECTIVE( 2021 ".amdhsa_exception_fp_ieee_div_zero", 2022 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 2023 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 2024 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 2025 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 2026 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 2027 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 2028 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 2029 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 2030 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 2031 2032 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 2033 return MCDisassembler::Fail; 2034 2035 return MCDisassembler::Success; 2036 } 2037 2038 #undef PRINT_DIRECTIVE 2039 2040 MCDisassembler::DecodeStatus 2041 AMDGPUDisassembler::decodeKernelDescriptorDirective( 2042 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 2043 raw_string_ostream &KdStream) const { 2044 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 2045 do { \ 2046 KdStream << Indent << DIRECTIVE " " \ 2047 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 2048 } while (0) 2049 2050 uint16_t TwoByteBuffer = 0; 2051 uint32_t FourByteBuffer = 0; 2052 2053 StringRef ReservedBytes; 2054 StringRef Indent = "\t"; 2055 2056 assert(Bytes.size() == 64); 2057 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 2058 2059 switch (Cursor.tell()) { 2060 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 2061 FourByteBuffer = DE.getU32(Cursor); 2062 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 2063 << '\n'; 2064 return MCDisassembler::Success; 2065 2066 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 2067 FourByteBuffer = DE.getU32(Cursor); 2068 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 2069 << FourByteBuffer << '\n'; 2070 return MCDisassembler::Success; 2071 2072 case amdhsa::KERNARG_SIZE_OFFSET: 2073 FourByteBuffer = DE.getU32(Cursor); 2074 KdStream << Indent << ".amdhsa_kernarg_size " 2075 << FourByteBuffer << '\n'; 2076 return MCDisassembler::Success; 2077 2078 case amdhsa::RESERVED0_OFFSET: 2079 // 4 reserved bytes, must be 0. 2080 ReservedBytes = DE.getBytes(Cursor, 4); 2081 for (int I = 0; I < 4; ++I) { 2082 if (ReservedBytes[I] != 0) { 2083 return MCDisassembler::Fail; 2084 } 2085 } 2086 return MCDisassembler::Success; 2087 2088 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 2089 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2090 // So far no directive controls this for Code Object V3, so simply skip for 2091 // disassembly. 2092 DE.skip(Cursor, 8); 2093 return MCDisassembler::Success; 2094 2095 case amdhsa::RESERVED1_OFFSET: 2096 // 20 reserved bytes, must be 0. 2097 ReservedBytes = DE.getBytes(Cursor, 20); 2098 for (int I = 0; I < 20; ++I) { 2099 if (ReservedBytes[I] != 0) { 2100 return MCDisassembler::Fail; 2101 } 2102 } 2103 return MCDisassembler::Success; 2104 2105 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2106 // COMPUTE_PGM_RSRC3 2107 // - Only set for GFX10, GFX6-9 have this to be 0. 2108 // - Currently no directives directly control this. 2109 FourByteBuffer = DE.getU32(Cursor); 2110 if (!isGFX10Plus() && FourByteBuffer) { 2111 return MCDisassembler::Fail; 2112 } 2113 return MCDisassembler::Success; 2114 2115 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2116 FourByteBuffer = DE.getU32(Cursor); 2117 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 2118 MCDisassembler::Fail) { 2119 return MCDisassembler::Fail; 2120 } 2121 return MCDisassembler::Success; 2122 2123 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2124 FourByteBuffer = DE.getU32(Cursor); 2125 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 2126 MCDisassembler::Fail) { 2127 return MCDisassembler::Fail; 2128 } 2129 return MCDisassembler::Success; 2130 2131 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2132 using namespace amdhsa; 2133 TwoByteBuffer = DE.getU16(Cursor); 2134 2135 if (!hasArchitectedFlatScratch()) 2136 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2137 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2138 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2139 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2140 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2141 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2142 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2143 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2144 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2145 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2146 if (!hasArchitectedFlatScratch()) 2147 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2148 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2149 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2150 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2151 2152 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2153 return MCDisassembler::Fail; 2154 2155 // Reserved for GFX9 2156 if (isGFX9() && 2157 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2158 return MCDisassembler::Fail; 2159 } else if (isGFX10Plus()) { 2160 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2161 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2162 } 2163 2164 if (AMDGPU::getAmdhsaCodeObjectVersion() >= 5) 2165 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2166 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2167 2168 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2169 return MCDisassembler::Fail; 2170 2171 return MCDisassembler::Success; 2172 2173 case amdhsa::RESERVED2_OFFSET: 2174 // 6 bytes from here are reserved, must be 0. 2175 ReservedBytes = DE.getBytes(Cursor, 6); 2176 for (int I = 0; I < 6; ++I) { 2177 if (ReservedBytes[I] != 0) 2178 return MCDisassembler::Fail; 2179 } 2180 return MCDisassembler::Success; 2181 2182 default: 2183 llvm_unreachable("Unhandled index. Case statements cover everything."); 2184 return MCDisassembler::Fail; 2185 } 2186 #undef PRINT_DIRECTIVE 2187 } 2188 2189 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2190 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2191 // CP microcode requires the kernel descriptor to be 64 aligned. 2192 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2193 return MCDisassembler::Fail; 2194 2195 std::string Kd; 2196 raw_string_ostream KdStream(Kd); 2197 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2198 2199 DataExtractor::Cursor C(0); 2200 while (C && C.tell() < Bytes.size()) { 2201 MCDisassembler::DecodeStatus Status = 2202 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2203 2204 cantFail(C.takeError()); 2205 2206 if (Status == MCDisassembler::Fail) 2207 return MCDisassembler::Fail; 2208 } 2209 KdStream << ".end_amdhsa_kernel\n"; 2210 outs() << KdStream.str(); 2211 return MCDisassembler::Success; 2212 } 2213 2214 std::optional<MCDisassembler::DecodeStatus> 2215 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2216 ArrayRef<uint8_t> Bytes, uint64_t Address, 2217 raw_ostream &CStream) const { 2218 // Right now only kernel descriptor needs to be handled. 2219 // We ignore all other symbols for target specific handling. 2220 // TODO: 2221 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2222 // Object V2 and V3 when symbols are marked protected. 2223 2224 // amd_kernel_code_t for Code Object V2. 2225 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2226 Size = 256; 2227 return MCDisassembler::Fail; 2228 } 2229 2230 // Code Object V3 kernel descriptors. 2231 StringRef Name = Symbol.Name; 2232 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 2233 Size = 64; // Size = 64 regardless of success or failure. 2234 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2235 } 2236 return std::nullopt; 2237 } 2238 2239 //===----------------------------------------------------------------------===// 2240 // AMDGPUSymbolizer 2241 //===----------------------------------------------------------------------===// 2242 2243 // Try to find symbol name for specified label 2244 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2245 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2246 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2247 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2248 2249 if (!IsBranch) { 2250 return false; 2251 } 2252 2253 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2254 if (!Symbols) 2255 return false; 2256 2257 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2258 return Val.Addr == static_cast<uint64_t>(Value) && 2259 Val.Type == ELF::STT_NOTYPE; 2260 }); 2261 if (Result != Symbols->end()) { 2262 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2263 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2264 Inst.addOperand(MCOperand::createExpr(Add)); 2265 return true; 2266 } 2267 // Add to list of referenced addresses, so caller can synthesize a label. 2268 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2269 return false; 2270 } 2271 2272 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2273 int64_t Value, 2274 uint64_t Address) { 2275 llvm_unreachable("unimplemented"); 2276 } 2277 2278 //===----------------------------------------------------------------------===// 2279 // Initialization 2280 //===----------------------------------------------------------------------===// 2281 2282 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2283 LLVMOpInfoCallback /*GetOpInfo*/, 2284 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2285 void *DisInfo, 2286 MCContext *Ctx, 2287 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2288 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2289 } 2290 2291 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2292 const MCSubtargetInfo &STI, 2293 MCContext &Ctx) { 2294 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2295 } 2296 2297 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2298 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2299 createAMDGPUDisassembler); 2300 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2301 createAMDGPUSymbolizer); 2302 } 2303