xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (revision 6966ac055c3b7a39266fb982493330df7a097997) 
1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //===----------------------------------------------------------------------===//
10 //
11 /// \file
12 ///
13 /// This file contains definition for AMDGPU ISA disassembler
14 //
15 //===----------------------------------------------------------------------===//
16 
17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
18 
19 #include "Disassembler/AMDGPUDisassembler.h"
20 #include "AMDGPU.h"
21 #include "AMDGPURegisterInfo.h"
22 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
23 #include "SIDefines.h"
24 #include "TargetInfo/AMDGPUTargetInfo.h"
25 #include "Utils/AMDGPUBaseInfo.h"
26 #include "llvm-c/Disassembler.h"
27 #include "llvm/ADT/APInt.h"
28 #include "llvm/ADT/ArrayRef.h"
29 #include "llvm/ADT/Twine.h"
30 #include "llvm/BinaryFormat/ELF.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCContext.h"
33 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
34 #include "llvm/MC/MCExpr.h"
35 #include "llvm/MC/MCFixedLenDisassembler.h"
36 #include "llvm/MC/MCInst.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/Support/Endian.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include <algorithm>
44 #include <cassert>
45 #include <cstddef>
46 #include <cstdint>
47 #include <iterator>
48 #include <tuple>
49 #include <vector>
50 
51 using namespace llvm;
52 
53 #define DEBUG_TYPE "amdgpu-disassembler"
54 
55 #define SGPR_MAX (isGFX10() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
56                             : AMDGPU::EncValues::SGPR_MAX_SI)
57 
58 using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
59 
60 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
61                                        MCContext &Ctx,
62                                        MCInstrInfo const *MCII) :
63   MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
64   TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
65 
66   // ToDo: AMDGPUDisassembler supports only VI ISA.
67   if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10())
68     report_fatal_error("Disassembly not yet supported for subtarget");
69 }
70 
71 inline static MCDisassembler::DecodeStatus
72 addOperand(MCInst &Inst, const MCOperand& Opnd) {
73   Inst.addOperand(Opnd);
74   return Opnd.isValid() ?
75     MCDisassembler::Success :
76     MCDisassembler::SoftFail;
77 }
78 
79 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
80                                 uint16_t NameIdx) {
81   int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
82   if (OpIdx != -1) {
83     auto I = MI.begin();
84     std::advance(I, OpIdx);
85     MI.insert(I, Op);
86   }
87   return OpIdx;
88 }
89 
90 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
91                                        uint64_t Addr, const void *Decoder) {
92   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
93 
94   // Our branches take a simm16, but we need two extra bits to account for the
95   // factor of 4.
96   APInt SignedOffset(18, Imm * 4, true);
97   int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
98 
99   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
100     return MCDisassembler::Success;
101   return addOperand(Inst, MCOperand::createImm(Imm));
102 }
103 
104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val,
105                                   uint64_t Addr, const void *Decoder) {
106   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
107   return addOperand(Inst, DAsm->decodeBoolReg(Val));
108 }
109 
110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
111 static DecodeStatus StaticDecoderName(MCInst &Inst, \
112                                        unsigned Imm, \
113                                        uint64_t /*Addr*/, \
114                                        const void *Decoder) { \
115   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
116   return addOperand(Inst, DAsm->DecoderName(Imm)); \
117 }
118 
119 #define DECODE_OPERAND_REG(RegClass) \
120 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
121 
122 DECODE_OPERAND_REG(VGPR_32)
123 DECODE_OPERAND_REG(VRegOrLds_32)
124 DECODE_OPERAND_REG(VS_32)
125 DECODE_OPERAND_REG(VS_64)
126 DECODE_OPERAND_REG(VS_128)
127 
128 DECODE_OPERAND_REG(VReg_64)
129 DECODE_OPERAND_REG(VReg_96)
130 DECODE_OPERAND_REG(VReg_128)
131 
132 DECODE_OPERAND_REG(SReg_32)
133 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
134 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
135 DECODE_OPERAND_REG(SRegOrLds_32)
136 DECODE_OPERAND_REG(SReg_64)
137 DECODE_OPERAND_REG(SReg_64_XEXEC)
138 DECODE_OPERAND_REG(SReg_128)
139 DECODE_OPERAND_REG(SReg_256)
140 DECODE_OPERAND_REG(SReg_512)
141 
142 DECODE_OPERAND_REG(AGPR_32)
143 DECODE_OPERAND_REG(AReg_128)
144 DECODE_OPERAND_REG(AReg_512)
145 DECODE_OPERAND_REG(AReg_1024)
146 DECODE_OPERAND_REG(AV_32)
147 DECODE_OPERAND_REG(AV_64)
148 
149 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst,
150                                          unsigned Imm,
151                                          uint64_t Addr,
152                                          const void *Decoder) {
153   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
154   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
155 }
156 
157 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,
158                                          unsigned Imm,
159                                          uint64_t Addr,
160                                          const void *Decoder) {
161   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
162   return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
163 }
164 
165 static DecodeStatus decodeOperand_VS_16(MCInst &Inst,
166                                         unsigned Imm,
167                                         uint64_t Addr,
168                                         const void *Decoder) {
169   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
170   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
171 }
172 
173 static DecodeStatus decodeOperand_VS_32(MCInst &Inst,
174                                         unsigned Imm,
175                                         uint64_t Addr,
176                                         const void *Decoder) {
177   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
178   return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm));
179 }
180 
181 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst,
182                                            unsigned Imm,
183                                            uint64_t Addr,
184                                            const void *Decoder) {
185   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
186   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512));
187 }
188 
189 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst,
190                                            unsigned Imm,
191                                            uint64_t Addr,
192                                            const void *Decoder) {
193   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
194   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512));
195 }
196 
197 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst,
198                                             unsigned Imm,
199                                             uint64_t Addr,
200                                             const void *Decoder) {
201   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
202   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512));
203 }
204 
205 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst,
206                                           unsigned Imm,
207                                           uint64_t Addr,
208                                           const void *Decoder) {
209   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
210   return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm));
211 }
212 
213 static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst,
214                                          unsigned Imm,
215                                          uint64_t Addr,
216                                          const void *Decoder) {
217   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
218   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm));
219 }
220 
221 #define DECODE_SDWA(DecName) \
222 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
223 
224 DECODE_SDWA(Src32)
225 DECODE_SDWA(Src16)
226 DECODE_SDWA(VopcDst)
227 
228 #include "AMDGPUGenDisassemblerTables.inc"
229 
230 //===----------------------------------------------------------------------===//
231 //
232 //===----------------------------------------------------------------------===//
233 
234 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
235   assert(Bytes.size() >= sizeof(T));
236   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
237   Bytes = Bytes.slice(sizeof(T));
238   return Res;
239 }
240 
241 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
242                                                MCInst &MI,
243                                                uint64_t Inst,
244                                                uint64_t Address) const {
245   assert(MI.getOpcode() == 0);
246   assert(MI.getNumOperands() == 0);
247   MCInst TmpInst;
248   HasLiteral = false;
249   const auto SavedBytes = Bytes;
250   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
251     MI = TmpInst;
252     return MCDisassembler::Success;
253   }
254   Bytes = SavedBytes;
255   return MCDisassembler::Fail;
256 }
257 
258 static bool isValidDPP8(const MCInst &MI) {
259   using namespace llvm::AMDGPU::DPP;
260   int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
261   assert(FiIdx != -1);
262   if ((unsigned)FiIdx >= MI.getNumOperands())
263     return false;
264   unsigned Fi = MI.getOperand(FiIdx).getImm();
265   return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
266 }
267 
268 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
269                                                 ArrayRef<uint8_t> Bytes_,
270                                                 uint64_t Address,
271                                                 raw_ostream &WS,
272                                                 raw_ostream &CS) const {
273   CommentStream = &CS;
274   bool IsSDWA = false;
275 
276   unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
277   Bytes = Bytes_.slice(0, MaxInstBytesNum);
278 
279   DecodeStatus Res = MCDisassembler::Fail;
280   do {
281     // ToDo: better to switch encoding length using some bit predicate
282     // but it is unknown yet, so try all we can
283 
284     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
285     // encodings
286     if (Bytes.size() >= 8) {
287       const uint64_t QW = eatBytes<uint64_t>(Bytes);
288 
289       Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address);
290       if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
291         break;
292 
293       MI = MCInst(); // clear
294 
295       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
296       if (Res) break;
297 
298       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
299       if (Res) { IsSDWA = true;  break; }
300 
301       Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
302       if (Res) { IsSDWA = true;  break; }
303 
304       Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
305       if (Res) { IsSDWA = true;  break; }
306 
307       // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
308       // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
309       // table first so we print the correct name.
310 
311       if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
312         Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
313         if (Res) break;
314       }
315 
316       if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
317         Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
318         if (Res)
319           break;
320       }
321 
322       // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
323       // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
324       // table first so we print the correct name.
325       if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
326         Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
327         if (Res)
328           break;
329       }
330     }
331 
332     // Reinitialize Bytes as DPP64 could have eaten too much
333     Bytes = Bytes_.slice(0, MaxInstBytesNum);
334 
335     // Try decode 32-bit instruction
336     if (Bytes.size() < 4) break;
337     const uint32_t DW = eatBytes<uint32_t>(Bytes);
338     Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
339     if (Res) break;
340 
341     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
342     if (Res) break;
343 
344     Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
345     if (Res) break;
346 
347     Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address);
348     if (Res) break;
349 
350     if (Bytes.size() < 4) break;
351     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
352     Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
353     if (Res) break;
354 
355     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
356     if (Res) break;
357 
358     Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
359     if (Res) break;
360 
361     Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
362   } while (false);
363 
364   if (Res && (MaxInstBytesNum - Bytes.size()) == 12 && (!HasLiteral ||
365         !(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3))) {
366     MaxInstBytesNum = 8;
367     Bytes = Bytes_.slice(0, MaxInstBytesNum);
368     eatBytes<uint64_t>(Bytes);
369   }
370 
371   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
372               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
373               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
374               MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
375               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
376               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
377               MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
378     // Insert dummy unused src2_modifiers.
379     insertNamedMCOperand(MI, MCOperand::createImm(0),
380                          AMDGPU::OpName::src2_modifiers);
381   }
382 
383   if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
384     int VAddr0Idx =
385         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
386     int RsrcIdx =
387         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
388     unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
389     if (VAddr0Idx >= 0 && NSAArgs > 0) {
390       unsigned NSAWords = (NSAArgs + 3) / 4;
391       if (Bytes.size() < 4 * NSAWords) {
392         Res = MCDisassembler::Fail;
393       } else {
394         for (unsigned i = 0; i < NSAArgs; ++i) {
395           MI.insert(MI.begin() + VAddr0Idx + 1 + i,
396                     decodeOperand_VGPR_32(Bytes[i]));
397         }
398         Bytes = Bytes.slice(4 * NSAWords);
399       }
400     }
401 
402     if (Res)
403       Res = convertMIMGInst(MI);
404   }
405 
406   if (Res && IsSDWA)
407     Res = convertSDWAInst(MI);
408 
409   int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
410                                               AMDGPU::OpName::vdst_in);
411   if (VDstIn_Idx != -1) {
412     int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
413                            MCOI::OperandConstraint::TIED_TO);
414     if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
415          !MI.getOperand(VDstIn_Idx).isReg() ||
416          MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
417       if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
418         MI.erase(&MI.getOperand(VDstIn_Idx));
419       insertNamedMCOperand(MI,
420         MCOperand::createReg(MI.getOperand(Tied).getReg()),
421         AMDGPU::OpName::vdst_in);
422     }
423   }
424 
425   // if the opcode was not recognized we'll assume a Size of 4 bytes
426   // (unless there are fewer bytes left)
427   Size = Res ? (MaxInstBytesNum - Bytes.size())
428              : std::min((size_t)4, Bytes_.size());
429   return Res;
430 }
431 
432 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
433   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
434       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
435     if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
436       // VOPC - insert clamp
437       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
438   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
439     int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
440     if (SDst != -1) {
441       // VOPC - insert VCC register as sdst
442       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
443                            AMDGPU::OpName::sdst);
444     } else {
445       // VOP1/2 - insert omod if present in instruction
446       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
447     }
448   }
449   return MCDisassembler::Success;
450 }
451 
452 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
453   unsigned Opc = MI.getOpcode();
454   unsigned DescNumOps = MCII->get(Opc).getNumOperands();
455 
456   // Insert dummy unused src modifiers.
457   if (MI.getNumOperands() < DescNumOps &&
458       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
459     insertNamedMCOperand(MI, MCOperand::createImm(0),
460                          AMDGPU::OpName::src0_modifiers);
461 
462   if (MI.getNumOperands() < DescNumOps &&
463       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
464     insertNamedMCOperand(MI, MCOperand::createImm(0),
465                          AMDGPU::OpName::src1_modifiers);
466 
467   return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail;
468 }
469 
470 // Note that before gfx10, the MIMG encoding provided no information about
471 // VADDR size. Consequently, decoded instructions always show address as if it
472 // has 1 dword, which could be not really so.
473 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
474 
475   int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
476                                            AMDGPU::OpName::vdst);
477 
478   int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
479                                             AMDGPU::OpName::vdata);
480   int VAddr0Idx =
481       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
482   int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
483                                             AMDGPU::OpName::dmask);
484 
485   int TFEIdx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
486                                             AMDGPU::OpName::tfe);
487   int D16Idx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
488                                             AMDGPU::OpName::d16);
489 
490   assert(VDataIdx != -1);
491   assert(DMaskIdx != -1);
492   assert(TFEIdx != -1);
493 
494   const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
495   bool IsAtomic = (VDstIdx != -1);
496   bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
497 
498   bool IsNSA = false;
499   unsigned AddrSize = Info->VAddrDwords;
500 
501   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
502     unsigned DimIdx =
503         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
504     const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
505         AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
506     const AMDGPU::MIMGDimInfo *Dim =
507         AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm());
508 
509     AddrSize = BaseOpcode->NumExtraArgs +
510                (BaseOpcode->Gradients ? Dim->NumGradients : 0) +
511                (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
512                (BaseOpcode->LodOrClampOrMip ? 1 : 0);
513     IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA;
514     if (!IsNSA) {
515       if (AddrSize > 8)
516         AddrSize = 16;
517       else if (AddrSize > 4)
518         AddrSize = 8;
519     } else {
520       if (AddrSize > Info->VAddrDwords) {
521         // The NSA encoding does not contain enough operands for the combination
522         // of base opcode / dimension. Should this be an error?
523         return MCDisassembler::Success;
524       }
525     }
526   }
527 
528   unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
529   unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u);
530 
531   bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
532   if (D16 && AMDGPU::hasPackedD16(STI)) {
533     DstSize = (DstSize + 1) / 2;
534   }
535 
536   // FIXME: Add tfe support
537   if (MI.getOperand(TFEIdx).getImm())
538     return MCDisassembler::Success;
539 
540   if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
541     return MCDisassembler::Success;
542 
543   int NewOpcode =
544       AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
545   if (NewOpcode == -1)
546     return MCDisassembler::Success;
547 
548   // Widen the register to the correct number of enabled channels.
549   unsigned NewVdata = AMDGPU::NoRegister;
550   if (DstSize != Info->VDataDwords) {
551     auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
552 
553     // Get first subregister of VData
554     unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
555     unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
556     Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
557 
558     NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
559                                        &MRI.getRegClass(DataRCID));
560     if (NewVdata == AMDGPU::NoRegister) {
561       // It's possible to encode this such that the low register + enabled
562       // components exceeds the register count.
563       return MCDisassembler::Success;
564     }
565   }
566 
567   unsigned NewVAddr0 = AMDGPU::NoRegister;
568   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA &&
569       AddrSize != Info->VAddrDwords) {
570     unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg();
571     unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0);
572     VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
573 
574     auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
575     NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0,
576                                         &MRI.getRegClass(AddrRCID));
577     if (NewVAddr0 == AMDGPU::NoRegister)
578       return MCDisassembler::Success;
579   }
580 
581   MI.setOpcode(NewOpcode);
582 
583   if (NewVdata != AMDGPU::NoRegister) {
584     MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
585 
586     if (IsAtomic) {
587       // Atomic operations have an additional operand (a copy of data)
588       MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
589     }
590   }
591 
592   if (NewVAddr0 != AMDGPU::NoRegister) {
593     MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
594   } else if (IsNSA) {
595     assert(AddrSize <= Info->VAddrDwords);
596     MI.erase(MI.begin() + VAddr0Idx + AddrSize,
597              MI.begin() + VAddr0Idx + Info->VAddrDwords);
598   }
599 
600   return MCDisassembler::Success;
601 }
602 
603 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
604   return getContext().getRegisterInfo()->
605     getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
606 }
607 
608 inline
609 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
610                                          const Twine& ErrMsg) const {
611   *CommentStream << "Error: " + ErrMsg;
612 
613   // ToDo: add support for error operands to MCInst.h
614   // return MCOperand::createError(V);
615   return MCOperand();
616 }
617 
618 inline
619 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
620   return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
621 }
622 
623 inline
624 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
625                                                unsigned Val) const {
626   const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
627   if (Val >= RegCl.getNumRegs())
628     return errOperand(Val, Twine(getRegClassName(RegClassID)) +
629                            ": unknown register " + Twine(Val));
630   return createRegOperand(RegCl.getRegister(Val));
631 }
632 
633 inline
634 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
635                                                 unsigned Val) const {
636   // ToDo: SI/CI have 104 SGPRs, VI - 102
637   // Valery: here we accepting as much as we can, let assembler sort it out
638   int shift = 0;
639   switch (SRegClassID) {
640   case AMDGPU::SGPR_32RegClassID:
641   case AMDGPU::TTMP_32RegClassID:
642     break;
643   case AMDGPU::SGPR_64RegClassID:
644   case AMDGPU::TTMP_64RegClassID:
645     shift = 1;
646     break;
647   case AMDGPU::SGPR_128RegClassID:
648   case AMDGPU::TTMP_128RegClassID:
649   // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
650   // this bundle?
651   case AMDGPU::SGPR_256RegClassID:
652   case AMDGPU::TTMP_256RegClassID:
653     // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
654   // this bundle?
655   case AMDGPU::SGPR_512RegClassID:
656   case AMDGPU::TTMP_512RegClassID:
657     shift = 2;
658     break;
659   // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
660   // this bundle?
661   default:
662     llvm_unreachable("unhandled register class");
663   }
664 
665   if (Val % (1 << shift)) {
666     *CommentStream << "Warning: " << getRegClassName(SRegClassID)
667                    << ": scalar reg isn't aligned " << Val;
668   }
669 
670   return createRegOperand(SRegClassID, Val >> shift);
671 }
672 
673 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
674   return decodeSrcOp(OPW32, Val);
675 }
676 
677 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
678   return decodeSrcOp(OPW64, Val);
679 }
680 
681 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const {
682   return decodeSrcOp(OPW128, Val);
683 }
684 
685 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const {
686   return decodeSrcOp(OPW16, Val);
687 }
688 
689 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const {
690   return decodeSrcOp(OPWV216, Val);
691 }
692 
693 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
694   // Some instructions have operand restrictions beyond what the encoding
695   // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
696   // high bit.
697   Val &= 255;
698 
699   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
700 }
701 
702 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const {
703   return decodeSrcOp(OPW32, Val);
704 }
705 
706 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const {
707   return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255);
708 }
709 
710 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const {
711   return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255);
712 }
713 
714 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const {
715   return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255);
716 }
717 
718 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const {
719   return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255);
720 }
721 
722 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const {
723   return decodeSrcOp(OPW32, Val);
724 }
725 
726 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const {
727   return decodeSrcOp(OPW64, Val);
728 }
729 
730 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
731   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
732 }
733 
734 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
735   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
736 }
737 
738 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
739   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
740 }
741 
742 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const {
743   return createRegOperand(AMDGPU::VReg_256RegClassID, Val);
744 }
745 
746 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const {
747   return createRegOperand(AMDGPU::VReg_512RegClassID, Val);
748 }
749 
750 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
751   // table-gen generated disassembler doesn't care about operand types
752   // leaving only registry class so SSrc_32 operand turns into SReg_32
753   // and therefore we accept immediates and literals here as well
754   return decodeSrcOp(OPW32, Val);
755 }
756 
757 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC(
758   unsigned Val) const {
759   // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
760   return decodeOperand_SReg_32(Val);
761 }
762 
763 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI(
764   unsigned Val) const {
765   // SReg_32_XM0 is SReg_32 without EXEC_HI
766   return decodeOperand_SReg_32(Val);
767 }
768 
769 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const {
770   // table-gen generated disassembler doesn't care about operand types
771   // leaving only registry class so SSrc_32 operand turns into SReg_32
772   // and therefore we accept immediates and literals here as well
773   return decodeSrcOp(OPW32, Val);
774 }
775 
776 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
777   return decodeSrcOp(OPW64, Val);
778 }
779 
780 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const {
781   return decodeSrcOp(OPW64, Val);
782 }
783 
784 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
785   return decodeSrcOp(OPW128, Val);
786 }
787 
788 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
789   return decodeDstOp(OPW256, Val);
790 }
791 
792 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
793   return decodeDstOp(OPW512, Val);
794 }
795 
796 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
797   // For now all literal constants are supposed to be unsigned integer
798   // ToDo: deal with signed/unsigned 64-bit integer constants
799   // ToDo: deal with float/double constants
800   if (!HasLiteral) {
801     if (Bytes.size() < 4) {
802       return errOperand(0, "cannot read literal, inst bytes left " +
803                         Twine(Bytes.size()));
804     }
805     HasLiteral = true;
806     Literal = eatBytes<uint32_t>(Bytes);
807   }
808   return MCOperand::createImm(Literal);
809 }
810 
811 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
812   using namespace AMDGPU::EncValues;
813 
814   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
815   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
816     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
817     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
818       // Cast prevents negative overflow.
819 }
820 
821 static int64_t getInlineImmVal32(unsigned Imm) {
822   switch (Imm) {
823   case 240:
824     return FloatToBits(0.5f);
825   case 241:
826     return FloatToBits(-0.5f);
827   case 242:
828     return FloatToBits(1.0f);
829   case 243:
830     return FloatToBits(-1.0f);
831   case 244:
832     return FloatToBits(2.0f);
833   case 245:
834     return FloatToBits(-2.0f);
835   case 246:
836     return FloatToBits(4.0f);
837   case 247:
838     return FloatToBits(-4.0f);
839   case 248: // 1 / (2 * PI)
840     return 0x3e22f983;
841   default:
842     llvm_unreachable("invalid fp inline imm");
843   }
844 }
845 
846 static int64_t getInlineImmVal64(unsigned Imm) {
847   switch (Imm) {
848   case 240:
849     return DoubleToBits(0.5);
850   case 241:
851     return DoubleToBits(-0.5);
852   case 242:
853     return DoubleToBits(1.0);
854   case 243:
855     return DoubleToBits(-1.0);
856   case 244:
857     return DoubleToBits(2.0);
858   case 245:
859     return DoubleToBits(-2.0);
860   case 246:
861     return DoubleToBits(4.0);
862   case 247:
863     return DoubleToBits(-4.0);
864   case 248: // 1 / (2 * PI)
865     return 0x3fc45f306dc9c882;
866   default:
867     llvm_unreachable("invalid fp inline imm");
868   }
869 }
870 
871 static int64_t getInlineImmVal16(unsigned Imm) {
872   switch (Imm) {
873   case 240:
874     return 0x3800;
875   case 241:
876     return 0xB800;
877   case 242:
878     return 0x3C00;
879   case 243:
880     return 0xBC00;
881   case 244:
882     return 0x4000;
883   case 245:
884     return 0xC000;
885   case 246:
886     return 0x4400;
887   case 247:
888     return 0xC400;
889   case 248: // 1 / (2 * PI)
890     return 0x3118;
891   default:
892     llvm_unreachable("invalid fp inline imm");
893   }
894 }
895 
896 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) {
897   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN
898       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
899 
900   // ToDo: case 248: 1/(2*PI) - is allowed only on VI
901   switch (Width) {
902   case OPW32:
903   case OPW128: // splat constants
904   case OPW512:
905   case OPW1024:
906     return MCOperand::createImm(getInlineImmVal32(Imm));
907   case OPW64:
908     return MCOperand::createImm(getInlineImmVal64(Imm));
909   case OPW16:
910   case OPWV216:
911     return MCOperand::createImm(getInlineImmVal16(Imm));
912   default:
913     llvm_unreachable("implement me");
914   }
915 }
916 
917 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
918   using namespace AMDGPU;
919 
920   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
921   switch (Width) {
922   default: // fall
923   case OPW32:
924   case OPW16:
925   case OPWV216:
926     return VGPR_32RegClassID;
927   case OPW64: return VReg_64RegClassID;
928   case OPW128: return VReg_128RegClassID;
929   }
930 }
931 
932 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const {
933   using namespace AMDGPU;
934 
935   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
936   switch (Width) {
937   default: // fall
938   case OPW32:
939   case OPW16:
940   case OPWV216:
941     return AGPR_32RegClassID;
942   case OPW64: return AReg_64RegClassID;
943   case OPW128: return AReg_128RegClassID;
944   case OPW512: return AReg_512RegClassID;
945   case OPW1024: return AReg_1024RegClassID;
946   }
947 }
948 
949 
950 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
951   using namespace AMDGPU;
952 
953   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
954   switch (Width) {
955   default: // fall
956   case OPW32:
957   case OPW16:
958   case OPWV216:
959     return SGPR_32RegClassID;
960   case OPW64: return SGPR_64RegClassID;
961   case OPW128: return SGPR_128RegClassID;
962   case OPW256: return SGPR_256RegClassID;
963   case OPW512: return SGPR_512RegClassID;
964   }
965 }
966 
967 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
968   using namespace AMDGPU;
969 
970   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
971   switch (Width) {
972   default: // fall
973   case OPW32:
974   case OPW16:
975   case OPWV216:
976     return TTMP_32RegClassID;
977   case OPW64: return TTMP_64RegClassID;
978   case OPW128: return TTMP_128RegClassID;
979   case OPW256: return TTMP_256RegClassID;
980   case OPW512: return TTMP_512RegClassID;
981   }
982 }
983 
984 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
985   using namespace AMDGPU::EncValues;
986 
987   unsigned TTmpMin =
988       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN;
989   unsigned TTmpMax =
990       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX;
991 
992   return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
993 }
994 
995 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
996   using namespace AMDGPU::EncValues;
997 
998   assert(Val < 1024); // enum10
999 
1000   bool IsAGPR = Val & 512;
1001   Val &= 511;
1002 
1003   if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
1004     return createRegOperand(IsAGPR ? getAgprClassId(Width)
1005                                    : getVgprClassId(Width), Val - VGPR_MIN);
1006   }
1007   if (Val <= SGPR_MAX) {
1008     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1009     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1010   }
1011 
1012   int TTmpIdx = getTTmpIdx(Val);
1013   if (TTmpIdx >= 0) {
1014     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1015   }
1016 
1017   if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1018     return decodeIntImmed(Val);
1019 
1020   if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1021     return decodeFPImmed(Width, Val);
1022 
1023   if (Val == LITERAL_CONST)
1024     return decodeLiteralConstant();
1025 
1026   switch (Width) {
1027   case OPW32:
1028   case OPW16:
1029   case OPWV216:
1030     return decodeSpecialReg32(Val);
1031   case OPW64:
1032     return decodeSpecialReg64(Val);
1033   default:
1034     llvm_unreachable("unexpected immediate type");
1035   }
1036 }
1037 
1038 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const {
1039   using namespace AMDGPU::EncValues;
1040 
1041   assert(Val < 128);
1042   assert(Width == OPW256 || Width == OPW512);
1043 
1044   if (Val <= SGPR_MAX) {
1045     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1046     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1047   }
1048 
1049   int TTmpIdx = getTTmpIdx(Val);
1050   if (TTmpIdx >= 0) {
1051     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1052   }
1053 
1054   llvm_unreachable("unknown dst register");
1055 }
1056 
1057 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
1058   using namespace AMDGPU;
1059 
1060   switch (Val) {
1061   case 102: return createRegOperand(FLAT_SCR_LO);
1062   case 103: return createRegOperand(FLAT_SCR_HI);
1063   case 104: return createRegOperand(XNACK_MASK_LO);
1064   case 105: return createRegOperand(XNACK_MASK_HI);
1065   case 106: return createRegOperand(VCC_LO);
1066   case 107: return createRegOperand(VCC_HI);
1067   case 108: return createRegOperand(TBA_LO);
1068   case 109: return createRegOperand(TBA_HI);
1069   case 110: return createRegOperand(TMA_LO);
1070   case 111: return createRegOperand(TMA_HI);
1071   case 124: return createRegOperand(M0);
1072   case 125: return createRegOperand(SGPR_NULL);
1073   case 126: return createRegOperand(EXEC_LO);
1074   case 127: return createRegOperand(EXEC_HI);
1075   case 235: return createRegOperand(SRC_SHARED_BASE);
1076   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1077   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1078   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1079   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1080   case 251: return createRegOperand(SRC_VCCZ);
1081   case 252: return createRegOperand(SRC_EXECZ);
1082   case 253: return createRegOperand(SRC_SCC);
1083   case 254: return createRegOperand(LDS_DIRECT);
1084   default: break;
1085   }
1086   return errOperand(Val, "unknown operand encoding " + Twine(Val));
1087 }
1088 
1089 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
1090   using namespace AMDGPU;
1091 
1092   switch (Val) {
1093   case 102: return createRegOperand(FLAT_SCR);
1094   case 104: return createRegOperand(XNACK_MASK);
1095   case 106: return createRegOperand(VCC);
1096   case 108: return createRegOperand(TBA);
1097   case 110: return createRegOperand(TMA);
1098   case 126: return createRegOperand(EXEC);
1099   case 235: return createRegOperand(SRC_SHARED_BASE);
1100   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1101   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1102   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1103   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1104   case 251: return createRegOperand(SRC_VCCZ);
1105   case 252: return createRegOperand(SRC_EXECZ);
1106   case 253: return createRegOperand(SRC_SCC);
1107   default: break;
1108   }
1109   return errOperand(Val, "unknown operand encoding " + Twine(Val));
1110 }
1111 
1112 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
1113                                             const unsigned Val) const {
1114   using namespace AMDGPU::SDWA;
1115   using namespace AMDGPU::EncValues;
1116 
1117   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1118       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
1119     // XXX: cast to int is needed to avoid stupid warning:
1120     // compare with unsigned is always true
1121     if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
1122         Val <= SDWA9EncValues::SRC_VGPR_MAX) {
1123       return createRegOperand(getVgprClassId(Width),
1124                               Val - SDWA9EncValues::SRC_VGPR_MIN);
1125     }
1126     if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1127         Val <= (isGFX10() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
1128                           : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
1129       return createSRegOperand(getSgprClassId(Width),
1130                                Val - SDWA9EncValues::SRC_SGPR_MIN);
1131     }
1132     if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1133         Val <= SDWA9EncValues::SRC_TTMP_MAX) {
1134       return createSRegOperand(getTtmpClassId(Width),
1135                                Val - SDWA9EncValues::SRC_TTMP_MIN);
1136     }
1137 
1138     const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1139 
1140     if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1141       return decodeIntImmed(SVal);
1142 
1143     if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1144       return decodeFPImmed(Width, SVal);
1145 
1146     return decodeSpecialReg32(SVal);
1147   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
1148     return createRegOperand(getVgprClassId(Width), Val);
1149   }
1150   llvm_unreachable("unsupported target");
1151 }
1152 
1153 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {
1154   return decodeSDWASrc(OPW16, Val);
1155 }
1156 
1157 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
1158   return decodeSDWASrc(OPW32, Val);
1159 }
1160 
1161 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
1162   using namespace AMDGPU::SDWA;
1163 
1164   assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1165           STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
1166          "SDWAVopcDst should be present only on GFX9+");
1167 
1168   bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
1169 
1170   if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
1171     Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
1172 
1173     int TTmpIdx = getTTmpIdx(Val);
1174     if (TTmpIdx >= 0) {
1175       return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx);
1176     } else if (Val > SGPR_MAX) {
1177       return IsWave64 ? decodeSpecialReg64(Val)
1178                       : decodeSpecialReg32(Val);
1179     } else {
1180       return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
1181     }
1182   } else {
1183     return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1184   }
1185 }
1186 
1187 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
1188   return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
1189     decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val);
1190 }
1191 
1192 bool AMDGPUDisassembler::isVI() const {
1193   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1194 }
1195 
1196 bool AMDGPUDisassembler::isGFX9() const {
1197   return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
1198 }
1199 
1200 bool AMDGPUDisassembler::isGFX10() const {
1201   return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
1202 }
1203 
1204 //===----------------------------------------------------------------------===//
1205 // AMDGPUSymbolizer
1206 //===----------------------------------------------------------------------===//
1207 
1208 // Try to find symbol name for specified label
1209 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
1210                                 raw_ostream &/*cStream*/, int64_t Value,
1211                                 uint64_t /*Address*/, bool IsBranch,
1212                                 uint64_t /*Offset*/, uint64_t /*InstSize*/) {
1213   using SymbolInfoTy = std::tuple<uint64_t, StringRef, uint8_t>;
1214   using SectionSymbolsTy = std::vector<SymbolInfoTy>;
1215 
1216   if (!IsBranch) {
1217     return false;
1218   }
1219 
1220   auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
1221   if (!Symbols)
1222     return false;
1223 
1224   auto Result = std::find_if(Symbols->begin(), Symbols->end(),
1225                              [Value](const SymbolInfoTy& Val) {
1226                                 return std::get<0>(Val) == static_cast<uint64_t>(Value)
1227                                     && std::get<2>(Val) == ELF::STT_NOTYPE;
1228                              });
1229   if (Result != Symbols->end()) {
1230     auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result));
1231     const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
1232     Inst.addOperand(MCOperand::createExpr(Add));
1233     return true;
1234   }
1235   return false;
1236 }
1237 
1238 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream,
1239                                                        int64_t Value,
1240                                                        uint64_t Address) {
1241   llvm_unreachable("unimplemented");
1242 }
1243 
1244 //===----------------------------------------------------------------------===//
1245 // Initialization
1246 //===----------------------------------------------------------------------===//
1247 
1248 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
1249                               LLVMOpInfoCallback /*GetOpInfo*/,
1250                               LLVMSymbolLookupCallback /*SymbolLookUp*/,
1251                               void *DisInfo,
1252                               MCContext *Ctx,
1253                               std::unique_ptr<MCRelocationInfo> &&RelInfo) {
1254   return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
1255 }
1256 
1257 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
1258                                                 const MCSubtargetInfo &STI,
1259                                                 MCContext &Ctx) {
1260   return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
1261 }
1262 
1263 extern "C" void LLVMInitializeAMDGPUDisassembler() {
1264   TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(),
1265                                          createAMDGPUDisassembler);
1266   TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
1267                                        createAMDGPUSymbolizer);
1268 }
1269