xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/DSInstructions.td (revision dd41de95a84d979615a2ef11df6850622bf6184e) 
1//===-- DSInstructions.td - DS Instruction Definitions --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
10  InstSI <outs, ins, "", pattern>,
11  SIMCInstr <opName, SIEncodingFamily.NONE> {
12
13  let LGKM_CNT = 1;
14  let DS = 1;
15  let Size = 8;
16  let UseNamedOperandTable = 1;
17
18  // Most instruction load and store data, so set this as the default.
19  let mayLoad = 1;
20  let mayStore = 1;
21  let maybeAtomic = 1;
22
23  let hasSideEffects = 0;
24  let SchedRW = [WriteLDS];
25
26  let isPseudo = 1;
27  let isCodeGenOnly = 1;
28
29  let AsmMatchConverter = "cvtDS";
30
31  string Mnemonic = opName;
32  string AsmOperands = asmOps;
33
34  // Well these bits a kind of hack because it would be more natural
35  // to test "outs" and "ins" dags for the presence of particular operands
36  bits<1> has_vdst = 1;
37  bits<1> has_addr = 1;
38  bits<1> has_data0 = 1;
39  bits<1> has_data1 = 1;
40
41  bits<1> has_gws_data0 = 0; // data0 is encoded as addr
42
43  bits<1> has_offset  = 1; // has "offset" that should be split to offset0,1
44  bits<1> has_offset0 = 1;
45  bits<1> has_offset1 = 1;
46
47  bits<1> has_gds = 1;
48  bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
49
50  bits<1> has_m0_read = 1;
51
52  let Uses = !if(has_m0_read, [M0, EXEC], [EXEC]);
53}
54
55class DS_Real <DS_Pseudo ds> :
56  InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
57  Enc64 {
58
59  let isPseudo = 0;
60  let isCodeGenOnly = 0;
61  let DS = 1;
62  let UseNamedOperandTable = 1;
63
64  // copy relevant pseudo op flags
65  let SubtargetPredicate = ds.SubtargetPredicate;
66  let OtherPredicates = ds.OtherPredicates;
67  let AsmMatchConverter  = ds.AsmMatchConverter;
68
69  // encoding fields
70  bits<8> vdst;
71  bits<1> gds;
72  bits<8> addr;
73  bits<8> data0;
74  bits<8> data1;
75  bits<8> offset0;
76  bits<8> offset1;
77
78  bits<16> offset;
79  let offset0 = !if(ds.has_offset, offset{7-0}, ?);
80  let offset1 = !if(ds.has_offset, offset{15-8}, ?);
81}
82
83
84// DS Pseudo instructions
85
86class DS_0A1D_NORET<string opName, RegisterClass rc = VGPR_32>
87: DS_Pseudo<opName,
88  (outs),
89  (ins rc:$data0, offset:$offset, gds:$gds),
90  "$data0$offset$gds"> {
91
92  let has_addr = 0;
93  let has_data1 = 0;
94  let has_vdst = 0;
95}
96
97class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
98: DS_Pseudo<opName,
99  (outs),
100  (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
101  "$addr, $data0$offset$gds"> {
102
103  let has_data1 = 0;
104  let has_vdst = 0;
105}
106
107multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
108  def "" : DS_1A1D_NORET<opName, rc>,
109           AtomicNoRet<opName, 0>;
110
111  let has_m0_read = 0 in {
112    def _gfx9 : DS_1A1D_NORET<opName, rc>,
113                AtomicNoRet<opName#"_gfx9", 0>;
114  }
115}
116
117class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
118: DS_Pseudo<opName,
119  (outs),
120  (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
121  "$addr, $data0, $data1"#"$offset"#"$gds"> {
122
123  let has_vdst = 0;
124}
125
126multiclass DS_1A2D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
127  def "" : DS_1A2D_NORET<opName, rc>,
128           AtomicNoRet<opName, 0>;
129
130  let has_m0_read = 0 in {
131    def _gfx9 : DS_1A2D_NORET<opName, rc>,
132                AtomicNoRet<opName#"_gfx9", 0>;
133  }
134}
135
136class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
137: DS_Pseudo<opName,
138  (outs),
139  (ins VGPR_32:$addr, rc:$data0, rc:$data1,
140       offset0:$offset0, offset1:$offset1, gds:$gds),
141  "$addr, $data0, $data1$offset0$offset1$gds"> {
142
143  let has_vdst = 0;
144  let has_offset = 0;
145  let AsmMatchConverter = "cvtDSOffset01";
146}
147
148multiclass DS_1A2D_Off8_NORET_mc <string opName, RegisterClass rc = VGPR_32> {
149  def "" : DS_1A2D_Off8_NORET<opName, rc>;
150
151  let has_m0_read = 0 in {
152    def _gfx9 : DS_1A2D_Off8_NORET<opName, rc>;
153  }
154}
155
156class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
157: DS_Pseudo<opName,
158  (outs rc:$vdst),
159  (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
160  "$vdst, $addr, $data0$offset$gds"> {
161
162  let hasPostISelHook = 1;
163  let has_data1 = 0;
164}
165
166multiclass DS_1A1D_RET_mc <string opName, RegisterClass rc = VGPR_32,
167                           string NoRetOp = ""> {
168  def "" : DS_1A1D_RET<opName, rc>,
169    AtomicNoRet<NoRetOp, !if(!eq(NoRetOp, ""), 0, 1)>;
170
171  let has_m0_read = 0 in {
172    def _gfx9 : DS_1A1D_RET<opName, rc>,
173      AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp#"_gfx9"),
174                  !if(!eq(NoRetOp, ""), 0, 1)>;
175  }
176}
177
178class DS_1A2D_RET<string opName,
179                  RegisterClass rc = VGPR_32,
180                  RegisterClass src = rc>
181: DS_Pseudo<opName,
182  (outs rc:$vdst),
183  (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
184  "$vdst, $addr, $data0, $data1$offset$gds"> {
185
186  let hasPostISelHook = 1;
187}
188
189multiclass DS_1A2D_RET_mc<string opName,
190                          RegisterClass rc = VGPR_32,
191                          string NoRetOp = "",
192                          RegisterClass src = rc> {
193  def "" : DS_1A2D_RET<opName, rc, src>,
194    AtomicNoRet<NoRetOp, !if(!eq(NoRetOp, ""), 0, 1)>;
195
196  let has_m0_read = 0 in {
197    def _gfx9 : DS_1A2D_RET<opName, rc, src>,
198      AtomicNoRet<NoRetOp#"_gfx9", !if(!eq(NoRetOp, ""), 0, 1)>;
199  }
200}
201
202class DS_1A2D_Off8_RET<string opName,
203                       RegisterClass rc = VGPR_32,
204                       RegisterClass src = rc>
205: DS_Pseudo<opName,
206  (outs rc:$vdst),
207  (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
208  "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
209
210  let has_offset = 0;
211  let AsmMatchConverter = "cvtDSOffset01";
212
213  let hasPostISelHook = 1;
214}
215
216multiclass DS_1A2D_Off8_RET_mc<string opName,
217                               RegisterClass rc = VGPR_32,
218                               RegisterClass src = rc> {
219  def "" : DS_1A2D_Off8_RET<opName, rc, src>;
220
221  let has_m0_read = 0 in {
222    def _gfx9 : DS_1A2D_Off8_RET<opName, rc, src>;
223  }
224}
225
226
227class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset>
228: DS_Pseudo<opName,
229  (outs rc:$vdst),
230  !if(HasTiedOutput,
231    (ins VGPR_32:$addr, ofs:$offset, gds:$gds, rc:$vdst_in),
232    (ins VGPR_32:$addr, ofs:$offset, gds:$gds)),
233  "$vdst, $addr$offset$gds"> {
234  let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
235  let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
236  let has_data0 = 0;
237  let has_data1 = 0;
238}
239
240multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> {
241  def "" : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
242
243  let has_m0_read = 0 in {
244    def _gfx9 : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
245  }
246}
247
248class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> :
249  DS_1A_RET<opName, rc, 1>;
250
251class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
252: DS_Pseudo<opName,
253  (outs rc:$vdst),
254  (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
255  "$vdst, $addr$offset0$offset1$gds"> {
256
257  let has_offset = 0;
258  let has_data0 = 0;
259  let has_data1 = 0;
260  let AsmMatchConverter = "cvtDSOffset01";
261}
262
263multiclass DS_1A_Off8_RET_mc <string opName, RegisterClass rc = VGPR_32> {
264  def "" : DS_1A_Off8_RET<opName, rc>;
265
266  let has_m0_read = 0 in {
267    def _gfx9 : DS_1A_Off8_RET<opName, rc>;
268  }
269}
270
271class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
272  (outs VGPR_32:$vdst),
273  (ins VGPR_32:$addr, offset:$offset),
274  "$vdst, $addr$offset gds"> {
275
276  let has_data0 = 0;
277  let has_data1 = 0;
278  let has_gds = 0;
279  let gdsValue = 1;
280  let AsmMatchConverter = "cvtDSGds";
281}
282
283class DS_0A_RET <string opName> : DS_Pseudo<opName,
284  (outs VGPR_32:$vdst),
285  (ins offset:$offset, gds:$gds),
286  "$vdst$offset$gds"> {
287
288  let mayLoad = 1;
289  let mayStore = 1;
290
291  let has_addr = 0;
292  let has_data0 = 0;
293  let has_data1 = 0;
294}
295
296class DS_1A <string opName> : DS_Pseudo<opName,
297  (outs),
298  (ins VGPR_32:$addr, offset:$offset, gds:$gds),
299  "$addr$offset$gds"> {
300
301  let mayLoad = 1;
302  let mayStore = 1;
303
304  let has_vdst = 0;
305  let has_data0 = 0;
306  let has_data1 = 0;
307}
308
309multiclass DS_1A_mc <string opName> {
310  def "" : DS_1A<opName>;
311
312  let has_m0_read = 0 in {
313    def _gfx9 : DS_1A<opName>;
314  }
315}
316
317
318class DS_GWS <string opName, dag ins, string asmOps>
319: DS_Pseudo<opName, (outs), ins, asmOps> {
320
321  let has_vdst  = 0;
322  let has_addr  = 0;
323  let has_data0 = 0;
324  let has_data1 = 0;
325
326  let has_gds   = 0;
327  let gdsValue  = 1;
328  let AsmMatchConverter = "cvtDSGds";
329}
330
331class DS_GWS_0D <string opName>
332: DS_GWS<opName,
333  (ins offset:$offset, gds:$gds), "$offset gds"> {
334  let hasSideEffects = 1;
335}
336
337class DS_GWS_1D <string opName>
338: DS_GWS<opName,
339  (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
340
341  let has_gws_data0 = 1;
342  let hasSideEffects = 1;
343}
344
345class DS_VOID <string opName> : DS_Pseudo<opName,
346  (outs), (ins), ""> {
347  let mayLoad = 0;
348  let mayStore = 0;
349  let hasSideEffects = 1;
350  let UseNamedOperandTable = 0;
351  let AsmMatchConverter = "";
352
353  let has_vdst = 0;
354  let has_addr = 0;
355  let has_data0 = 0;
356  let has_data1 = 0;
357  let has_offset = 0;
358  let has_offset0 = 0;
359  let has_offset1 = 0;
360  let has_gds = 0;
361}
362
363class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
364: DS_Pseudo<opName,
365  (outs VGPR_32:$vdst),
366  (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
367  "$vdst, $addr, $data0$offset",
368  [(set i32:$vdst,
369   (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
370
371  let mayLoad = 0;
372  let mayStore = 0;
373  let isConvergent = 1;
374
375  let has_data1 = 0;
376  let has_gds = 0;
377}
378
379defm DS_ADD_U32       : DS_1A1D_NORET_mc<"ds_add_u32">;
380defm DS_SUB_U32       : DS_1A1D_NORET_mc<"ds_sub_u32">;
381defm DS_RSUB_U32      : DS_1A1D_NORET_mc<"ds_rsub_u32">;
382defm DS_INC_U32       : DS_1A1D_NORET_mc<"ds_inc_u32">;
383defm DS_DEC_U32       : DS_1A1D_NORET_mc<"ds_dec_u32">;
384defm DS_MIN_I32       : DS_1A1D_NORET_mc<"ds_min_i32">;
385defm DS_MAX_I32       : DS_1A1D_NORET_mc<"ds_max_i32">;
386defm DS_MIN_U32       : DS_1A1D_NORET_mc<"ds_min_u32">;
387defm DS_MAX_U32       : DS_1A1D_NORET_mc<"ds_max_u32">;
388defm DS_AND_B32       : DS_1A1D_NORET_mc<"ds_and_b32">;
389defm DS_OR_B32        : DS_1A1D_NORET_mc<"ds_or_b32">;
390defm DS_XOR_B32       : DS_1A1D_NORET_mc<"ds_xor_b32">;
391
392let SubtargetPredicate = HasLDSFPAtomics in {
393defm DS_ADD_F32       : DS_1A1D_NORET_mc<"ds_add_f32">;
394}
395
396// FIXME: Are these really present pre-gfx8?
397defm DS_MIN_F32       : DS_1A1D_NORET_mc<"ds_min_f32">;
398defm DS_MAX_F32       : DS_1A1D_NORET_mc<"ds_max_f32">;
399
400let mayLoad = 0 in {
401defm DS_WRITE_B8      : DS_1A1D_NORET_mc<"ds_write_b8">;
402defm DS_WRITE_B16     : DS_1A1D_NORET_mc<"ds_write_b16">;
403defm DS_WRITE_B32     : DS_1A1D_NORET_mc<"ds_write_b32">;
404defm DS_WRITE2_B32    : DS_1A2D_Off8_NORET_mc<"ds_write2_b32">;
405defm DS_WRITE2ST64_B32: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b32">;
406
407
408let has_m0_read = 0 in {
409
410let SubtargetPredicate = HasD16LoadStore in {
411def DS_WRITE_B8_D16_HI  : DS_1A1D_NORET<"ds_write_b8_d16_hi">;
412def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">;
413}
414
415} // End has_m0_read = 0
416
417let SubtargetPredicate = HasDSAddTid in {
418def DS_WRITE_ADDTID_B32 : DS_0A1D_NORET<"ds_write_addtid_b32">;
419}
420
421} // End mayLoad = 0
422
423defm DS_MSKOR_B32     : DS_1A2D_NORET_mc<"ds_mskor_b32">;
424defm DS_CMPST_B32     : DS_1A2D_NORET_mc<"ds_cmpst_b32">;
425defm DS_CMPST_F32     : DS_1A2D_NORET_mc<"ds_cmpst_f32">;
426
427defm DS_ADD_U64       : DS_1A1D_NORET_mc<"ds_add_u64", VReg_64>;
428defm DS_SUB_U64       : DS_1A1D_NORET_mc<"ds_sub_u64", VReg_64>;
429defm DS_RSUB_U64      : DS_1A1D_NORET_mc<"ds_rsub_u64", VReg_64>;
430defm DS_INC_U64       : DS_1A1D_NORET_mc<"ds_inc_u64", VReg_64>;
431defm DS_DEC_U64       : DS_1A1D_NORET_mc<"ds_dec_u64", VReg_64>;
432defm DS_MIN_I64       : DS_1A1D_NORET_mc<"ds_min_i64", VReg_64>;
433defm DS_MAX_I64       : DS_1A1D_NORET_mc<"ds_max_i64", VReg_64>;
434defm DS_MIN_U64       : DS_1A1D_NORET_mc<"ds_min_u64", VReg_64>;
435defm DS_MAX_U64       : DS_1A1D_NORET_mc<"ds_max_u64", VReg_64>;
436defm DS_AND_B64       : DS_1A1D_NORET_mc<"ds_and_b64", VReg_64>;
437defm DS_OR_B64        : DS_1A1D_NORET_mc<"ds_or_b64", VReg_64>;
438defm DS_XOR_B64       : DS_1A1D_NORET_mc<"ds_xor_b64", VReg_64>;
439defm DS_MSKOR_B64     : DS_1A2D_NORET_mc<"ds_mskor_b64", VReg_64>;
440let mayLoad = 0 in {
441defm DS_WRITE_B64     : DS_1A1D_NORET_mc<"ds_write_b64", VReg_64>;
442defm DS_WRITE2_B64    : DS_1A2D_Off8_NORET_mc<"ds_write2_b64", VReg_64>;
443defm DS_WRITE2ST64_B64: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b64", VReg_64>;
444}
445defm DS_CMPST_B64     : DS_1A2D_NORET_mc<"ds_cmpst_b64", VReg_64>;
446defm DS_CMPST_F64     : DS_1A2D_NORET_mc<"ds_cmpst_f64", VReg_64>;
447defm DS_MIN_F64       : DS_1A1D_NORET_mc<"ds_min_f64", VReg_64>;
448defm DS_MAX_F64       : DS_1A1D_NORET_mc<"ds_max_f64", VReg_64>;
449
450defm DS_ADD_RTN_U32   : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
451
452let SubtargetPredicate = HasLDSFPAtomics in {
453defm DS_ADD_RTN_F32   : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32, "ds_add_f32">;
454}
455defm DS_SUB_RTN_U32   : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
456defm DS_RSUB_RTN_U32  : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
457defm DS_INC_RTN_U32   : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
458defm DS_DEC_RTN_U32   : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
459defm DS_MIN_RTN_I32   : DS_1A1D_RET_mc<"ds_min_rtn_i32", VGPR_32, "ds_min_i32">;
460defm DS_MAX_RTN_I32   : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
461defm DS_MIN_RTN_U32   : DS_1A1D_RET_mc<"ds_min_rtn_u32", VGPR_32, "ds_min_u32">;
462defm DS_MAX_RTN_U32   : DS_1A1D_RET_mc<"ds_max_rtn_u32", VGPR_32, "ds_max_u32">;
463defm DS_AND_RTN_B32   : DS_1A1D_RET_mc<"ds_and_rtn_b32", VGPR_32, "ds_and_b32">;
464defm DS_OR_RTN_B32    : DS_1A1D_RET_mc<"ds_or_rtn_b32", VGPR_32, "ds_or_b32">;
465defm DS_XOR_RTN_B32   : DS_1A1D_RET_mc<"ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">;
466defm DS_MSKOR_RTN_B32 : DS_1A2D_RET_mc<"ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">;
467defm DS_CMPST_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
468defm DS_CMPST_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
469defm DS_MIN_RTN_F32   : DS_1A1D_RET_mc<"ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
470defm DS_MAX_RTN_F32   : DS_1A1D_RET_mc<"ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
471
472defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b32">;
473defm DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>;
474defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>;
475
476defm DS_ADD_RTN_U64  : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64, "ds_add_u64">;
477defm DS_SUB_RTN_U64  : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
478defm DS_RSUB_RTN_U64  : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
479defm DS_INC_RTN_U64   : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
480defm DS_DEC_RTN_U64   : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
481defm DS_MIN_RTN_I64    : DS_1A1D_RET_mc<"ds_min_rtn_i64", VReg_64, "ds_min_i64">;
482defm DS_MAX_RTN_I64    : DS_1A1D_RET_mc<"ds_max_rtn_i64", VReg_64, "ds_max_i64">;
483defm DS_MIN_RTN_U64   : DS_1A1D_RET_mc<"ds_min_rtn_u64", VReg_64, "ds_min_u64">;
484defm DS_MAX_RTN_U64   : DS_1A1D_RET_mc<"ds_max_rtn_u64", VReg_64, "ds_max_u64">;
485defm DS_AND_RTN_B64    : DS_1A1D_RET_mc<"ds_and_rtn_b64", VReg_64, "ds_and_b64">;
486defm DS_OR_RTN_B64     : DS_1A1D_RET_mc<"ds_or_rtn_b64", VReg_64, "ds_or_b64">;
487defm DS_XOR_RTN_B64    : DS_1A1D_RET_mc<"ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
488defm DS_MSKOR_RTN_B64  : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
489defm DS_CMPST_RTN_B64  : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
490defm DS_CMPST_RTN_F64  : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
491defm DS_MIN_RTN_F64    : DS_1A1D_RET_mc<"ds_min_rtn_f64", VReg_64, "ds_min_f64">;
492defm DS_MAX_RTN_F64    : DS_1A1D_RET_mc<"ds_max_rtn_f64", VReg_64, "ds_max_f64">;
493
494defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", VReg_64>;
495defm DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>;
496defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>;
497
498let isConvergent = 1, usesCustomInserter = 1 in {
499def DS_GWS_INIT       : DS_GWS_1D<"ds_gws_init"> {
500  let mayLoad = 0;
501}
502def DS_GWS_SEMA_V     : DS_GWS_0D<"ds_gws_sema_v">;
503def DS_GWS_SEMA_BR    : DS_GWS_1D<"ds_gws_sema_br">;
504def DS_GWS_SEMA_P     : DS_GWS_0D<"ds_gws_sema_p">;
505def DS_GWS_BARRIER    : DS_GWS_1D<"ds_gws_barrier">;
506}
507
508let SubtargetPredicate = HasDsSrc2Insts in {
509def DS_ADD_SRC2_U32   : DS_1A<"ds_add_src2_u32">;
510def DS_SUB_SRC2_U32   : DS_1A<"ds_sub_src2_u32">;
511def DS_RSUB_SRC2_U32  : DS_1A<"ds_rsub_src2_u32">;
512def DS_INC_SRC2_U32   : DS_1A<"ds_inc_src2_u32">;
513def DS_DEC_SRC2_U32   : DS_1A<"ds_dec_src2_u32">;
514def DS_MIN_SRC2_I32   : DS_1A<"ds_min_src2_i32">;
515def DS_MAX_SRC2_I32   : DS_1A<"ds_max_src2_i32">;
516def DS_MIN_SRC2_U32   : DS_1A<"ds_min_src2_u32">;
517def DS_MAX_SRC2_U32   : DS_1A<"ds_max_src2_u32">;
518def DS_AND_SRC2_B32   : DS_1A<"ds_and_src2_b32">;
519def DS_OR_SRC2_B32    : DS_1A<"ds_or_src2_b32">;
520def DS_XOR_SRC2_B32   : DS_1A<"ds_xor_src2_b32">;
521def DS_MIN_SRC2_F32   : DS_1A<"ds_min_src2_f32">;
522def DS_MAX_SRC2_F32   : DS_1A<"ds_max_src2_f32">;
523
524def DS_ADD_SRC2_U64   : DS_1A<"ds_add_src2_u64">;
525def DS_SUB_SRC2_U64   : DS_1A<"ds_sub_src2_u64">;
526def DS_RSUB_SRC2_U64  : DS_1A<"ds_rsub_src2_u64">;
527def DS_INC_SRC2_U64   : DS_1A<"ds_inc_src2_u64">;
528def DS_DEC_SRC2_U64   : DS_1A<"ds_dec_src2_u64">;
529def DS_MIN_SRC2_I64   : DS_1A<"ds_min_src2_i64">;
530def DS_MAX_SRC2_I64   : DS_1A<"ds_max_src2_i64">;
531def DS_MIN_SRC2_U64   : DS_1A<"ds_min_src2_u64">;
532def DS_MAX_SRC2_U64   : DS_1A<"ds_max_src2_u64">;
533def DS_AND_SRC2_B64   : DS_1A<"ds_and_src2_b64">;
534def DS_OR_SRC2_B64    : DS_1A<"ds_or_src2_b64">;
535def DS_XOR_SRC2_B64   : DS_1A<"ds_xor_src2_b64">;
536def DS_MIN_SRC2_F64   : DS_1A<"ds_min_src2_f64">;
537def DS_MAX_SRC2_F64   : DS_1A<"ds_max_src2_f64">;
538
539def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">;
540def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
541} // End SubtargetPredicate = HasDsSrc2Insts
542
543let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
544def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>;
545}
546
547let mayStore = 0 in {
548defm DS_READ_I8      : DS_1A_RET_mc<"ds_read_i8">;
549defm DS_READ_U8      : DS_1A_RET_mc<"ds_read_u8">;
550defm DS_READ_I16     : DS_1A_RET_mc<"ds_read_i16">;
551defm DS_READ_U16     : DS_1A_RET_mc<"ds_read_u16">;
552defm DS_READ_B32     : DS_1A_RET_mc<"ds_read_b32">;
553defm DS_READ_B64     : DS_1A_RET_mc<"ds_read_b64", VReg_64>;
554
555defm DS_READ2_B32    : DS_1A_Off8_RET_mc<"ds_read2_b32", VReg_64>;
556defm DS_READ2ST64_B32: DS_1A_Off8_RET_mc<"ds_read2st64_b32", VReg_64>;
557
558defm DS_READ2_B64    : DS_1A_Off8_RET_mc<"ds_read2_b64", VReg_128>;
559defm DS_READ2ST64_B64: DS_1A_Off8_RET_mc<"ds_read2st64_b64", VReg_128>;
560
561let has_m0_read = 0 in {
562let SubtargetPredicate = HasD16LoadStore in {
563def DS_READ_U8_D16     : DS_1A_RET_Tied<"ds_read_u8_d16">;
564def DS_READ_U8_D16_HI  : DS_1A_RET_Tied<"ds_read_u8_d16_hi">;
565def DS_READ_I8_D16     : DS_1A_RET_Tied<"ds_read_i8_d16">;
566def DS_READ_I8_D16_HI  : DS_1A_RET_Tied<"ds_read_i8_d16_hi">;
567def DS_READ_U16_D16    : DS_1A_RET_Tied<"ds_read_u16_d16">;
568def DS_READ_U16_D16_HI : DS_1A_RET_Tied<"ds_read_u16_d16_hi">;
569}
570} // End has_m0_read = 0
571
572let SubtargetPredicate = HasDSAddTid in {
573def DS_READ_ADDTID_B32 : DS_0A_RET<"ds_read_addtid_b32">;
574}
575
576} // End mayStore = 0
577
578def DS_CONSUME       : DS_0A_RET<"ds_consume">;
579def DS_APPEND        : DS_0A_RET<"ds_append">;
580def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
581
582//===----------------------------------------------------------------------===//
583// Instruction definitions for CI and newer.
584//===----------------------------------------------------------------------===//
585
586let SubtargetPredicate = isGFX7Plus in {
587
588defm DS_WRAP_RTN_B32 : DS_1A2D_RET_mc<"ds_wrap_rtn_b32", VGPR_32>;
589defm DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET_mc<"ds_condxchg32_rtn_b64", VReg_64>;
590
591let isConvergent = 1, usesCustomInserter = 1 in {
592def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
593}
594
595let mayStore = 0 in {
596defm DS_READ_B96 : DS_1A_RET_mc<"ds_read_b96", VReg_96>;
597defm DS_READ_B128: DS_1A_RET_mc<"ds_read_b128", VReg_128>;
598} // End mayStore = 0
599
600let mayLoad = 0 in {
601defm DS_WRITE_B96 : DS_1A1D_NORET_mc<"ds_write_b96", VReg_96>;
602defm DS_WRITE_B128 : DS_1A1D_NORET_mc<"ds_write_b128", VReg_128>;
603} // End mayLoad = 0
604
605def DS_NOP : DS_VOID<"ds_nop">;
606
607} // let SubtargetPredicate = isGFX7Plus
608
609//===----------------------------------------------------------------------===//
610// Instruction definitions for VI and newer.
611//===----------------------------------------------------------------------===//
612
613let SubtargetPredicate = isGFX8Plus in {
614
615let Uses = [EXEC] in {
616def DS_PERMUTE_B32  : DS_1A1D_PERMUTE <"ds_permute_b32",
617                                       int_amdgcn_ds_permute>;
618def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
619                                       int_amdgcn_ds_bpermute>;
620}
621
622} // let SubtargetPredicate = isGFX8Plus
623
624let SubtargetPredicate = HasLDSFPAtomics, OtherPredicates = [HasDsSrc2Insts] in {
625def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
626}
627
628//===----------------------------------------------------------------------===//
629// DS Patterns
630//===----------------------------------------------------------------------===//
631
632def : GCNPat <
633  (int_amdgcn_ds_swizzle i32:$src, timm:$offset16),
634  (DS_SWIZZLE_B32 VGPR_32:$src, (as_i16timm $offset16), (i1 0))
635>;
636
637class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
638  (vt (frag (DS1Addr1Offset i32:$ptr, i16:$offset))),
639  (inst $ptr, offset:$offset, (i1 gds))
640>;
641
642multiclass DSReadPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
643
644  let OtherPredicates = [LDSRequiresM0Init] in {
645    def : DSReadPat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
646  }
647
648  let OtherPredicates = [NotLDSRequiresM0Init] in {
649    def : DSReadPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
650  }
651}
652
653class DSReadPat_D16 <DS_Pseudo inst, PatFrag frag, ValueType vt> : GCNPat <
654  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$in),
655  (inst $ptr, offset:$offset, (i1 0), $in)
656>;
657
658defm : DSReadPat_mc <DS_READ_I8, i32, "sextloadi8_local">;
659defm : DSReadPat_mc <DS_READ_I8,  i16, "sextloadi8_local">;
660defm : DSReadPat_mc <DS_READ_U8,  i32, "extloadi8_local">;
661defm : DSReadPat_mc <DS_READ_U8,  i32, "zextloadi8_local">;
662defm : DSReadPat_mc <DS_READ_U8,  i16, "extloadi8_local">;
663defm : DSReadPat_mc <DS_READ_U8,  i16, "zextloadi8_local">;
664defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
665defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
666defm : DSReadPat_mc <DS_READ_U16, i32, "extloadi16_local">;
667defm : DSReadPat_mc <DS_READ_U16, i32, "zextloadi16_local">;
668defm : DSReadPat_mc <DS_READ_U16, i16, "load_local">;
669
670foreach vt = Reg32Types.types in {
671defm : DSReadPat_mc <DS_READ_B32, vt, "load_local">;
672}
673
674defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_32_local">;
675defm : DSReadPat_mc <DS_READ_B64, i64, "atomic_load_64_local">;
676
677let AddedComplexity = 100 in {
678
679foreach vt = VReg_64.RegTypes in {
680defm : DSReadPat_mc <DS_READ_B64, vt, "load_align8_local">;
681}
682
683defm : DSReadPat_mc <DS_READ_B128, v4i32, "load_align16_local">;
684
685} // End AddedComplexity = 100
686
687let OtherPredicates = [D16PreservesUnusedBits] in {
688def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2i16>;
689def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2f16>;
690def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2i16>;
691def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2f16>;
692def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2i16>;
693def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2f16>;
694
695def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2i16>;
696def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2f16>;
697def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2i16>;
698def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2f16>;
699def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2i16>;
700def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2f16>;
701}
702
703class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
704  (frag vt:$value, (DS1Addr1Offset i32:$ptr, i16:$offset)),
705  (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))
706>;
707
708multiclass DSWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
709  let OtherPredicates = [LDSRequiresM0Init] in {
710    def : DSWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
711  }
712
713  let OtherPredicates = [NotLDSRequiresM0Init] in {
714    def : DSWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
715  }
716}
717
718// Irritatingly, atomic_store reverses the order of operands from a
719// normal store.
720class DSAtomicWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
721  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$value),
722  (inst $ptr, $value, offset:$offset, (i1 0))
723>;
724
725multiclass DSAtomicWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
726  let OtherPredicates = [LDSRequiresM0Init] in {
727    def : DSAtomicWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
728  }
729
730  let OtherPredicates = [NotLDSRequiresM0Init] in {
731    def : DSAtomicWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
732  }
733}
734
735defm : DSWritePat_mc <DS_WRITE_B8, i32, "truncstorei8_local">;
736defm : DSWritePat_mc <DS_WRITE_B16, i32, "truncstorei16_local">;
737defm : DSWritePat_mc <DS_WRITE_B8, i16, "truncstorei8_local">;
738defm : DSWritePat_mc <DS_WRITE_B16, i16, "store_local">;
739
740foreach vt = Reg32Types.types in {
741defm : DSWritePat_mc <DS_WRITE_B32, vt, "store_local">;
742}
743
744defm : DSAtomicWritePat_mc <DS_WRITE_B32, i32, "atomic_store_local_32">;
745defm : DSAtomicWritePat_mc <DS_WRITE_B64, i64, "atomic_store_local_64">;
746
747let OtherPredicates = [D16PreservesUnusedBits] in {
748def : DSWritePat <DS_WRITE_B16_D16_HI, i32, store_hi16_local>;
749def : DSWritePat <DS_WRITE_B8_D16_HI, i32, truncstorei8_hi16_local>;
750}
751
752class DS64Bit4ByteAlignedReadPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
753  (vt:$value (frag (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))),
754  (inst $ptr, $offset0, $offset1, (i1 0))
755>;
756
757class DS64Bit4ByteAlignedWritePat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat<
758  (frag vt:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1)),
759  (inst $ptr, (i32 (EXTRACT_SUBREG VReg_64:$value, sub0)),
760              (i32 (EXTRACT_SUBREG VReg_64:$value, sub1)), $offset0, $offset1,
761              (i1 0))
762>;
763
764multiclass DS64Bit4ByteAlignedPat_mc<ValueType vt> {
765  let OtherPredicates = [LDSRequiresM0Init, isGFX7Plus] in {
766    def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32, vt, load_local_m0>;
767    def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32, vt, store_local_m0>;
768  }
769
770  let OtherPredicates = [NotLDSRequiresM0Init] in {
771    def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32_gfx9, vt, load_local>;
772    def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32_gfx9, vt, store_local>;
773  }
774}
775
776// v2i32 loads are split into i32 loads on SI during lowering, due to a bug
777// related to bounds checking.
778foreach vt = VReg_64.RegTypes in {
779defm : DS64Bit4ByteAlignedPat_mc<vt>;
780}
781
782let AddedComplexity = 100 in {
783
784foreach vt = VReg_64.RegTypes in {
785defm : DSWritePat_mc <DS_WRITE_B64, vt, "store_align8_local">;
786}
787
788defm : DSWritePat_mc <DS_WRITE_B128, v4i32, "store_align16_local">;
789
790} // End AddedComplexity = 100
791class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
792  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$value),
793  (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))
794>;
795
796multiclass DSAtomicRetPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
797  let OtherPredicates = [LDSRequiresM0Init] in {
798    def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_local_m0_"#vt.Size)>;
799  }
800
801  let OtherPredicates = [NotLDSRequiresM0Init] in {
802    def : DSAtomicRetPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
803                         !cast<PatFrag>(frag#"_local_"#vt.Size)>;
804  }
805
806  def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_region_m0_"#vt.Size), 1>;
807}
808
809
810
811class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
812  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$cmp, vt:$swap),
813  (inst $ptr, getVregSrcForVT<vt>.ret:$cmp, getVregSrcForVT<vt>.ret:$swap, offset:$offset, (i1 gds))
814>;
815
816multiclass DSAtomicCmpXChg_mc<DS_Pseudo inst, ValueType vt, string frag> {
817  let OtherPredicates = [LDSRequiresM0Init] in {
818    def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_local_m0_"#vt.Size)>;
819  }
820
821  let OtherPredicates = [NotLDSRequiresM0Init] in {
822    def : DSAtomicCmpXChg<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
823                          !cast<PatFrag>(frag#"_local_"#vt.Size)>;
824  }
825
826  def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_region_m0_"#vt.Size), 1>;
827}
828
829
830
831// 32-bit atomics.
832defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B32, i32, "atomic_swap">;
833defm : DSAtomicRetPat_mc<DS_ADD_RTN_U32, i32, "atomic_load_add">;
834defm : DSAtomicRetPat_mc<DS_SUB_RTN_U32, i32, "atomic_load_sub">;
835defm : DSAtomicRetPat_mc<DS_INC_RTN_U32, i32, "atomic_inc">;
836defm : DSAtomicRetPat_mc<DS_DEC_RTN_U32, i32, "atomic_dec">;
837defm : DSAtomicRetPat_mc<DS_AND_RTN_B32, i32, "atomic_load_and">;
838defm : DSAtomicRetPat_mc<DS_OR_RTN_B32, i32, "atomic_load_or">;
839defm : DSAtomicRetPat_mc<DS_XOR_RTN_B32, i32, "atomic_load_xor">;
840defm : DSAtomicRetPat_mc<DS_MIN_RTN_I32, i32, "atomic_load_min">;
841defm : DSAtomicRetPat_mc<DS_MAX_RTN_I32, i32, "atomic_load_max">;
842defm : DSAtomicRetPat_mc<DS_MIN_RTN_U32, i32, "atomic_load_umin">;
843defm : DSAtomicRetPat_mc<DS_MAX_RTN_U32, i32, "atomic_load_umax">;
844defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B32, i32, "atomic_cmp_swap">;
845
846let SubtargetPredicate = HasLDSFPAtomics in {
847defm : DSAtomicRetPat_mc<DS_MIN_RTN_F32, f32, "atomic_load_fmin">;
848defm : DSAtomicRetPat_mc<DS_MAX_RTN_F32, f32, "atomic_load_fmax">;
849defm : DSAtomicRetPat_mc<DS_ADD_RTN_F32, f32, "atomic_load_fadd">;
850}
851
852// 64-bit atomics.
853defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B64, i64, "atomic_swap">;
854defm : DSAtomicRetPat_mc<DS_ADD_RTN_U64, i64, "atomic_load_add">;
855defm : DSAtomicRetPat_mc<DS_SUB_RTN_U64, i64, "atomic_load_sub">;
856defm : DSAtomicRetPat_mc<DS_INC_RTN_U64, i64, "atomic_inc">;
857defm : DSAtomicRetPat_mc<DS_DEC_RTN_U64, i64, "atomic_dec">;
858defm : DSAtomicRetPat_mc<DS_AND_RTN_B64, i64, "atomic_load_and">;
859defm : DSAtomicRetPat_mc<DS_OR_RTN_B64, i64, "atomic_load_or">;
860defm : DSAtomicRetPat_mc<DS_XOR_RTN_B64, i64, "atomic_load_xor">;
861defm : DSAtomicRetPat_mc<DS_MIN_RTN_I64, i64, "atomic_load_min">;
862defm : DSAtomicRetPat_mc<DS_MAX_RTN_I64, i64, "atomic_load_max">;
863defm : DSAtomicRetPat_mc<DS_MIN_RTN_U64, i64, "atomic_load_umin">;
864defm : DSAtomicRetPat_mc<DS_MAX_RTN_U64, i64, "atomic_load_umax">;
865
866defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B64, i64, "atomic_cmp_swap">;
867
868def : Pat <
869  (SIds_ordered_count i32:$value, i16:$offset),
870  (DS_ORDERED_COUNT $value, (as_i16imm $offset))
871>;
872
873//===----------------------------------------------------------------------===//
874// Target-specific instruction encodings.
875//===----------------------------------------------------------------------===//
876
877//===----------------------------------------------------------------------===//
878// Base ENC_DS for GFX6, GFX7, GFX10.
879//===----------------------------------------------------------------------===//
880
881class Base_DS_Real_gfx6_gfx7_gfx10<bits<8> op, DS_Pseudo ps, int ef> :
882    DS_Real<ps>, SIMCInstr <ps.Mnemonic, ef> {
883
884  let Inst{7-0}   = !if(ps.has_offset0, offset0, 0);
885  let Inst{15-8}  = !if(ps.has_offset1, offset1, 0);
886  let Inst{17}    = !if(ps.has_gds, gds, ps.gdsValue);
887  let Inst{25-18} = op;
888  let Inst{31-26} = 0x36;
889  let Inst{39-32} = !if(ps.has_addr, addr, !if(ps.has_gws_data0, data0, 0));
890  let Inst{47-40} = !if(ps.has_data0, data0, 0);
891  let Inst{55-48} = !if(ps.has_data1, data1, 0);
892  let Inst{63-56} = !if(ps.has_vdst, vdst, 0);
893}
894
895//===----------------------------------------------------------------------===//
896// GFX10.
897//===----------------------------------------------------------------------===//
898
899let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
900  multiclass DS_Real_gfx10<bits<8> op>  {
901    def _gfx10 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
902                                              SIEncodingFamily.GFX10>;
903  }
904} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
905
906defm DS_ADD_F32          : DS_Real_gfx10<0x015>;
907defm DS_ADD_RTN_F32      : DS_Real_gfx10<0x055>;
908defm DS_ADD_SRC2_F32     : DS_Real_gfx10<0x095>;
909defm DS_WRITE_B8_D16_HI  : DS_Real_gfx10<0x0a0>;
910defm DS_WRITE_B16_D16_HI : DS_Real_gfx10<0x0a1>;
911defm DS_READ_U8_D16      : DS_Real_gfx10<0x0a2>;
912defm DS_READ_U8_D16_HI   : DS_Real_gfx10<0x0a3>;
913defm DS_READ_I8_D16      : DS_Real_gfx10<0x0a4>;
914defm DS_READ_I8_D16_HI   : DS_Real_gfx10<0x0a5>;
915defm DS_READ_U16_D16     : DS_Real_gfx10<0x0a6>;
916defm DS_READ_U16_D16_HI  : DS_Real_gfx10<0x0a7>;
917defm DS_WRITE_ADDTID_B32 : DS_Real_gfx10<0x0b0>;
918defm DS_READ_ADDTID_B32  : DS_Real_gfx10<0x0b1>;
919defm DS_PERMUTE_B32      : DS_Real_gfx10<0x0b2>;
920defm DS_BPERMUTE_B32     : DS_Real_gfx10<0x0b3>;
921
922//===----------------------------------------------------------------------===//
923// GFX7, GFX10.
924//===----------------------------------------------------------------------===//
925
926let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {
927  multiclass DS_Real_gfx7<bits<8> op> {
928    def _gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
929                                             SIEncodingFamily.SI>;
930  }
931} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7"
932
933multiclass DS_Real_gfx7_gfx10<bits<8> op> :
934  DS_Real_gfx7<op>, DS_Real_gfx10<op>;
935
936// FIXME-GFX7: Add tests when upstreaming this part.
937defm DS_GWS_SEMA_RELEASE_ALL : DS_Real_gfx7_gfx10<0x018>;
938defm DS_WRAP_RTN_B32         : DS_Real_gfx7_gfx10<0x034>;
939defm DS_CONDXCHG32_RTN_B64   : DS_Real_gfx7_gfx10<0x07e>;
940defm DS_WRITE_B96            : DS_Real_gfx7_gfx10<0x0de>;
941defm DS_WRITE_B128           : DS_Real_gfx7_gfx10<0x0df>;
942defm DS_READ_B96             : DS_Real_gfx7_gfx10<0x0fe>;
943defm DS_READ_B128            : DS_Real_gfx7_gfx10<0x0ff>;
944
945//===----------------------------------------------------------------------===//
946// GFX6, GFX7, GFX10.
947//===----------------------------------------------------------------------===//
948
949let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
950  multiclass DS_Real_gfx6_gfx7<bits<8> op> {
951    def _gfx6_gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
952                                                  SIEncodingFamily.SI>;
953  }
954} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
955
956multiclass DS_Real_gfx6_gfx7_gfx10<bits<8> op> :
957  DS_Real_gfx6_gfx7<op>, DS_Real_gfx10<op>;
958
959defm DS_ADD_U32             : DS_Real_gfx6_gfx7_gfx10<0x000>;
960defm DS_SUB_U32             : DS_Real_gfx6_gfx7_gfx10<0x001>;
961defm DS_RSUB_U32            : DS_Real_gfx6_gfx7_gfx10<0x002>;
962defm DS_INC_U32             : DS_Real_gfx6_gfx7_gfx10<0x003>;
963defm DS_DEC_U32             : DS_Real_gfx6_gfx7_gfx10<0x004>;
964defm DS_MIN_I32             : DS_Real_gfx6_gfx7_gfx10<0x005>;
965defm DS_MAX_I32             : DS_Real_gfx6_gfx7_gfx10<0x006>;
966defm DS_MIN_U32             : DS_Real_gfx6_gfx7_gfx10<0x007>;
967defm DS_MAX_U32             : DS_Real_gfx6_gfx7_gfx10<0x008>;
968defm DS_AND_B32             : DS_Real_gfx6_gfx7_gfx10<0x009>;
969defm DS_OR_B32              : DS_Real_gfx6_gfx7_gfx10<0x00a>;
970defm DS_XOR_B32             : DS_Real_gfx6_gfx7_gfx10<0x00b>;
971defm DS_MSKOR_B32           : DS_Real_gfx6_gfx7_gfx10<0x00c>;
972defm DS_WRITE_B32           : DS_Real_gfx6_gfx7_gfx10<0x00d>;
973defm DS_WRITE2_B32          : DS_Real_gfx6_gfx7_gfx10<0x00e>;
974defm DS_WRITE2ST64_B32      : DS_Real_gfx6_gfx7_gfx10<0x00f>;
975defm DS_CMPST_B32           : DS_Real_gfx6_gfx7_gfx10<0x010>;
976defm DS_CMPST_F32           : DS_Real_gfx6_gfx7_gfx10<0x011>;
977defm DS_MIN_F32             : DS_Real_gfx6_gfx7_gfx10<0x012>;
978defm DS_MAX_F32             : DS_Real_gfx6_gfx7_gfx10<0x013>;
979defm DS_NOP                 : DS_Real_gfx6_gfx7_gfx10<0x014>;
980defm DS_GWS_INIT            : DS_Real_gfx6_gfx7_gfx10<0x019>;
981defm DS_GWS_SEMA_V          : DS_Real_gfx6_gfx7_gfx10<0x01a>;
982defm DS_GWS_SEMA_BR         : DS_Real_gfx6_gfx7_gfx10<0x01b>;
983defm DS_GWS_SEMA_P          : DS_Real_gfx6_gfx7_gfx10<0x01c>;
984defm DS_GWS_BARRIER         : DS_Real_gfx6_gfx7_gfx10<0x01d>;
985defm DS_WRITE_B8            : DS_Real_gfx6_gfx7_gfx10<0x01e>;
986defm DS_WRITE_B16           : DS_Real_gfx6_gfx7_gfx10<0x01f>;
987defm DS_ADD_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x020>;
988defm DS_SUB_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x021>;
989defm DS_RSUB_RTN_U32        : DS_Real_gfx6_gfx7_gfx10<0x022>;
990defm DS_INC_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x023>;
991defm DS_DEC_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x024>;
992defm DS_MIN_RTN_I32         : DS_Real_gfx6_gfx7_gfx10<0x025>;
993defm DS_MAX_RTN_I32         : DS_Real_gfx6_gfx7_gfx10<0x026>;
994defm DS_MIN_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x027>;
995defm DS_MAX_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x028>;
996defm DS_AND_RTN_B32         : DS_Real_gfx6_gfx7_gfx10<0x029>;
997defm DS_OR_RTN_B32          : DS_Real_gfx6_gfx7_gfx10<0x02a>;
998defm DS_XOR_RTN_B32         : DS_Real_gfx6_gfx7_gfx10<0x02b>;
999defm DS_MSKOR_RTN_B32       : DS_Real_gfx6_gfx7_gfx10<0x02c>;
1000defm DS_WRXCHG_RTN_B32      : DS_Real_gfx6_gfx7_gfx10<0x02d>;
1001defm DS_WRXCHG2_RTN_B32     : DS_Real_gfx6_gfx7_gfx10<0x02e>;
1002defm DS_WRXCHG2ST64_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02f>;
1003defm DS_CMPST_RTN_B32       : DS_Real_gfx6_gfx7_gfx10<0x030>;
1004defm DS_CMPST_RTN_F32       : DS_Real_gfx6_gfx7_gfx10<0x031>;
1005defm DS_MIN_RTN_F32         : DS_Real_gfx6_gfx7_gfx10<0x032>;
1006defm DS_MAX_RTN_F32         : DS_Real_gfx6_gfx7_gfx10<0x033>;
1007defm DS_SWIZZLE_B32         : DS_Real_gfx6_gfx7_gfx10<0x035>;
1008defm DS_READ_B32            : DS_Real_gfx6_gfx7_gfx10<0x036>;
1009defm DS_READ2_B32           : DS_Real_gfx6_gfx7_gfx10<0x037>;
1010defm DS_READ2ST64_B32       : DS_Real_gfx6_gfx7_gfx10<0x038>;
1011defm DS_READ_I8             : DS_Real_gfx6_gfx7_gfx10<0x039>;
1012defm DS_READ_U8             : DS_Real_gfx6_gfx7_gfx10<0x03a>;
1013defm DS_READ_I16            : DS_Real_gfx6_gfx7_gfx10<0x03b>;
1014defm DS_READ_U16            : DS_Real_gfx6_gfx7_gfx10<0x03c>;
1015defm DS_CONSUME             : DS_Real_gfx6_gfx7_gfx10<0x03d>;
1016defm DS_APPEND              : DS_Real_gfx6_gfx7_gfx10<0x03e>;
1017defm DS_ORDERED_COUNT       : DS_Real_gfx6_gfx7_gfx10<0x03f>;
1018defm DS_ADD_U64             : DS_Real_gfx6_gfx7_gfx10<0x040>;
1019defm DS_SUB_U64             : DS_Real_gfx6_gfx7_gfx10<0x041>;
1020defm DS_RSUB_U64            : DS_Real_gfx6_gfx7_gfx10<0x042>;
1021defm DS_INC_U64             : DS_Real_gfx6_gfx7_gfx10<0x043>;
1022defm DS_DEC_U64             : DS_Real_gfx6_gfx7_gfx10<0x044>;
1023defm DS_MIN_I64             : DS_Real_gfx6_gfx7_gfx10<0x045>;
1024defm DS_MAX_I64             : DS_Real_gfx6_gfx7_gfx10<0x046>;
1025defm DS_MIN_U64             : DS_Real_gfx6_gfx7_gfx10<0x047>;
1026defm DS_MAX_U64             : DS_Real_gfx6_gfx7_gfx10<0x048>;
1027defm DS_AND_B64             : DS_Real_gfx6_gfx7_gfx10<0x049>;
1028defm DS_OR_B64              : DS_Real_gfx6_gfx7_gfx10<0x04a>;
1029defm DS_XOR_B64             : DS_Real_gfx6_gfx7_gfx10<0x04b>;
1030defm DS_MSKOR_B64           : DS_Real_gfx6_gfx7_gfx10<0x04c>;
1031defm DS_WRITE_B64           : DS_Real_gfx6_gfx7_gfx10<0x04d>;
1032defm DS_WRITE2_B64          : DS_Real_gfx6_gfx7_gfx10<0x04e>;
1033defm DS_WRITE2ST64_B64      : DS_Real_gfx6_gfx7_gfx10<0x04f>;
1034defm DS_CMPST_B64           : DS_Real_gfx6_gfx7_gfx10<0x050>;
1035defm DS_CMPST_F64           : DS_Real_gfx6_gfx7_gfx10<0x051>;
1036defm DS_MIN_F64             : DS_Real_gfx6_gfx7_gfx10<0x052>;
1037defm DS_MAX_F64             : DS_Real_gfx6_gfx7_gfx10<0x053>;
1038defm DS_ADD_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x060>;
1039defm DS_SUB_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x061>;
1040defm DS_RSUB_RTN_U64        : DS_Real_gfx6_gfx7_gfx10<0x062>;
1041defm DS_INC_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x063>;
1042defm DS_DEC_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x064>;
1043defm DS_MIN_RTN_I64         : DS_Real_gfx6_gfx7_gfx10<0x065>;
1044defm DS_MAX_RTN_I64         : DS_Real_gfx6_gfx7_gfx10<0x066>;
1045defm DS_MIN_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x067>;
1046defm DS_MAX_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x068>;
1047defm DS_AND_RTN_B64         : DS_Real_gfx6_gfx7_gfx10<0x069>;
1048defm DS_OR_RTN_B64          : DS_Real_gfx6_gfx7_gfx10<0x06a>;
1049defm DS_XOR_RTN_B64         : DS_Real_gfx6_gfx7_gfx10<0x06b>;
1050defm DS_MSKOR_RTN_B64       : DS_Real_gfx6_gfx7_gfx10<0x06c>;
1051defm DS_WRXCHG_RTN_B64      : DS_Real_gfx6_gfx7_gfx10<0x06d>;
1052defm DS_WRXCHG2_RTN_B64     : DS_Real_gfx6_gfx7_gfx10<0x06e>;
1053defm DS_WRXCHG2ST64_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06f>;
1054defm DS_CMPST_RTN_B64       : DS_Real_gfx6_gfx7_gfx10<0x070>;
1055defm DS_CMPST_RTN_F64       : DS_Real_gfx6_gfx7_gfx10<0x071>;
1056defm DS_MIN_RTN_F64         : DS_Real_gfx6_gfx7_gfx10<0x072>;
1057defm DS_MAX_RTN_F64         : DS_Real_gfx6_gfx7_gfx10<0x073>;
1058defm DS_READ_B64            : DS_Real_gfx6_gfx7_gfx10<0x076>;
1059defm DS_READ2_B64           : DS_Real_gfx6_gfx7_gfx10<0x077>;
1060defm DS_READ2ST64_B64       : DS_Real_gfx6_gfx7_gfx10<0x078>;
1061defm DS_ADD_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x080>;
1062defm DS_SUB_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x081>;
1063defm DS_RSUB_SRC2_U32       : DS_Real_gfx6_gfx7_gfx10<0x082>;
1064defm DS_INC_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x083>;
1065defm DS_DEC_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x084>;
1066defm DS_MIN_SRC2_I32        : DS_Real_gfx6_gfx7_gfx10<0x085>;
1067defm DS_MAX_SRC2_I32        : DS_Real_gfx6_gfx7_gfx10<0x086>;
1068defm DS_MIN_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x087>;
1069defm DS_MAX_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x088>;
1070defm DS_AND_SRC2_B32        : DS_Real_gfx6_gfx7_gfx10<0x089>;
1071defm DS_OR_SRC2_B32         : DS_Real_gfx6_gfx7_gfx10<0x08a>;
1072defm DS_XOR_SRC2_B32        : DS_Real_gfx6_gfx7_gfx10<0x08b>;
1073defm DS_WRITE_SRC2_B32      : DS_Real_gfx6_gfx7_gfx10<0x08d>;
1074defm DS_MIN_SRC2_F32        : DS_Real_gfx6_gfx7_gfx10<0x092>;
1075defm DS_MAX_SRC2_F32        : DS_Real_gfx6_gfx7_gfx10<0x093>;
1076defm DS_ADD_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c0>;
1077defm DS_SUB_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c1>;
1078defm DS_RSUB_SRC2_U64       : DS_Real_gfx6_gfx7_gfx10<0x0c2>;
1079defm DS_INC_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c3>;
1080defm DS_DEC_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c4>;
1081defm DS_MIN_SRC2_I64        : DS_Real_gfx6_gfx7_gfx10<0x0c5>;
1082defm DS_MAX_SRC2_I64        : DS_Real_gfx6_gfx7_gfx10<0x0c6>;
1083defm DS_MIN_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c7>;
1084defm DS_MAX_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c8>;
1085defm DS_AND_SRC2_B64        : DS_Real_gfx6_gfx7_gfx10<0x0c9>;
1086defm DS_OR_SRC2_B64         : DS_Real_gfx6_gfx7_gfx10<0x0ca>;
1087defm DS_XOR_SRC2_B64        : DS_Real_gfx6_gfx7_gfx10<0x0cb>;
1088defm DS_WRITE_SRC2_B64      : DS_Real_gfx6_gfx7_gfx10<0x0cd>;
1089defm DS_MIN_SRC2_F64        : DS_Real_gfx6_gfx7_gfx10<0x0d2>;
1090defm DS_MAX_SRC2_F64        : DS_Real_gfx6_gfx7_gfx10<0x0d3>;
1091
1092//===----------------------------------------------------------------------===//
1093// GFX8, GFX9 (VI).
1094//===----------------------------------------------------------------------===//
1095
1096class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
1097  DS_Real <ds>,
1098  SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
1099  let AssemblerPredicate = isGFX8GFX9;
1100  let DecoderNamespace = "GFX8";
1101
1102  // encoding
1103  let Inst{7-0}   = !if(ds.has_offset0, offset0, 0);
1104  let Inst{15-8}  = !if(ds.has_offset1, offset1, 0);
1105  let Inst{16}    = !if(ds.has_gds, gds, ds.gdsValue);
1106  let Inst{24-17} = op;
1107  let Inst{31-26} = 0x36; // ds prefix
1108  let Inst{39-32} = !if(ds.has_addr, addr, !if(ds.has_gws_data0, data0, 0));
1109  let Inst{47-40} = !if(ds.has_data0, data0, 0);
1110  let Inst{55-48} = !if(ds.has_data1, data1, 0);
1111  let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
1112}
1113
1114def DS_ADD_U32_vi         : DS_Real_vi<0x0,  DS_ADD_U32>;
1115def DS_SUB_U32_vi         : DS_Real_vi<0x1,  DS_SUB_U32>;
1116def DS_RSUB_U32_vi        : DS_Real_vi<0x2,  DS_RSUB_U32>;
1117def DS_INC_U32_vi         : DS_Real_vi<0x3,  DS_INC_U32>;
1118def DS_DEC_U32_vi         : DS_Real_vi<0x4,  DS_DEC_U32>;
1119def DS_MIN_I32_vi         : DS_Real_vi<0x5,  DS_MIN_I32>;
1120def DS_MAX_I32_vi         : DS_Real_vi<0x6,  DS_MAX_I32>;
1121def DS_MIN_U32_vi         : DS_Real_vi<0x7,  DS_MIN_U32>;
1122def DS_MAX_U32_vi         : DS_Real_vi<0x8,  DS_MAX_U32>;
1123def DS_AND_B32_vi         : DS_Real_vi<0x9,  DS_AND_B32>;
1124def DS_OR_B32_vi          : DS_Real_vi<0xa,  DS_OR_B32>;
1125def DS_XOR_B32_vi         : DS_Real_vi<0xb,  DS_XOR_B32>;
1126def DS_MSKOR_B32_vi       : DS_Real_vi<0xc,  DS_MSKOR_B32>;
1127def DS_WRITE_B32_vi       : DS_Real_vi<0xd,  DS_WRITE_B32>;
1128def DS_WRITE2_B32_vi      : DS_Real_vi<0xe,  DS_WRITE2_B32>;
1129def DS_WRITE2ST64_B32_vi  : DS_Real_vi<0xf,  DS_WRITE2ST64_B32>;
1130def DS_CMPST_B32_vi       : DS_Real_vi<0x10, DS_CMPST_B32>;
1131def DS_CMPST_F32_vi       : DS_Real_vi<0x11, DS_CMPST_F32>;
1132def DS_MIN_F32_vi         : DS_Real_vi<0x12, DS_MIN_F32>;
1133def DS_MAX_F32_vi         : DS_Real_vi<0x13, DS_MAX_F32>;
1134def DS_NOP_vi             : DS_Real_vi<0x14, DS_NOP>;
1135def DS_ADD_F32_vi         : DS_Real_vi<0x15, DS_ADD_F32>;
1136def DS_GWS_INIT_vi        : DS_Real_vi<0x99, DS_GWS_INIT>;
1137def DS_GWS_SEMA_V_vi      : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
1138def DS_GWS_SEMA_BR_vi     : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
1139def DS_GWS_SEMA_P_vi      : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
1140def DS_GWS_BARRIER_vi     : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
1141def DS_WRITE_ADDTID_B32_vi : DS_Real_vi<0x1d, DS_WRITE_ADDTID_B32>;
1142def DS_WRITE_B8_vi        : DS_Real_vi<0x1e, DS_WRITE_B8>;
1143def DS_WRITE_B16_vi       : DS_Real_vi<0x1f, DS_WRITE_B16>;
1144def DS_ADD_RTN_U32_vi     : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
1145def DS_SUB_RTN_U32_vi     : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
1146def DS_RSUB_RTN_U32_vi    : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
1147def DS_INC_RTN_U32_vi     : DS_Real_vi<0x23, DS_INC_RTN_U32>;
1148def DS_DEC_RTN_U32_vi     : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
1149def DS_MIN_RTN_I32_vi     : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
1150def DS_MAX_RTN_I32_vi     : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
1151def DS_MIN_RTN_U32_vi     : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
1152def DS_MAX_RTN_U32_vi     : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
1153def DS_AND_RTN_B32_vi     : DS_Real_vi<0x29, DS_AND_RTN_B32>;
1154def DS_OR_RTN_B32_vi      : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
1155def DS_XOR_RTN_B32_vi     : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
1156def DS_MSKOR_RTN_B32_vi   : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
1157def DS_WRXCHG_RTN_B32_vi  : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
1158def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
1159def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
1160def DS_CMPST_RTN_B32_vi   : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
1161def DS_CMPST_RTN_F32_vi   : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
1162def DS_MIN_RTN_F32_vi     : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
1163def DS_MAX_RTN_F32_vi     : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
1164def DS_WRAP_RTN_B32_vi    : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
1165def DS_ADD_RTN_F32_vi     : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
1166def DS_READ_B32_vi        : DS_Real_vi<0x36, DS_READ_B32>;
1167def DS_READ2_B32_vi       : DS_Real_vi<0x37, DS_READ2_B32>;
1168def DS_READ2ST64_B32_vi   : DS_Real_vi<0x38, DS_READ2ST64_B32>;
1169def DS_READ_I8_vi         : DS_Real_vi<0x39, DS_READ_I8>;
1170def DS_READ_U8_vi         : DS_Real_vi<0x3a, DS_READ_U8>;
1171def DS_READ_I16_vi        : DS_Real_vi<0x3b, DS_READ_I16>;
1172def DS_READ_U16_vi        : DS_Real_vi<0x3c, DS_READ_U16>;
1173def DS_READ_ADDTID_B32_vi : DS_Real_vi<0xb6, DS_READ_ADDTID_B32>;
1174def DS_CONSUME_vi         : DS_Real_vi<0xbd, DS_CONSUME>;
1175def DS_APPEND_vi          : DS_Real_vi<0xbe, DS_APPEND>;
1176def DS_ORDERED_COUNT_vi   : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
1177def DS_SWIZZLE_B32_vi     : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
1178def DS_PERMUTE_B32_vi     : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
1179def DS_BPERMUTE_B32_vi    : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
1180
1181def DS_ADD_U64_vi         : DS_Real_vi<0x40, DS_ADD_U64>;
1182def DS_SUB_U64_vi         : DS_Real_vi<0x41, DS_SUB_U64>;
1183def DS_RSUB_U64_vi        : DS_Real_vi<0x42, DS_RSUB_U64>;
1184def DS_INC_U64_vi         : DS_Real_vi<0x43, DS_INC_U64>;
1185def DS_DEC_U64_vi         : DS_Real_vi<0x44, DS_DEC_U64>;
1186def DS_MIN_I64_vi         : DS_Real_vi<0x45, DS_MIN_I64>;
1187def DS_MAX_I64_vi         : DS_Real_vi<0x46, DS_MAX_I64>;
1188def DS_MIN_U64_vi         : DS_Real_vi<0x47, DS_MIN_U64>;
1189def DS_MAX_U64_vi         : DS_Real_vi<0x48, DS_MAX_U64>;
1190def DS_AND_B64_vi         : DS_Real_vi<0x49, DS_AND_B64>;
1191def DS_OR_B64_vi          : DS_Real_vi<0x4a, DS_OR_B64>;
1192def DS_XOR_B64_vi         : DS_Real_vi<0x4b, DS_XOR_B64>;
1193def DS_MSKOR_B64_vi       : DS_Real_vi<0x4c, DS_MSKOR_B64>;
1194def DS_WRITE_B64_vi       : DS_Real_vi<0x4d, DS_WRITE_B64>;
1195def DS_WRITE2_B64_vi      : DS_Real_vi<0x4E, DS_WRITE2_B64>;
1196def DS_WRITE2ST64_B64_vi  : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
1197def DS_CMPST_B64_vi       : DS_Real_vi<0x50, DS_CMPST_B64>;
1198def DS_CMPST_F64_vi       : DS_Real_vi<0x51, DS_CMPST_F64>;
1199def DS_MIN_F64_vi         : DS_Real_vi<0x52, DS_MIN_F64>;
1200def DS_MAX_F64_vi         : DS_Real_vi<0x53, DS_MAX_F64>;
1201
1202def DS_WRITE_B8_D16_HI_vi  : DS_Real_vi<0x54, DS_WRITE_B8_D16_HI>;
1203def DS_WRITE_B16_D16_HI_vi : DS_Real_vi<0x55, DS_WRITE_B16_D16_HI>;
1204
1205def DS_READ_U8_D16_vi     : DS_Real_vi<0x56, DS_READ_U8_D16>;
1206def DS_READ_U8_D16_HI_vi  : DS_Real_vi<0x57, DS_READ_U8_D16_HI>;
1207def DS_READ_I8_D16_vi     : DS_Real_vi<0x58, DS_READ_I8_D16>;
1208def DS_READ_I8_D16_HI_vi  : DS_Real_vi<0x59, DS_READ_I8_D16_HI>;
1209def DS_READ_U16_D16_vi    : DS_Real_vi<0x5a, DS_READ_U16_D16>;
1210def DS_READ_U16_D16_HI_vi : DS_Real_vi<0x5b, DS_READ_U16_D16_HI>;
1211
1212def DS_ADD_RTN_U64_vi     : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
1213def DS_SUB_RTN_U64_vi     : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
1214def DS_RSUB_RTN_U64_vi    : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
1215def DS_INC_RTN_U64_vi     : DS_Real_vi<0x63, DS_INC_RTN_U64>;
1216def DS_DEC_RTN_U64_vi     : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
1217def DS_MIN_RTN_I64_vi     : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
1218def DS_MAX_RTN_I64_vi     : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
1219def DS_MIN_RTN_U64_vi     : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
1220def DS_MAX_RTN_U64_vi     : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
1221def DS_AND_RTN_B64_vi     : DS_Real_vi<0x69, DS_AND_RTN_B64>;
1222def DS_OR_RTN_B64_vi      : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
1223def DS_XOR_RTN_B64_vi     : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
1224def DS_MSKOR_RTN_B64_vi   : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
1225def DS_WRXCHG_RTN_B64_vi  : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
1226def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
1227def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
1228def DS_CONDXCHG32_RTN_B64_vi   : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
1229def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
1230def DS_CMPST_RTN_B64_vi   : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
1231def DS_CMPST_RTN_F64_vi   : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
1232def DS_MIN_RTN_F64_vi     : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
1233def DS_MAX_RTN_F64_vi     : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
1234
1235def DS_READ_B64_vi        : DS_Real_vi<0x76, DS_READ_B64>;
1236def DS_READ2_B64_vi       : DS_Real_vi<0x77, DS_READ2_B64>;
1237def DS_READ2ST64_B64_vi   : DS_Real_vi<0x78, DS_READ2ST64_B64>;
1238
1239def DS_ADD_SRC2_U32_vi    : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
1240def DS_SUB_SRC2_U32_vi    : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
1241def DS_RSUB_SRC2_U32_vi   : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
1242def DS_INC_SRC2_U32_vi    : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
1243def DS_DEC_SRC2_U32_vi    : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
1244def DS_MIN_SRC2_I32_vi    : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
1245def DS_MAX_SRC2_I32_vi    : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
1246def DS_MIN_SRC2_U32_vi    : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
1247def DS_MAX_SRC2_U32_vi    : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
1248def DS_AND_SRC2_B32_vi    : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
1249def DS_OR_SRC2_B32_vi     : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
1250def DS_XOR_SRC2_B32_vi    : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
1251def DS_WRITE_SRC2_B32_vi  : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
1252def DS_MIN_SRC2_F32_vi    : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
1253def DS_MAX_SRC2_F32_vi    : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
1254def DS_ADD_SRC2_F32_vi    : DS_Real_vi<0x95, DS_ADD_SRC2_F32>;
1255def DS_ADD_SRC2_U64_vi    : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
1256def DS_SUB_SRC2_U64_vi    : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
1257def DS_RSUB_SRC2_U64_vi   : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
1258def DS_INC_SRC2_U64_vi    : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
1259def DS_DEC_SRC2_U64_vi    : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
1260def DS_MIN_SRC2_I64_vi    : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
1261def DS_MAX_SRC2_I64_vi    : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
1262def DS_MIN_SRC2_U64_vi    : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
1263def DS_MAX_SRC2_U64_vi    : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
1264def DS_AND_SRC2_B64_vi    : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
1265def DS_OR_SRC2_B64_vi     : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
1266def DS_XOR_SRC2_B64_vi    : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
1267def DS_WRITE_SRC2_B64_vi  : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
1268def DS_MIN_SRC2_F64_vi    : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
1269def DS_MAX_SRC2_F64_vi    : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
1270def DS_WRITE_B96_vi       : DS_Real_vi<0xde, DS_WRITE_B96>;
1271def DS_WRITE_B128_vi      : DS_Real_vi<0xdf, DS_WRITE_B128>;
1272def DS_READ_B96_vi        : DS_Real_vi<0xfe, DS_READ_B96>;
1273def DS_READ_B128_vi       : DS_Real_vi<0xff, DS_READ_B128>;
1274