xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/DSInstructions.td (revision 924226fba12cc9a228c73b956e1b7fa24c60b055) 
1//===-- DSInstructions.td - DS Instruction Definitions --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
10  InstSI <outs, ins, "", pattern>,
11  SIMCInstr <opName, SIEncodingFamily.NONE> {
12
13  let LGKM_CNT = 1;
14  let DS = 1;
15  let Size = 8;
16  let UseNamedOperandTable = 1;
17
18  // Most instruction load and store data, so set this as the default.
19  let mayLoad = 1;
20  let mayStore = 1;
21  let maybeAtomic = 1;
22
23  let hasSideEffects = 0;
24  let SchedRW = [WriteLDS];
25
26  let isPseudo = 1;
27  let isCodeGenOnly = 1;
28
29  let AsmMatchConverter = "cvtDS";
30
31  string Mnemonic = opName;
32  string AsmOperands = asmOps;
33
34  // Well these bits a kind of hack because it would be more natural
35  // to test "outs" and "ins" dags for the presence of particular operands
36  bits<1> has_vdst = 1;
37  bits<1> has_addr = 1;
38  bits<1> has_data0 = 1;
39  bits<1> has_data1 = 1;
40
41  bits<1> has_gws_data0 = 0; // data0 is encoded as addr
42
43  bits<1> has_offset  = 1; // has "offset" that should be split to offset0,1
44  bits<1> has_offset0 = 1;
45  bits<1> has_offset1 = 1;
46
47  bits<1> has_gds = 1;
48  bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
49
50  bits<1> has_m0_read = 1;
51
52  let Uses = !if(has_m0_read, [M0, EXEC], [EXEC]);
53}
54
55class DS_Real <DS_Pseudo ps> :
56  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
57  Enc64 {
58
59  let isPseudo = 0;
60  let isCodeGenOnly = 0;
61  let LGKM_CNT = 1;
62  let DS = 1;
63  let UseNamedOperandTable = 1;
64
65  // copy relevant pseudo op flags
66  let SubtargetPredicate = ps.SubtargetPredicate;
67  let OtherPredicates    = ps.OtherPredicates;
68  let AsmMatchConverter  = ps.AsmMatchConverter;
69  let SchedRW            = ps.SchedRW;
70  let mayLoad            = ps.mayLoad;
71  let mayStore           = ps.mayStore;
72  let IsAtomicRet        = ps.IsAtomicRet;
73  let IsAtomicNoRet      = ps.IsAtomicNoRet;
74
75  // encoding fields
76  bits<10> vdst;
77  bits<1> gds;
78  bits<8> addr;
79  bits<10> data0;
80  bits<10> data1;
81  bits<8> offset0;
82  bits<8> offset1;
83
84  bits<16> offset;
85  let offset0 = !if(ps.has_offset, offset{7-0}, ?);
86  let offset1 = !if(ps.has_offset, offset{15-8}, ?);
87
88  bits<1> acc = !if(ps.has_vdst, vdst{9},
89                    !if(!or(ps.has_data0, ps.has_gws_data0), data0{9}, 0));
90}
91
92// DS Pseudo instructions
93
94class DS_0A1D_NORET<string opName, RegisterClass rc = VGPR_32>
95: DS_Pseudo<opName,
96  (outs),
97  (ins getLdStRegisterOperand<rc>.ret:$data0, offset:$offset, gds:$gds),
98  " $data0$offset$gds"> {
99
100  let has_addr = 0;
101  let has_data1 = 0;
102  let has_vdst = 0;
103}
104
105class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
106: DS_Pseudo<opName,
107  (outs),
108  (ins VGPR_32:$addr, getLdStRegisterOperand<rc>.ret:$data0, offset:$offset, gds:$gds),
109  " $addr, $data0$offset$gds"> {
110
111  let has_data1 = 0;
112  let has_vdst = 0;
113  let IsAtomicNoRet = 1;
114}
115
116multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
117  def "" : DS_1A1D_NORET<opName, rc>,
118           AtomicNoRet<opName, 0>;
119
120  let has_m0_read = 0 in {
121    def _gfx9 : DS_1A1D_NORET<opName, rc>,
122                AtomicNoRet<opName#"_gfx9", 0>;
123  }
124}
125
126multiclass DS_1A1D_NORET_mc_gfx9<string opName, RegisterClass rc = VGPR_32> {
127  let has_m0_read = 0 in {
128    def "" : DS_1A1D_NORET<opName, rc>,
129                AtomicNoRet<opName, 0>;
130  }
131}
132
133class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32,
134                    RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
135: DS_Pseudo<opName,
136  (outs),
137  (ins VGPR_32:$addr, data_op:$data0, data_op:$data1, offset:$offset, gds:$gds),
138  " $addr, $data0, $data1$offset$gds"> {
139
140  let has_vdst = 0;
141  let IsAtomicNoRet = 1;
142}
143
144multiclass DS_1A2D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
145  def "" : DS_1A2D_NORET<opName, rc>,
146           AtomicNoRet<opName, 0>;
147
148  let has_m0_read = 0 in {
149    def _gfx9 : DS_1A2D_NORET<opName, rc>,
150                AtomicNoRet<opName#"_gfx9", 0>;
151  }
152}
153
154class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32,
155                          RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
156: DS_Pseudo<opName,
157  (outs),
158  (ins VGPR_32:$addr, data_op:$data0, data_op:$data1,
159       offset0:$offset0, offset1:$offset1, gds:$gds),
160  " $addr, $data0, $data1$offset0$offset1$gds"> {
161
162  let has_vdst = 0;
163  let has_offset = 0;
164  let AsmMatchConverter = "cvtDSOffset01";
165}
166
167multiclass DS_1A2D_Off8_NORET_mc <string opName, RegisterClass rc = VGPR_32> {
168  def "" : DS_1A2D_Off8_NORET<opName, rc>;
169
170  let has_m0_read = 0 in {
171    def _gfx9 : DS_1A2D_Off8_NORET<opName, rc>;
172  }
173}
174
175class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32,
176                  RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
177: DS_Pseudo<opName,
178  (outs data_op:$vdst),
179  (ins VGPR_32:$addr, data_op:$data0, offset:$offset, gds:$gds),
180  " $vdst, $addr, $data0$offset$gds"> {
181
182  let hasPostISelHook = 1;
183  let has_data1 = 0;
184  let IsAtomicRet = 1;
185}
186
187multiclass DS_1A1D_RET_mc <string opName, RegisterClass rc = VGPR_32,
188                           string NoRetOp = ""> {
189  def "" : DS_1A1D_RET<opName, rc>,
190    AtomicNoRet<NoRetOp, !ne(NoRetOp, "")>;
191
192  let has_m0_read = 0 in {
193    def _gfx9 : DS_1A1D_RET<opName, rc>,
194      AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp#"_gfx9"),
195                  !ne(NoRetOp, "")>;
196  }
197}
198
199multiclass DS_1A1D_RET_mc_gfx9 <string opName, RegisterClass rc = VGPR_32,
200                                string NoRetOp = ""> {
201  let has_m0_read = 0 in {
202    def "" : DS_1A1D_RET<opName, rc>,
203      AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp),
204                  !if(!eq(NoRetOp, ""), 0, 1)>;
205  }
206}
207
208class DS_1A2D_RET<string opName,
209                  RegisterClass rc = VGPR_32,
210                  RegisterClass src = rc,
211                  RegisterOperand dst_op = getLdStRegisterOperand<rc>.ret,
212                  RegisterOperand src_op = getLdStRegisterOperand<src>.ret>
213: DS_Pseudo<opName,
214  (outs dst_op:$vdst),
215  (ins VGPR_32:$addr, src_op:$data0, src_op:$data1, offset:$offset, gds:$gds),
216  " $vdst, $addr, $data0, $data1$offset$gds"> {
217
218  let hasPostISelHook = 1;
219  let IsAtomicRet = 1;
220}
221
222multiclass DS_1A2D_RET_mc<string opName,
223                          RegisterClass rc = VGPR_32,
224                          string NoRetOp = "",
225                          RegisterClass src = rc> {
226  def "" : DS_1A2D_RET<opName, rc, src>,
227    AtomicNoRet<NoRetOp, !ne(NoRetOp, "")>;
228
229  let has_m0_read = 0 in {
230    def _gfx9 : DS_1A2D_RET<opName, rc, src>,
231      AtomicNoRet<NoRetOp#"_gfx9", !ne(NoRetOp, "")>;
232  }
233}
234
235class DS_1A2D_Off8_RET<string opName,
236                       RegisterClass rc = VGPR_32,
237                       RegisterClass src = rc,
238                       RegisterOperand dst_op = getLdStRegisterOperand<rc>.ret,
239                       RegisterOperand src_op = getLdStRegisterOperand<src>.ret>
240: DS_Pseudo<opName,
241  (outs dst_op:$vdst),
242  (ins VGPR_32:$addr, src_op:$data0, src_op:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
243  " $vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
244
245  let has_offset = 0;
246  let AsmMatchConverter = "cvtDSOffset01";
247
248  let hasPostISelHook = 1;
249}
250
251multiclass DS_1A2D_Off8_RET_mc<string opName,
252                               RegisterClass rc = VGPR_32,
253                               RegisterClass src = rc> {
254  def "" : DS_1A2D_Off8_RET<opName, rc, src>;
255
256  let has_m0_read = 0 in {
257    def _gfx9 : DS_1A2D_Off8_RET<opName, rc, src>;
258  }
259}
260
261
262class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset,
263                RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
264: DS_Pseudo<opName,
265  (outs data_op:$vdst),
266  !if(HasTiedOutput,
267    (ins VGPR_32:$addr, ofs:$offset, gds:$gds, data_op:$vdst_in),
268    (ins VGPR_32:$addr, ofs:$offset, gds:$gds)),
269  " $vdst, $addr$offset$gds"> {
270  let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
271  let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
272  let has_data0 = 0;
273  let has_data1 = 0;
274}
275
276multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> {
277  def "" : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
278
279  let has_m0_read = 0 in {
280    def _gfx9 : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
281  }
282}
283
284class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> :
285  DS_1A_RET<opName, rc, 1>;
286
287class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
288: DS_Pseudo<opName,
289  (outs getLdStRegisterOperand<rc>.ret:$vdst),
290  (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
291  " $vdst, $addr$offset0$offset1$gds"> {
292
293  let has_offset = 0;
294  let has_data0 = 0;
295  let has_data1 = 0;
296  let AsmMatchConverter = "cvtDSOffset01";
297}
298
299multiclass DS_1A_Off8_RET_mc <string opName, RegisterClass rc = VGPR_32> {
300  def "" : DS_1A_Off8_RET<opName, rc>;
301
302  let has_m0_read = 0 in {
303    def _gfx9 : DS_1A_Off8_RET<opName, rc>;
304  }
305}
306
307class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
308  (outs getLdStRegisterOperand<VGPR_32>.ret:$vdst),
309  (ins VGPR_32:$addr, offset:$offset),
310  " $vdst, $addr$offset gds"> {
311
312  let has_data0 = 0;
313  let has_data1 = 0;
314  let has_gds = 0;
315  let gdsValue = 1;
316  let AsmMatchConverter = "cvtDSGds";
317}
318
319class DS_0A_RET <string opName> : DS_Pseudo<opName,
320  (outs getLdStRegisterOperand<VGPR_32>.ret:$vdst),
321  (ins offset:$offset, gds:$gds),
322  " $vdst$offset$gds"> {
323
324  let mayLoad = 1;
325  let mayStore = 1;
326
327  let has_addr = 0;
328  let has_data0 = 0;
329  let has_data1 = 0;
330}
331
332class DS_1A <string opName> : DS_Pseudo<opName,
333  (outs),
334  (ins VGPR_32:$addr, offset:$offset, gds:$gds),
335  " $addr$offset$gds"> {
336
337  let mayLoad = 1;
338  let mayStore = 1;
339
340  let has_vdst = 0;
341  let has_data0 = 0;
342  let has_data1 = 0;
343}
344
345multiclass DS_1A_mc <string opName> {
346  def "" : DS_1A<opName>;
347
348  let has_m0_read = 0 in {
349    def _gfx9 : DS_1A<opName>;
350  }
351}
352
353
354class DS_GWS <string opName, dag ins, string asmOps>
355: DS_Pseudo<opName, (outs), ins, asmOps> {
356
357  let has_vdst  = 0;
358  let has_addr  = 0;
359  let has_data0 = 0;
360  let has_data1 = 0;
361
362  let has_gds   = 0;
363  let gdsValue  = 1;
364  let AsmMatchConverter = "cvtDSGds";
365}
366
367class DS_GWS_0D <string opName>
368: DS_GWS<opName,
369  (ins offset:$offset), "$offset gds"> {
370  let hasSideEffects = 1;
371}
372
373class DS_GWS_1D <string opName>
374: DS_GWS<opName,
375  (ins getLdStRegisterOperand<VGPR_32>.ret:$data0, offset:$offset),
376  " $data0$offset gds"> {
377
378  let has_gws_data0 = 1;
379  let hasSideEffects = 1;
380}
381
382class DS_VOID <string opName> : DS_Pseudo<opName,
383  (outs), (ins), ""> {
384  let mayLoad = 0;
385  let mayStore = 0;
386  let hasSideEffects = 1;
387  let UseNamedOperandTable = 0;
388  let AsmMatchConverter = "";
389
390  let has_vdst = 0;
391  let has_addr = 0;
392  let has_data0 = 0;
393  let has_data1 = 0;
394  let has_offset = 0;
395  let has_offset0 = 0;
396  let has_offset1 = 0;
397  let has_gds = 0;
398}
399
400class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag,
401                       RegisterOperand data_op = getLdStRegisterOperand<VGPR_32>.ret>
402: DS_Pseudo<opName,
403  (outs data_op:$vdst),
404  (ins VGPR_32:$addr, data_op:$data0, offset:$offset),
405  " $vdst, $addr, $data0$offset",
406  [(set i32:$vdst,
407   (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
408
409  let mayLoad = 0;
410  let mayStore = 0;
411  let isConvergent = 1;
412
413  let has_data1 = 0;
414  let has_gds = 0;
415}
416
417defm DS_ADD_U32       : DS_1A1D_NORET_mc<"ds_add_u32">;
418defm DS_SUB_U32       : DS_1A1D_NORET_mc<"ds_sub_u32">;
419defm DS_RSUB_U32      : DS_1A1D_NORET_mc<"ds_rsub_u32">;
420defm DS_INC_U32       : DS_1A1D_NORET_mc<"ds_inc_u32">;
421defm DS_DEC_U32       : DS_1A1D_NORET_mc<"ds_dec_u32">;
422defm DS_MIN_I32       : DS_1A1D_NORET_mc<"ds_min_i32">;
423defm DS_MAX_I32       : DS_1A1D_NORET_mc<"ds_max_i32">;
424defm DS_MIN_U32       : DS_1A1D_NORET_mc<"ds_min_u32">;
425defm DS_MAX_U32       : DS_1A1D_NORET_mc<"ds_max_u32">;
426defm DS_AND_B32       : DS_1A1D_NORET_mc<"ds_and_b32">;
427defm DS_OR_B32        : DS_1A1D_NORET_mc<"ds_or_b32">;
428defm DS_XOR_B32       : DS_1A1D_NORET_mc<"ds_xor_b32">;
429
430let SubtargetPredicate = HasLDSFPAtomicAdd in {
431defm DS_ADD_F32       : DS_1A1D_NORET_mc<"ds_add_f32">;
432}
433
434defm DS_MIN_F32       : DS_1A1D_NORET_mc<"ds_min_f32">;
435defm DS_MAX_F32       : DS_1A1D_NORET_mc<"ds_max_f32">;
436
437let mayLoad = 0 in {
438defm DS_WRITE_B8      : DS_1A1D_NORET_mc<"ds_write_b8">;
439defm DS_WRITE_B16     : DS_1A1D_NORET_mc<"ds_write_b16">;
440defm DS_WRITE_B32     : DS_1A1D_NORET_mc<"ds_write_b32">;
441defm DS_WRITE2_B32    : DS_1A2D_Off8_NORET_mc<"ds_write2_b32">;
442defm DS_WRITE2ST64_B32: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b32">;
443
444
445let has_m0_read = 0 in {
446
447let SubtargetPredicate = HasD16LoadStore in {
448def DS_WRITE_B8_D16_HI  : DS_1A1D_NORET<"ds_write_b8_d16_hi">;
449def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">;
450}
451
452} // End has_m0_read = 0
453
454let SubtargetPredicate = HasDSAddTid in {
455def DS_WRITE_ADDTID_B32 : DS_0A1D_NORET<"ds_write_addtid_b32">;
456}
457
458} // End mayLoad = 0
459
460let SubtargetPredicate = isGFX90APlus in {
461  defm DS_ADD_F64     : DS_1A1D_NORET_mc_gfx9<"ds_add_f64", VReg_64>;
462  defm DS_ADD_RTN_F64 : DS_1A1D_RET_mc_gfx9<"ds_add_rtn_f64", VReg_64, "ds_add_f64">;
463} // End SubtargetPredicate = isGFX90APlus
464
465defm DS_MSKOR_B32     : DS_1A2D_NORET_mc<"ds_mskor_b32">;
466defm DS_CMPST_B32     : DS_1A2D_NORET_mc<"ds_cmpst_b32">;
467defm DS_CMPST_F32     : DS_1A2D_NORET_mc<"ds_cmpst_f32">;
468
469defm DS_ADD_U64       : DS_1A1D_NORET_mc<"ds_add_u64", VReg_64>;
470defm DS_SUB_U64       : DS_1A1D_NORET_mc<"ds_sub_u64", VReg_64>;
471defm DS_RSUB_U64      : DS_1A1D_NORET_mc<"ds_rsub_u64", VReg_64>;
472defm DS_INC_U64       : DS_1A1D_NORET_mc<"ds_inc_u64", VReg_64>;
473defm DS_DEC_U64       : DS_1A1D_NORET_mc<"ds_dec_u64", VReg_64>;
474defm DS_MIN_I64       : DS_1A1D_NORET_mc<"ds_min_i64", VReg_64>;
475defm DS_MAX_I64       : DS_1A1D_NORET_mc<"ds_max_i64", VReg_64>;
476defm DS_MIN_U64       : DS_1A1D_NORET_mc<"ds_min_u64", VReg_64>;
477defm DS_MAX_U64       : DS_1A1D_NORET_mc<"ds_max_u64", VReg_64>;
478defm DS_AND_B64       : DS_1A1D_NORET_mc<"ds_and_b64", VReg_64>;
479defm DS_OR_B64        : DS_1A1D_NORET_mc<"ds_or_b64", VReg_64>;
480defm DS_XOR_B64       : DS_1A1D_NORET_mc<"ds_xor_b64", VReg_64>;
481defm DS_MSKOR_B64     : DS_1A2D_NORET_mc<"ds_mskor_b64", VReg_64>;
482let mayLoad = 0 in {
483defm DS_WRITE_B64     : DS_1A1D_NORET_mc<"ds_write_b64", VReg_64>;
484defm DS_WRITE2_B64    : DS_1A2D_Off8_NORET_mc<"ds_write2_b64", VReg_64>;
485defm DS_WRITE2ST64_B64: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b64", VReg_64>;
486}
487defm DS_CMPST_B64     : DS_1A2D_NORET_mc<"ds_cmpst_b64", VReg_64>;
488defm DS_CMPST_F64     : DS_1A2D_NORET_mc<"ds_cmpst_f64", VReg_64>;
489defm DS_MIN_F64       : DS_1A1D_NORET_mc<"ds_min_f64", VReg_64>;
490defm DS_MAX_F64       : DS_1A1D_NORET_mc<"ds_max_f64", VReg_64>;
491
492defm DS_ADD_RTN_U32   : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
493
494let SubtargetPredicate = HasLDSFPAtomicAdd in {
495defm DS_ADD_RTN_F32   : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32, "ds_add_f32">;
496}
497defm DS_SUB_RTN_U32   : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
498defm DS_RSUB_RTN_U32  : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
499defm DS_INC_RTN_U32   : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
500defm DS_DEC_RTN_U32   : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
501defm DS_MIN_RTN_I32   : DS_1A1D_RET_mc<"ds_min_rtn_i32", VGPR_32, "ds_min_i32">;
502defm DS_MAX_RTN_I32   : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
503defm DS_MIN_RTN_U32   : DS_1A1D_RET_mc<"ds_min_rtn_u32", VGPR_32, "ds_min_u32">;
504defm DS_MAX_RTN_U32   : DS_1A1D_RET_mc<"ds_max_rtn_u32", VGPR_32, "ds_max_u32">;
505defm DS_AND_RTN_B32   : DS_1A1D_RET_mc<"ds_and_rtn_b32", VGPR_32, "ds_and_b32">;
506defm DS_OR_RTN_B32    : DS_1A1D_RET_mc<"ds_or_rtn_b32", VGPR_32, "ds_or_b32">;
507defm DS_XOR_RTN_B32   : DS_1A1D_RET_mc<"ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">;
508defm DS_MSKOR_RTN_B32 : DS_1A2D_RET_mc<"ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">;
509defm DS_CMPST_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
510defm DS_CMPST_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
511defm DS_MIN_RTN_F32   : DS_1A1D_RET_mc<"ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
512defm DS_MAX_RTN_F32   : DS_1A1D_RET_mc<"ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
513
514defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b32">;
515defm DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>;
516defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>;
517
518defm DS_ADD_RTN_U64  : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64, "ds_add_u64">;
519defm DS_SUB_RTN_U64  : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
520defm DS_RSUB_RTN_U64  : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
521defm DS_INC_RTN_U64   : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
522defm DS_DEC_RTN_U64   : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
523defm DS_MIN_RTN_I64    : DS_1A1D_RET_mc<"ds_min_rtn_i64", VReg_64, "ds_min_i64">;
524defm DS_MAX_RTN_I64    : DS_1A1D_RET_mc<"ds_max_rtn_i64", VReg_64, "ds_max_i64">;
525defm DS_MIN_RTN_U64   : DS_1A1D_RET_mc<"ds_min_rtn_u64", VReg_64, "ds_min_u64">;
526defm DS_MAX_RTN_U64   : DS_1A1D_RET_mc<"ds_max_rtn_u64", VReg_64, "ds_max_u64">;
527defm DS_AND_RTN_B64    : DS_1A1D_RET_mc<"ds_and_rtn_b64", VReg_64, "ds_and_b64">;
528defm DS_OR_RTN_B64     : DS_1A1D_RET_mc<"ds_or_rtn_b64", VReg_64, "ds_or_b64">;
529defm DS_XOR_RTN_B64    : DS_1A1D_RET_mc<"ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
530defm DS_MSKOR_RTN_B64  : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
531defm DS_CMPST_RTN_B64  : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
532defm DS_CMPST_RTN_F64  : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
533defm DS_MIN_RTN_F64    : DS_1A1D_RET_mc<"ds_min_rtn_f64", VReg_64, "ds_min_f64">;
534defm DS_MAX_RTN_F64    : DS_1A1D_RET_mc<"ds_max_rtn_f64", VReg_64, "ds_max_f64">;
535
536defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", VReg_64>;
537defm DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>;
538defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>;
539
540let isConvergent = 1, usesCustomInserter = 1 in {
541def DS_GWS_INIT       : DS_GWS_1D<"ds_gws_init"> {
542  let mayLoad = 0;
543}
544def DS_GWS_SEMA_V     : DS_GWS_0D<"ds_gws_sema_v">;
545def DS_GWS_SEMA_BR    : DS_GWS_1D<"ds_gws_sema_br">;
546def DS_GWS_SEMA_P     : DS_GWS_0D<"ds_gws_sema_p">;
547def DS_GWS_BARRIER    : DS_GWS_1D<"ds_gws_barrier">;
548}
549
550let SubtargetPredicate = HasDsSrc2Insts in {
551def DS_ADD_SRC2_U32   : DS_1A<"ds_add_src2_u32">;
552def DS_SUB_SRC2_U32   : DS_1A<"ds_sub_src2_u32">;
553def DS_RSUB_SRC2_U32  : DS_1A<"ds_rsub_src2_u32">;
554def DS_INC_SRC2_U32   : DS_1A<"ds_inc_src2_u32">;
555def DS_DEC_SRC2_U32   : DS_1A<"ds_dec_src2_u32">;
556def DS_MIN_SRC2_I32   : DS_1A<"ds_min_src2_i32">;
557def DS_MAX_SRC2_I32   : DS_1A<"ds_max_src2_i32">;
558def DS_MIN_SRC2_U32   : DS_1A<"ds_min_src2_u32">;
559def DS_MAX_SRC2_U32   : DS_1A<"ds_max_src2_u32">;
560def DS_AND_SRC2_B32   : DS_1A<"ds_and_src2_b32">;
561def DS_OR_SRC2_B32    : DS_1A<"ds_or_src2_b32">;
562def DS_XOR_SRC2_B32   : DS_1A<"ds_xor_src2_b32">;
563def DS_MIN_SRC2_F32   : DS_1A<"ds_min_src2_f32">;
564def DS_MAX_SRC2_F32   : DS_1A<"ds_max_src2_f32">;
565
566def DS_ADD_SRC2_U64   : DS_1A<"ds_add_src2_u64">;
567def DS_SUB_SRC2_U64   : DS_1A<"ds_sub_src2_u64">;
568def DS_RSUB_SRC2_U64  : DS_1A<"ds_rsub_src2_u64">;
569def DS_INC_SRC2_U64   : DS_1A<"ds_inc_src2_u64">;
570def DS_DEC_SRC2_U64   : DS_1A<"ds_dec_src2_u64">;
571def DS_MIN_SRC2_I64   : DS_1A<"ds_min_src2_i64">;
572def DS_MAX_SRC2_I64   : DS_1A<"ds_max_src2_i64">;
573def DS_MIN_SRC2_U64   : DS_1A<"ds_min_src2_u64">;
574def DS_MAX_SRC2_U64   : DS_1A<"ds_max_src2_u64">;
575def DS_AND_SRC2_B64   : DS_1A<"ds_and_src2_b64">;
576def DS_OR_SRC2_B64    : DS_1A<"ds_or_src2_b64">;
577def DS_XOR_SRC2_B64   : DS_1A<"ds_xor_src2_b64">;
578def DS_MIN_SRC2_F64   : DS_1A<"ds_min_src2_f64">;
579def DS_MAX_SRC2_F64   : DS_1A<"ds_max_src2_f64">;
580
581def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">;
582def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
583} // End SubtargetPredicate = HasDsSrc2Insts
584
585let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
586def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>;
587}
588
589let mayStore = 0 in {
590defm DS_READ_I8      : DS_1A_RET_mc<"ds_read_i8">;
591defm DS_READ_U8      : DS_1A_RET_mc<"ds_read_u8">;
592defm DS_READ_I16     : DS_1A_RET_mc<"ds_read_i16">;
593defm DS_READ_U16     : DS_1A_RET_mc<"ds_read_u16">;
594defm DS_READ_B32     : DS_1A_RET_mc<"ds_read_b32">;
595defm DS_READ_B64     : DS_1A_RET_mc<"ds_read_b64", VReg_64>;
596
597defm DS_READ2_B32    : DS_1A_Off8_RET_mc<"ds_read2_b32", VReg_64>;
598defm DS_READ2ST64_B32: DS_1A_Off8_RET_mc<"ds_read2st64_b32", VReg_64>;
599
600defm DS_READ2_B64    : DS_1A_Off8_RET_mc<"ds_read2_b64", VReg_128>;
601defm DS_READ2ST64_B64: DS_1A_Off8_RET_mc<"ds_read2st64_b64", VReg_128>;
602
603let has_m0_read = 0 in {
604let SubtargetPredicate = HasD16LoadStore in {
605def DS_READ_U8_D16     : DS_1A_RET_Tied<"ds_read_u8_d16">;
606def DS_READ_U8_D16_HI  : DS_1A_RET_Tied<"ds_read_u8_d16_hi">;
607def DS_READ_I8_D16     : DS_1A_RET_Tied<"ds_read_i8_d16">;
608def DS_READ_I8_D16_HI  : DS_1A_RET_Tied<"ds_read_i8_d16_hi">;
609def DS_READ_U16_D16    : DS_1A_RET_Tied<"ds_read_u16_d16">;
610def DS_READ_U16_D16_HI : DS_1A_RET_Tied<"ds_read_u16_d16_hi">;
611}
612} // End has_m0_read = 0
613
614let SubtargetPredicate = HasDSAddTid in {
615def DS_READ_ADDTID_B32 : DS_0A_RET<"ds_read_addtid_b32">;
616}
617
618} // End mayStore = 0
619
620def DS_CONSUME       : DS_0A_RET<"ds_consume">;
621def DS_APPEND        : DS_0A_RET<"ds_append">;
622def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
623
624//===----------------------------------------------------------------------===//
625// Instruction definitions for CI and newer.
626//===----------------------------------------------------------------------===//
627
628let SubtargetPredicate = isGFX7Plus in {
629
630defm DS_WRAP_RTN_B32 : DS_1A2D_RET_mc<"ds_wrap_rtn_b32", VGPR_32>;
631defm DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET_mc<"ds_condxchg32_rtn_b64", VReg_64>;
632
633let isConvergent = 1, usesCustomInserter = 1 in {
634def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
635}
636
637let mayStore = 0 in {
638defm DS_READ_B96 : DS_1A_RET_mc<"ds_read_b96", VReg_96>;
639defm DS_READ_B128: DS_1A_RET_mc<"ds_read_b128", VReg_128>;
640} // End mayStore = 0
641
642let mayLoad = 0 in {
643defm DS_WRITE_B96 : DS_1A1D_NORET_mc<"ds_write_b96", VReg_96>;
644defm DS_WRITE_B128 : DS_1A1D_NORET_mc<"ds_write_b128", VReg_128>;
645} // End mayLoad = 0
646
647def DS_NOP : DS_VOID<"ds_nop">;
648
649} // let SubtargetPredicate = isGFX7Plus
650
651//===----------------------------------------------------------------------===//
652// Instruction definitions for VI and newer.
653//===----------------------------------------------------------------------===//
654
655let SubtargetPredicate = isGFX8Plus in {
656
657let Uses = [EXEC] in {
658def DS_PERMUTE_B32  : DS_1A1D_PERMUTE <"ds_permute_b32",
659                                       int_amdgcn_ds_permute>;
660def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
661                                       int_amdgcn_ds_bpermute>;
662}
663
664} // let SubtargetPredicate = isGFX8Plus
665
666let SubtargetPredicate = HasLDSFPAtomicAdd, OtherPredicates = [HasDsSrc2Insts] in {
667def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
668}
669
670//===----------------------------------------------------------------------===//
671// DS Patterns
672//===----------------------------------------------------------------------===//
673
674def : GCNPat <
675  (int_amdgcn_ds_swizzle i32:$src, timm:$offset16),
676  (DS_SWIZZLE_B32 VGPR_32:$src, (as_i16timm $offset16), (i1 0))
677>;
678
679class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
680  (vt (frag (DS1Addr1Offset i32:$ptr, i16:$offset))),
681  (inst $ptr, offset:$offset, (i1 gds))
682>;
683
684multiclass DSReadPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
685
686  let OtherPredicates = [LDSRequiresM0Init] in {
687    def : DSReadPat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
688  }
689
690  let OtherPredicates = [NotLDSRequiresM0Init] in {
691    def : DSReadPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
692  }
693}
694
695class DSReadPat_D16 <DS_Pseudo inst, PatFrag frag, ValueType vt> : GCNPat <
696  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$in),
697  (inst $ptr, offset:$offset, (i1 0), $in)
698>;
699
700defm : DSReadPat_mc <DS_READ_I8, i32, "sextloadi8_local">;
701defm : DSReadPat_mc <DS_READ_I8,  i16, "sextloadi8_local">;
702defm : DSReadPat_mc <DS_READ_U8,  i32, "extloadi8_local">;
703defm : DSReadPat_mc <DS_READ_U8,  i32, "zextloadi8_local">;
704defm : DSReadPat_mc <DS_READ_U8,  i16, "extloadi8_local">;
705defm : DSReadPat_mc <DS_READ_U8,  i16, "zextloadi8_local">;
706defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
707defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
708defm : DSReadPat_mc <DS_READ_U16, i32, "extloadi16_local">;
709defm : DSReadPat_mc <DS_READ_U16, i32, "zextloadi16_local">;
710defm : DSReadPat_mc <DS_READ_U16, i16, "load_local">;
711
712foreach vt = Reg32Types.types in {
713defm : DSReadPat_mc <DS_READ_B32, vt, "load_local">;
714}
715
716defm : DSReadPat_mc <DS_READ_U8, i16, "atomic_load_8_local">;
717defm : DSReadPat_mc <DS_READ_U8, i32, "atomic_load_8_local">;
718defm : DSReadPat_mc <DS_READ_U16, i16, "atomic_load_16_local">;
719defm : DSReadPat_mc <DS_READ_U16, i32, "atomic_load_16_local">;
720defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_32_local">;
721defm : DSReadPat_mc <DS_READ_B64, i64, "atomic_load_64_local">;
722
723let OtherPredicates = [D16PreservesUnusedBits] in {
724def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2i16>;
725def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2f16>;
726def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2i16>;
727def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2f16>;
728def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2i16>;
729def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2f16>;
730
731def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2i16>;
732def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2f16>;
733def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2i16>;
734def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2f16>;
735def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2i16>;
736def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2f16>;
737}
738
739class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
740  (frag vt:$value, (DS1Addr1Offset i32:$ptr, i16:$offset)),
741  (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))
742>;
743
744multiclass DSWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
745  let OtherPredicates = [LDSRequiresM0Init] in {
746    def : DSWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
747  }
748
749  let OtherPredicates = [NotLDSRequiresM0Init] in {
750    def : DSWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
751  }
752}
753
754// Irritatingly, atomic_store reverses the order of operands from a
755// normal store.
756class DSAtomicWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
757  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$value),
758  (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 0))
759>;
760
761multiclass DSAtomicWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
762  let OtherPredicates = [LDSRequiresM0Init] in {
763    def : DSAtomicWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
764  }
765
766  let OtherPredicates = [NotLDSRequiresM0Init] in {
767    def : DSAtomicWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
768  }
769}
770
771defm : DSWritePat_mc <DS_WRITE_B8, i32, "truncstorei8_local">;
772defm : DSWritePat_mc <DS_WRITE_B16, i32, "truncstorei16_local">;
773defm : DSWritePat_mc <DS_WRITE_B8, i16, "truncstorei8_local">;
774defm : DSWritePat_mc <DS_WRITE_B16, i16, "store_local">;
775
776foreach vt = Reg32Types.types in {
777defm : DSWritePat_mc <DS_WRITE_B32, vt, "store_local">;
778}
779
780defm : DSAtomicWritePat_mc <DS_WRITE_B8, i16, "atomic_store_local_8">;
781defm : DSAtomicWritePat_mc <DS_WRITE_B8, i32, "atomic_store_local_8">;
782defm : DSAtomicWritePat_mc <DS_WRITE_B16, i16, "atomic_store_local_16">;
783defm : DSAtomicWritePat_mc <DS_WRITE_B16, i32, "atomic_store_local_16">;
784defm : DSAtomicWritePat_mc <DS_WRITE_B32, i32, "atomic_store_local_32">;
785defm : DSAtomicWritePat_mc <DS_WRITE_B64, i64, "atomic_store_local_64">;
786
787let OtherPredicates = [D16PreservesUnusedBits] in {
788def : DSWritePat <DS_WRITE_B16_D16_HI, i32, store_hi16_local>;
789def : DSWritePat <DS_WRITE_B8_D16_HI, i32, truncstorei8_hi16_local>;
790}
791
792class DS64Bit4ByteAlignedReadPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
793  (vt:$value (frag (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))),
794  (inst $ptr, $offset0, $offset1, (i1 0))
795>;
796
797class DS64Bit4ByteAlignedWritePat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat<
798  (frag vt:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1)),
799  (inst $ptr, (i32 (EXTRACT_SUBREG VReg_64:$value, sub0)),
800              (i32 (EXTRACT_SUBREG VReg_64:$value, sub1)), $offset0, $offset1,
801              (i1 0))
802>;
803
804class DS128Bit8ByteAlignedReadPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
805  (vt:$value (frag (DS128Bit8ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))),
806  (inst $ptr, $offset0, $offset1, (i1 0))
807>;
808
809class DS128Bit8ByteAlignedWritePat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat<
810  (frag vt:$value, (DS128Bit8ByteAligned i32:$ptr, i8:$offset0, i8:$offset1)),
811  (inst $ptr, (i64 (EXTRACT_SUBREG VReg_128:$value, sub0_sub1)),
812              (i64 (EXTRACT_SUBREG VReg_128:$value, sub2_sub3)), $offset0, $offset1,
813              (i1 0))
814>;
815
816multiclass DS64Bit4ByteAlignedPat_mc<ValueType vt> {
817  let OtherPredicates = [LDSRequiresM0Init, isGFX7Plus] in {
818    def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32, vt, load_local_m0>;
819    def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32, vt, store_local_m0>;
820  }
821
822  let OtherPredicates = [NotLDSRequiresM0Init] in {
823    def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32_gfx9, vt, load_local>;
824    def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32_gfx9, vt, store_local>;
825  }
826}
827
828multiclass DS128Bit8ByteAlignedPat_mc<ValueType vt> {
829  let OtherPredicates = [LDSRequiresM0Init, isGFX7Plus] in {
830    def : DS128Bit8ByteAlignedReadPat<DS_READ2_B64, vt, load_local_m0>;
831    def : DS128Bit8ByteAlignedWritePat<DS_WRITE2_B64, vt, store_local_m0>;
832  }
833
834  let OtherPredicates = [NotLDSRequiresM0Init] in {
835    def : DS128Bit8ByteAlignedReadPat<DS_READ2_B64_gfx9, vt, load_local>;
836    def : DS128Bit8ByteAlignedWritePat<DS_WRITE2_B64_gfx9, vt, store_local>;
837  }
838}
839
840// v2i32 loads are split into i32 loads on SI during lowering, due to a bug
841// related to bounds checking.
842foreach vt = VReg_64.RegTypes in {
843defm : DS64Bit4ByteAlignedPat_mc<vt>;
844}
845
846foreach vt = VReg_128.RegTypes in {
847defm : DS128Bit8ByteAlignedPat_mc<vt>;
848}
849
850// Prefer ds_read over ds_read2 and ds_write over ds_write2, all other things
851// being equal, because it has a larger immediate offset range.
852let AddedComplexity = 100 in {
853
854foreach vt = VReg_64.RegTypes in {
855defm : DSReadPat_mc <DS_READ_B64, vt, "load_align8_local">;
856defm : DSWritePat_mc <DS_WRITE_B64, vt, "store_align8_local">;
857}
858
859let SubtargetPredicate = isGFX7Plus in {
860
861foreach vt = VReg_96.RegTypes in {
862defm : DSReadPat_mc <DS_READ_B96, vt, "load_align16_local">;
863defm : DSWritePat_mc <DS_WRITE_B96, vt, "store_align16_local">;
864}
865
866foreach vt = VReg_128.RegTypes in {
867defm : DSReadPat_mc <DS_READ_B128, vt, "load_align16_local">;
868defm : DSWritePat_mc <DS_WRITE_B128, vt, "store_align16_local">;
869}
870
871let SubtargetPredicate = HasUnalignedAccessMode in {
872
873// FIXME: From performance point of view, is ds_read_b96/ds_write_b96 better choice
874// for unaligned accesses?
875foreach vt = VReg_96.RegTypes in {
876defm : DSReadPat_mc <DS_READ_B96, vt, "load_local">;
877defm : DSWritePat_mc <DS_WRITE_B96, vt, "store_local">;
878}
879
880// For performance reasons, *do not* select ds_read_b128/ds_write_b128 for unaligned
881// accesses.
882
883} // End SubtargetPredicate = HasUnalignedAccessMode
884
885} // End SubtargetPredicate = isGFX7Plus
886
887} // End AddedComplexity = 100
888
889class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
890  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$value),
891  (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))
892>;
893
894multiclass DSAtomicRetPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
895  let OtherPredicates = [LDSRequiresM0Init] in {
896    def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_local_m0_"#vt.Size)>;
897  }
898
899  let OtherPredicates = [NotLDSRequiresM0Init] in {
900    def : DSAtomicRetPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
901                         !cast<PatFrag>(frag#"_local_"#vt.Size)>;
902  }
903
904  def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_region_m0_"#vt.Size), 1>;
905}
906
907
908
909class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
910  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$cmp, vt:$swap),
911  (inst $ptr, getVregSrcForVT<vt>.ret:$cmp, getVregSrcForVT<vt>.ret:$swap, offset:$offset, (i1 gds))
912>;
913
914multiclass DSAtomicCmpXChg_mc<DS_Pseudo inst, ValueType vt, string frag> {
915  let OtherPredicates = [LDSRequiresM0Init] in {
916    def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_local_m0_"#vt.Size)>;
917  }
918
919  let OtherPredicates = [NotLDSRequiresM0Init] in {
920    def : DSAtomicCmpXChg<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
921                          !cast<PatFrag>(frag#"_local_"#vt.Size)>;
922  }
923
924  def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_region_m0_"#vt.Size), 1>;
925}
926
927
928
929// 32-bit atomics.
930defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B32, i32, "atomic_swap">;
931defm : DSAtomicRetPat_mc<DS_ADD_RTN_U32, i32, "atomic_load_add">;
932defm : DSAtomicRetPat_mc<DS_SUB_RTN_U32, i32, "atomic_load_sub">;
933defm : DSAtomicRetPat_mc<DS_INC_RTN_U32, i32, "atomic_inc">;
934defm : DSAtomicRetPat_mc<DS_DEC_RTN_U32, i32, "atomic_dec">;
935defm : DSAtomicRetPat_mc<DS_AND_RTN_B32, i32, "atomic_load_and">;
936defm : DSAtomicRetPat_mc<DS_OR_RTN_B32, i32, "atomic_load_or">;
937defm : DSAtomicRetPat_mc<DS_XOR_RTN_B32, i32, "atomic_load_xor">;
938defm : DSAtomicRetPat_mc<DS_MIN_RTN_I32, i32, "atomic_load_min">;
939defm : DSAtomicRetPat_mc<DS_MAX_RTN_I32, i32, "atomic_load_max">;
940defm : DSAtomicRetPat_mc<DS_MIN_RTN_U32, i32, "atomic_load_umin">;
941defm : DSAtomicRetPat_mc<DS_MAX_RTN_U32, i32, "atomic_load_umax">;
942defm : DSAtomicRetPat_mc<DS_MIN_RTN_F32, f32, "atomic_load_fmin">;
943defm : DSAtomicRetPat_mc<DS_MAX_RTN_F32, f32, "atomic_load_fmax">;
944defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B32, i32, "atomic_cmp_swap">;
945
946let SubtargetPredicate = HasLDSFPAtomicAdd in {
947defm : DSAtomicRetPat_mc<DS_ADD_RTN_F32, f32, "atomic_load_fadd">;
948}
949
950// 64-bit atomics.
951defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B64, i64, "atomic_swap">;
952defm : DSAtomicRetPat_mc<DS_ADD_RTN_U64, i64, "atomic_load_add">;
953defm : DSAtomicRetPat_mc<DS_SUB_RTN_U64, i64, "atomic_load_sub">;
954defm : DSAtomicRetPat_mc<DS_INC_RTN_U64, i64, "atomic_inc">;
955defm : DSAtomicRetPat_mc<DS_DEC_RTN_U64, i64, "atomic_dec">;
956defm : DSAtomicRetPat_mc<DS_AND_RTN_B64, i64, "atomic_load_and">;
957defm : DSAtomicRetPat_mc<DS_OR_RTN_B64, i64, "atomic_load_or">;
958defm : DSAtomicRetPat_mc<DS_XOR_RTN_B64, i64, "atomic_load_xor">;
959defm : DSAtomicRetPat_mc<DS_MIN_RTN_I64, i64, "atomic_load_min">;
960defm : DSAtomicRetPat_mc<DS_MAX_RTN_I64, i64, "atomic_load_max">;
961defm : DSAtomicRetPat_mc<DS_MIN_RTN_U64, i64, "atomic_load_umin">;
962defm : DSAtomicRetPat_mc<DS_MAX_RTN_U64, i64, "atomic_load_umax">;
963defm : DSAtomicRetPat_mc<DS_MIN_RTN_F64, f64, "atomic_load_fmin">;
964defm : DSAtomicRetPat_mc<DS_MAX_RTN_F64, f64, "atomic_load_fmax">;
965
966defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B64, i64, "atomic_cmp_swap">;
967
968let SubtargetPredicate = isGFX90APlus in {
969def : DSAtomicRetPat<DS_ADD_RTN_F64, f64, atomic_load_fadd_local_64>;
970}
971
972def : Pat <
973  (SIds_ordered_count i32:$value, i16:$offset),
974  (DS_ORDERED_COUNT $value, (as_i16imm $offset))
975>;
976
977//===----------------------------------------------------------------------===//
978// Target-specific instruction encodings.
979//===----------------------------------------------------------------------===//
980
981//===----------------------------------------------------------------------===//
982// Base ENC_DS for GFX6, GFX7, GFX10.
983//===----------------------------------------------------------------------===//
984
985class Base_DS_Real_gfx6_gfx7_gfx10<bits<8> op, DS_Pseudo ps, int ef> :
986    DS_Real<ps>, SIMCInstr <ps.Mnemonic, ef> {
987
988  let Inst{7-0}   = !if(ps.has_offset0, offset0, 0);
989  let Inst{15-8}  = !if(ps.has_offset1, offset1, 0);
990  let Inst{17}    = !if(ps.has_gds, gds, ps.gdsValue);
991  let Inst{25-18} = op;
992  let Inst{31-26} = 0x36;
993  let Inst{39-32} = !if(ps.has_addr, addr, !if(ps.has_gws_data0, data0{7-0}, 0));
994  let Inst{47-40} = !if(ps.has_data0, data0{7-0}, 0);
995  let Inst{55-48} = !if(ps.has_data1, data1{7-0}, 0);
996  let Inst{63-56} = !if(ps.has_vdst, vdst{7-0}, 0);
997}
998
999//===----------------------------------------------------------------------===//
1000// GFX10.
1001//===----------------------------------------------------------------------===//
1002
1003let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
1004  multiclass DS_Real_gfx10<bits<8> op>  {
1005    def _gfx10 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
1006                                              SIEncodingFamily.GFX10>;
1007  }
1008} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
1009
1010defm DS_ADD_F32          : DS_Real_gfx10<0x015>;
1011defm DS_ADD_RTN_F32      : DS_Real_gfx10<0x055>;
1012defm DS_ADD_SRC2_F32     : DS_Real_gfx10<0x095>;
1013defm DS_WRITE_B8_D16_HI  : DS_Real_gfx10<0x0a0>;
1014defm DS_WRITE_B16_D16_HI : DS_Real_gfx10<0x0a1>;
1015defm DS_READ_U8_D16      : DS_Real_gfx10<0x0a2>;
1016defm DS_READ_U8_D16_HI   : DS_Real_gfx10<0x0a3>;
1017defm DS_READ_I8_D16      : DS_Real_gfx10<0x0a4>;
1018defm DS_READ_I8_D16_HI   : DS_Real_gfx10<0x0a5>;
1019defm DS_READ_U16_D16     : DS_Real_gfx10<0x0a6>;
1020defm DS_READ_U16_D16_HI  : DS_Real_gfx10<0x0a7>;
1021defm DS_WRITE_ADDTID_B32 : DS_Real_gfx10<0x0b0>;
1022defm DS_READ_ADDTID_B32  : DS_Real_gfx10<0x0b1>;
1023defm DS_PERMUTE_B32      : DS_Real_gfx10<0x0b2>;
1024defm DS_BPERMUTE_B32     : DS_Real_gfx10<0x0b3>;
1025
1026//===----------------------------------------------------------------------===//
1027// GFX7, GFX10.
1028//===----------------------------------------------------------------------===//
1029
1030let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {
1031  multiclass DS_Real_gfx7<bits<8> op> {
1032    def _gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
1033                                             SIEncodingFamily.SI>;
1034  }
1035} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7"
1036
1037multiclass DS_Real_gfx7_gfx10<bits<8> op> :
1038  DS_Real_gfx7<op>, DS_Real_gfx10<op>;
1039
1040// FIXME-GFX7: Add tests when upstreaming this part.
1041defm DS_GWS_SEMA_RELEASE_ALL : DS_Real_gfx7_gfx10<0x018>;
1042defm DS_WRAP_RTN_B32         : DS_Real_gfx7_gfx10<0x034>;
1043defm DS_CONDXCHG32_RTN_B64   : DS_Real_gfx7_gfx10<0x07e>;
1044defm DS_WRITE_B96            : DS_Real_gfx7_gfx10<0x0de>;
1045defm DS_WRITE_B128           : DS_Real_gfx7_gfx10<0x0df>;
1046defm DS_READ_B96             : DS_Real_gfx7_gfx10<0x0fe>;
1047defm DS_READ_B128            : DS_Real_gfx7_gfx10<0x0ff>;
1048
1049//===----------------------------------------------------------------------===//
1050// GFX6, GFX7, GFX10.
1051//===----------------------------------------------------------------------===//
1052
1053let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
1054  multiclass DS_Real_gfx6_gfx7<bits<8> op> {
1055    def _gfx6_gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
1056                                                  SIEncodingFamily.SI>;
1057  }
1058} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
1059
1060multiclass DS_Real_gfx6_gfx7_gfx10<bits<8> op> :
1061  DS_Real_gfx6_gfx7<op>, DS_Real_gfx10<op>;
1062
1063defm DS_ADD_U32             : DS_Real_gfx6_gfx7_gfx10<0x000>;
1064defm DS_SUB_U32             : DS_Real_gfx6_gfx7_gfx10<0x001>;
1065defm DS_RSUB_U32            : DS_Real_gfx6_gfx7_gfx10<0x002>;
1066defm DS_INC_U32             : DS_Real_gfx6_gfx7_gfx10<0x003>;
1067defm DS_DEC_U32             : DS_Real_gfx6_gfx7_gfx10<0x004>;
1068defm DS_MIN_I32             : DS_Real_gfx6_gfx7_gfx10<0x005>;
1069defm DS_MAX_I32             : DS_Real_gfx6_gfx7_gfx10<0x006>;
1070defm DS_MIN_U32             : DS_Real_gfx6_gfx7_gfx10<0x007>;
1071defm DS_MAX_U32             : DS_Real_gfx6_gfx7_gfx10<0x008>;
1072defm DS_AND_B32             : DS_Real_gfx6_gfx7_gfx10<0x009>;
1073defm DS_OR_B32              : DS_Real_gfx6_gfx7_gfx10<0x00a>;
1074defm DS_XOR_B32             : DS_Real_gfx6_gfx7_gfx10<0x00b>;
1075defm DS_MSKOR_B32           : DS_Real_gfx6_gfx7_gfx10<0x00c>;
1076defm DS_WRITE_B32           : DS_Real_gfx6_gfx7_gfx10<0x00d>;
1077defm DS_WRITE2_B32          : DS_Real_gfx6_gfx7_gfx10<0x00e>;
1078defm DS_WRITE2ST64_B32      : DS_Real_gfx6_gfx7_gfx10<0x00f>;
1079defm DS_CMPST_B32           : DS_Real_gfx6_gfx7_gfx10<0x010>;
1080defm DS_CMPST_F32           : DS_Real_gfx6_gfx7_gfx10<0x011>;
1081defm DS_MIN_F32             : DS_Real_gfx6_gfx7_gfx10<0x012>;
1082defm DS_MAX_F32             : DS_Real_gfx6_gfx7_gfx10<0x013>;
1083defm DS_NOP                 : DS_Real_gfx6_gfx7_gfx10<0x014>;
1084defm DS_GWS_INIT            : DS_Real_gfx6_gfx7_gfx10<0x019>;
1085defm DS_GWS_SEMA_V          : DS_Real_gfx6_gfx7_gfx10<0x01a>;
1086defm DS_GWS_SEMA_BR         : DS_Real_gfx6_gfx7_gfx10<0x01b>;
1087defm DS_GWS_SEMA_P          : DS_Real_gfx6_gfx7_gfx10<0x01c>;
1088defm DS_GWS_BARRIER         : DS_Real_gfx6_gfx7_gfx10<0x01d>;
1089defm DS_WRITE_B8            : DS_Real_gfx6_gfx7_gfx10<0x01e>;
1090defm DS_WRITE_B16           : DS_Real_gfx6_gfx7_gfx10<0x01f>;
1091defm DS_ADD_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x020>;
1092defm DS_SUB_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x021>;
1093defm DS_RSUB_RTN_U32        : DS_Real_gfx6_gfx7_gfx10<0x022>;
1094defm DS_INC_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x023>;
1095defm DS_DEC_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x024>;
1096defm DS_MIN_RTN_I32         : DS_Real_gfx6_gfx7_gfx10<0x025>;
1097defm DS_MAX_RTN_I32         : DS_Real_gfx6_gfx7_gfx10<0x026>;
1098defm DS_MIN_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x027>;
1099defm DS_MAX_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x028>;
1100defm DS_AND_RTN_B32         : DS_Real_gfx6_gfx7_gfx10<0x029>;
1101defm DS_OR_RTN_B32          : DS_Real_gfx6_gfx7_gfx10<0x02a>;
1102defm DS_XOR_RTN_B32         : DS_Real_gfx6_gfx7_gfx10<0x02b>;
1103defm DS_MSKOR_RTN_B32       : DS_Real_gfx6_gfx7_gfx10<0x02c>;
1104defm DS_WRXCHG_RTN_B32      : DS_Real_gfx6_gfx7_gfx10<0x02d>;
1105defm DS_WRXCHG2_RTN_B32     : DS_Real_gfx6_gfx7_gfx10<0x02e>;
1106defm DS_WRXCHG2ST64_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02f>;
1107defm DS_CMPST_RTN_B32       : DS_Real_gfx6_gfx7_gfx10<0x030>;
1108defm DS_CMPST_RTN_F32       : DS_Real_gfx6_gfx7_gfx10<0x031>;
1109defm DS_MIN_RTN_F32         : DS_Real_gfx6_gfx7_gfx10<0x032>;
1110defm DS_MAX_RTN_F32         : DS_Real_gfx6_gfx7_gfx10<0x033>;
1111defm DS_SWIZZLE_B32         : DS_Real_gfx6_gfx7_gfx10<0x035>;
1112defm DS_READ_B32            : DS_Real_gfx6_gfx7_gfx10<0x036>;
1113defm DS_READ2_B32           : DS_Real_gfx6_gfx7_gfx10<0x037>;
1114defm DS_READ2ST64_B32       : DS_Real_gfx6_gfx7_gfx10<0x038>;
1115defm DS_READ_I8             : DS_Real_gfx6_gfx7_gfx10<0x039>;
1116defm DS_READ_U8             : DS_Real_gfx6_gfx7_gfx10<0x03a>;
1117defm DS_READ_I16            : DS_Real_gfx6_gfx7_gfx10<0x03b>;
1118defm DS_READ_U16            : DS_Real_gfx6_gfx7_gfx10<0x03c>;
1119defm DS_CONSUME             : DS_Real_gfx6_gfx7_gfx10<0x03d>;
1120defm DS_APPEND              : DS_Real_gfx6_gfx7_gfx10<0x03e>;
1121defm DS_ORDERED_COUNT       : DS_Real_gfx6_gfx7_gfx10<0x03f>;
1122defm DS_ADD_U64             : DS_Real_gfx6_gfx7_gfx10<0x040>;
1123defm DS_SUB_U64             : DS_Real_gfx6_gfx7_gfx10<0x041>;
1124defm DS_RSUB_U64            : DS_Real_gfx6_gfx7_gfx10<0x042>;
1125defm DS_INC_U64             : DS_Real_gfx6_gfx7_gfx10<0x043>;
1126defm DS_DEC_U64             : DS_Real_gfx6_gfx7_gfx10<0x044>;
1127defm DS_MIN_I64             : DS_Real_gfx6_gfx7_gfx10<0x045>;
1128defm DS_MAX_I64             : DS_Real_gfx6_gfx7_gfx10<0x046>;
1129defm DS_MIN_U64             : DS_Real_gfx6_gfx7_gfx10<0x047>;
1130defm DS_MAX_U64             : DS_Real_gfx6_gfx7_gfx10<0x048>;
1131defm DS_AND_B64             : DS_Real_gfx6_gfx7_gfx10<0x049>;
1132defm DS_OR_B64              : DS_Real_gfx6_gfx7_gfx10<0x04a>;
1133defm DS_XOR_B64             : DS_Real_gfx6_gfx7_gfx10<0x04b>;
1134defm DS_MSKOR_B64           : DS_Real_gfx6_gfx7_gfx10<0x04c>;
1135defm DS_WRITE_B64           : DS_Real_gfx6_gfx7_gfx10<0x04d>;
1136defm DS_WRITE2_B64          : DS_Real_gfx6_gfx7_gfx10<0x04e>;
1137defm DS_WRITE2ST64_B64      : DS_Real_gfx6_gfx7_gfx10<0x04f>;
1138defm DS_CMPST_B64           : DS_Real_gfx6_gfx7_gfx10<0x050>;
1139defm DS_CMPST_F64           : DS_Real_gfx6_gfx7_gfx10<0x051>;
1140defm DS_MIN_F64             : DS_Real_gfx6_gfx7_gfx10<0x052>;
1141defm DS_MAX_F64             : DS_Real_gfx6_gfx7_gfx10<0x053>;
1142defm DS_ADD_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x060>;
1143defm DS_SUB_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x061>;
1144defm DS_RSUB_RTN_U64        : DS_Real_gfx6_gfx7_gfx10<0x062>;
1145defm DS_INC_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x063>;
1146defm DS_DEC_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x064>;
1147defm DS_MIN_RTN_I64         : DS_Real_gfx6_gfx7_gfx10<0x065>;
1148defm DS_MAX_RTN_I64         : DS_Real_gfx6_gfx7_gfx10<0x066>;
1149defm DS_MIN_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x067>;
1150defm DS_MAX_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x068>;
1151defm DS_AND_RTN_B64         : DS_Real_gfx6_gfx7_gfx10<0x069>;
1152defm DS_OR_RTN_B64          : DS_Real_gfx6_gfx7_gfx10<0x06a>;
1153defm DS_XOR_RTN_B64         : DS_Real_gfx6_gfx7_gfx10<0x06b>;
1154defm DS_MSKOR_RTN_B64       : DS_Real_gfx6_gfx7_gfx10<0x06c>;
1155defm DS_WRXCHG_RTN_B64      : DS_Real_gfx6_gfx7_gfx10<0x06d>;
1156defm DS_WRXCHG2_RTN_B64     : DS_Real_gfx6_gfx7_gfx10<0x06e>;
1157defm DS_WRXCHG2ST64_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06f>;
1158defm DS_CMPST_RTN_B64       : DS_Real_gfx6_gfx7_gfx10<0x070>;
1159defm DS_CMPST_RTN_F64       : DS_Real_gfx6_gfx7_gfx10<0x071>;
1160defm DS_MIN_RTN_F64         : DS_Real_gfx6_gfx7_gfx10<0x072>;
1161defm DS_MAX_RTN_F64         : DS_Real_gfx6_gfx7_gfx10<0x073>;
1162defm DS_READ_B64            : DS_Real_gfx6_gfx7_gfx10<0x076>;
1163defm DS_READ2_B64           : DS_Real_gfx6_gfx7_gfx10<0x077>;
1164defm DS_READ2ST64_B64       : DS_Real_gfx6_gfx7_gfx10<0x078>;
1165defm DS_ADD_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x080>;
1166defm DS_SUB_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x081>;
1167defm DS_RSUB_SRC2_U32       : DS_Real_gfx6_gfx7_gfx10<0x082>;
1168defm DS_INC_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x083>;
1169defm DS_DEC_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x084>;
1170defm DS_MIN_SRC2_I32        : DS_Real_gfx6_gfx7_gfx10<0x085>;
1171defm DS_MAX_SRC2_I32        : DS_Real_gfx6_gfx7_gfx10<0x086>;
1172defm DS_MIN_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x087>;
1173defm DS_MAX_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x088>;
1174defm DS_AND_SRC2_B32        : DS_Real_gfx6_gfx7_gfx10<0x089>;
1175defm DS_OR_SRC2_B32         : DS_Real_gfx6_gfx7_gfx10<0x08a>;
1176defm DS_XOR_SRC2_B32        : DS_Real_gfx6_gfx7_gfx10<0x08b>;
1177defm DS_WRITE_SRC2_B32      : DS_Real_gfx6_gfx7_gfx10<0x08d>;
1178defm DS_MIN_SRC2_F32        : DS_Real_gfx6_gfx7_gfx10<0x092>;
1179defm DS_MAX_SRC2_F32        : DS_Real_gfx6_gfx7_gfx10<0x093>;
1180defm DS_ADD_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c0>;
1181defm DS_SUB_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c1>;
1182defm DS_RSUB_SRC2_U64       : DS_Real_gfx6_gfx7_gfx10<0x0c2>;
1183defm DS_INC_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c3>;
1184defm DS_DEC_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c4>;
1185defm DS_MIN_SRC2_I64        : DS_Real_gfx6_gfx7_gfx10<0x0c5>;
1186defm DS_MAX_SRC2_I64        : DS_Real_gfx6_gfx7_gfx10<0x0c6>;
1187defm DS_MIN_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c7>;
1188defm DS_MAX_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c8>;
1189defm DS_AND_SRC2_B64        : DS_Real_gfx6_gfx7_gfx10<0x0c9>;
1190defm DS_OR_SRC2_B64         : DS_Real_gfx6_gfx7_gfx10<0x0ca>;
1191defm DS_XOR_SRC2_B64        : DS_Real_gfx6_gfx7_gfx10<0x0cb>;
1192defm DS_WRITE_SRC2_B64      : DS_Real_gfx6_gfx7_gfx10<0x0cd>;
1193defm DS_MIN_SRC2_F64        : DS_Real_gfx6_gfx7_gfx10<0x0d2>;
1194defm DS_MAX_SRC2_F64        : DS_Real_gfx6_gfx7_gfx10<0x0d3>;
1195
1196//===----------------------------------------------------------------------===//
1197// GFX8, GFX9 (VI).
1198//===----------------------------------------------------------------------===//
1199
1200class DS_Real_vi <bits<8> op, DS_Pseudo ps> :
1201  DS_Real <ps>,
1202  SIMCInstr <ps.Mnemonic, SIEncodingFamily.VI> {
1203  let AssemblerPredicate = isGFX8GFX9;
1204  let DecoderNamespace = "GFX8";
1205
1206  // encoding
1207  let Inst{7-0}   = !if(ps.has_offset0, offset0, 0);
1208  let Inst{15-8}  = !if(ps.has_offset1, offset1, 0);
1209  let Inst{16}    = !if(ps.has_gds, gds, ps.gdsValue);
1210  let Inst{24-17} = op;
1211  let Inst{25}    = acc;
1212  let Inst{31-26} = 0x36; // ds prefix
1213  let Inst{39-32} = !if(ps.has_addr, addr, !if(ps.has_gws_data0, data0{7-0}, 0));
1214  let Inst{47-40} = !if(ps.has_data0, data0{7-0}, 0);
1215  let Inst{55-48} = !if(ps.has_data1, data1{7-0}, 0);
1216  let Inst{63-56} = !if(ps.has_vdst, vdst{7-0}, 0);
1217}
1218
1219def DS_ADD_U32_vi         : DS_Real_vi<0x0,  DS_ADD_U32>;
1220def DS_SUB_U32_vi         : DS_Real_vi<0x1,  DS_SUB_U32>;
1221def DS_RSUB_U32_vi        : DS_Real_vi<0x2,  DS_RSUB_U32>;
1222def DS_INC_U32_vi         : DS_Real_vi<0x3,  DS_INC_U32>;
1223def DS_DEC_U32_vi         : DS_Real_vi<0x4,  DS_DEC_U32>;
1224def DS_MIN_I32_vi         : DS_Real_vi<0x5,  DS_MIN_I32>;
1225def DS_MAX_I32_vi         : DS_Real_vi<0x6,  DS_MAX_I32>;
1226def DS_MIN_U32_vi         : DS_Real_vi<0x7,  DS_MIN_U32>;
1227def DS_MAX_U32_vi         : DS_Real_vi<0x8,  DS_MAX_U32>;
1228def DS_AND_B32_vi         : DS_Real_vi<0x9,  DS_AND_B32>;
1229def DS_OR_B32_vi          : DS_Real_vi<0xa,  DS_OR_B32>;
1230def DS_XOR_B32_vi         : DS_Real_vi<0xb,  DS_XOR_B32>;
1231def DS_MSKOR_B32_vi       : DS_Real_vi<0xc,  DS_MSKOR_B32>;
1232def DS_WRITE_B32_vi       : DS_Real_vi<0xd,  DS_WRITE_B32>;
1233def DS_WRITE2_B32_vi      : DS_Real_vi<0xe,  DS_WRITE2_B32>;
1234def DS_WRITE2ST64_B32_vi  : DS_Real_vi<0xf,  DS_WRITE2ST64_B32>;
1235def DS_CMPST_B32_vi       : DS_Real_vi<0x10, DS_CMPST_B32>;
1236def DS_CMPST_F32_vi       : DS_Real_vi<0x11, DS_CMPST_F32>;
1237def DS_MIN_F32_vi         : DS_Real_vi<0x12, DS_MIN_F32>;
1238def DS_MAX_F32_vi         : DS_Real_vi<0x13, DS_MAX_F32>;
1239def DS_NOP_vi             : DS_Real_vi<0x14, DS_NOP>;
1240def DS_ADD_F32_vi         : DS_Real_vi<0x15, DS_ADD_F32>;
1241def DS_GWS_INIT_vi        : DS_Real_vi<0x99, DS_GWS_INIT>;
1242def DS_GWS_SEMA_V_vi      : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
1243def DS_GWS_SEMA_BR_vi     : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
1244def DS_GWS_SEMA_P_vi      : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
1245def DS_GWS_BARRIER_vi     : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
1246def DS_WRITE_ADDTID_B32_vi : DS_Real_vi<0x1d, DS_WRITE_ADDTID_B32>;
1247def DS_WRITE_B8_vi        : DS_Real_vi<0x1e, DS_WRITE_B8>;
1248def DS_WRITE_B16_vi       : DS_Real_vi<0x1f, DS_WRITE_B16>;
1249def DS_ADD_RTN_U32_vi     : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
1250def DS_SUB_RTN_U32_vi     : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
1251def DS_RSUB_RTN_U32_vi    : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
1252def DS_INC_RTN_U32_vi     : DS_Real_vi<0x23, DS_INC_RTN_U32>;
1253def DS_DEC_RTN_U32_vi     : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
1254def DS_MIN_RTN_I32_vi     : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
1255def DS_MAX_RTN_I32_vi     : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
1256def DS_MIN_RTN_U32_vi     : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
1257def DS_MAX_RTN_U32_vi     : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
1258def DS_AND_RTN_B32_vi     : DS_Real_vi<0x29, DS_AND_RTN_B32>;
1259def DS_OR_RTN_B32_vi      : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
1260def DS_XOR_RTN_B32_vi     : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
1261def DS_MSKOR_RTN_B32_vi   : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
1262def DS_WRXCHG_RTN_B32_vi  : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
1263def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
1264def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
1265def DS_CMPST_RTN_B32_vi   : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
1266def DS_CMPST_RTN_F32_vi   : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
1267def DS_MIN_RTN_F32_vi     : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
1268def DS_MAX_RTN_F32_vi     : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
1269def DS_WRAP_RTN_B32_vi    : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
1270def DS_ADD_RTN_F32_vi     : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
1271def DS_READ_B32_vi        : DS_Real_vi<0x36, DS_READ_B32>;
1272def DS_READ2_B32_vi       : DS_Real_vi<0x37, DS_READ2_B32>;
1273def DS_READ2ST64_B32_vi   : DS_Real_vi<0x38, DS_READ2ST64_B32>;
1274def DS_READ_I8_vi         : DS_Real_vi<0x39, DS_READ_I8>;
1275def DS_READ_U8_vi         : DS_Real_vi<0x3a, DS_READ_U8>;
1276def DS_READ_I16_vi        : DS_Real_vi<0x3b, DS_READ_I16>;
1277def DS_READ_U16_vi        : DS_Real_vi<0x3c, DS_READ_U16>;
1278def DS_READ_ADDTID_B32_vi : DS_Real_vi<0xb6, DS_READ_ADDTID_B32>;
1279def DS_CONSUME_vi         : DS_Real_vi<0xbd, DS_CONSUME>;
1280def DS_APPEND_vi          : DS_Real_vi<0xbe, DS_APPEND>;
1281def DS_ORDERED_COUNT_vi   : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
1282def DS_SWIZZLE_B32_vi     : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
1283def DS_PERMUTE_B32_vi     : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
1284def DS_BPERMUTE_B32_vi    : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
1285
1286def DS_ADD_U64_vi         : DS_Real_vi<0x40, DS_ADD_U64>;
1287def DS_SUB_U64_vi         : DS_Real_vi<0x41, DS_SUB_U64>;
1288def DS_RSUB_U64_vi        : DS_Real_vi<0x42, DS_RSUB_U64>;
1289def DS_INC_U64_vi         : DS_Real_vi<0x43, DS_INC_U64>;
1290def DS_DEC_U64_vi         : DS_Real_vi<0x44, DS_DEC_U64>;
1291def DS_MIN_I64_vi         : DS_Real_vi<0x45, DS_MIN_I64>;
1292def DS_MAX_I64_vi         : DS_Real_vi<0x46, DS_MAX_I64>;
1293def DS_MIN_U64_vi         : DS_Real_vi<0x47, DS_MIN_U64>;
1294def DS_MAX_U64_vi         : DS_Real_vi<0x48, DS_MAX_U64>;
1295def DS_AND_B64_vi         : DS_Real_vi<0x49, DS_AND_B64>;
1296def DS_OR_B64_vi          : DS_Real_vi<0x4a, DS_OR_B64>;
1297def DS_XOR_B64_vi         : DS_Real_vi<0x4b, DS_XOR_B64>;
1298def DS_MSKOR_B64_vi       : DS_Real_vi<0x4c, DS_MSKOR_B64>;
1299def DS_WRITE_B64_vi       : DS_Real_vi<0x4d, DS_WRITE_B64>;
1300def DS_WRITE2_B64_vi      : DS_Real_vi<0x4E, DS_WRITE2_B64>;
1301def DS_WRITE2ST64_B64_vi  : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
1302def DS_CMPST_B64_vi       : DS_Real_vi<0x50, DS_CMPST_B64>;
1303def DS_CMPST_F64_vi       : DS_Real_vi<0x51, DS_CMPST_F64>;
1304def DS_MIN_F64_vi         : DS_Real_vi<0x52, DS_MIN_F64>;
1305def DS_MAX_F64_vi         : DS_Real_vi<0x53, DS_MAX_F64>;
1306
1307def DS_WRITE_B8_D16_HI_vi  : DS_Real_vi<0x54, DS_WRITE_B8_D16_HI>;
1308def DS_WRITE_B16_D16_HI_vi : DS_Real_vi<0x55, DS_WRITE_B16_D16_HI>;
1309
1310def DS_READ_U8_D16_vi     : DS_Real_vi<0x56, DS_READ_U8_D16>;
1311def DS_READ_U8_D16_HI_vi  : DS_Real_vi<0x57, DS_READ_U8_D16_HI>;
1312def DS_READ_I8_D16_vi     : DS_Real_vi<0x58, DS_READ_I8_D16>;
1313def DS_READ_I8_D16_HI_vi  : DS_Real_vi<0x59, DS_READ_I8_D16_HI>;
1314def DS_READ_U16_D16_vi    : DS_Real_vi<0x5a, DS_READ_U16_D16>;
1315def DS_READ_U16_D16_HI_vi : DS_Real_vi<0x5b, DS_READ_U16_D16_HI>;
1316
1317def DS_ADD_RTN_U64_vi     : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
1318def DS_SUB_RTN_U64_vi     : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
1319def DS_RSUB_RTN_U64_vi    : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
1320def DS_INC_RTN_U64_vi     : DS_Real_vi<0x63, DS_INC_RTN_U64>;
1321def DS_DEC_RTN_U64_vi     : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
1322def DS_MIN_RTN_I64_vi     : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
1323def DS_MAX_RTN_I64_vi     : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
1324def DS_MIN_RTN_U64_vi     : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
1325def DS_MAX_RTN_U64_vi     : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
1326def DS_AND_RTN_B64_vi     : DS_Real_vi<0x69, DS_AND_RTN_B64>;
1327def DS_OR_RTN_B64_vi      : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
1328def DS_XOR_RTN_B64_vi     : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
1329def DS_MSKOR_RTN_B64_vi   : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
1330def DS_WRXCHG_RTN_B64_vi  : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
1331def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
1332def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
1333def DS_CONDXCHG32_RTN_B64_vi   : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
1334def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
1335def DS_CMPST_RTN_B64_vi   : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
1336def DS_CMPST_RTN_F64_vi   : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
1337def DS_MIN_RTN_F64_vi     : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
1338def DS_MAX_RTN_F64_vi     : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
1339
1340def DS_READ_B64_vi        : DS_Real_vi<0x76, DS_READ_B64>;
1341def DS_READ2_B64_vi       : DS_Real_vi<0x77, DS_READ2_B64>;
1342def DS_READ2ST64_B64_vi   : DS_Real_vi<0x78, DS_READ2ST64_B64>;
1343
1344def DS_ADD_SRC2_U32_vi    : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
1345def DS_SUB_SRC2_U32_vi    : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
1346def DS_RSUB_SRC2_U32_vi   : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
1347def DS_INC_SRC2_U32_vi    : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
1348def DS_DEC_SRC2_U32_vi    : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
1349def DS_MIN_SRC2_I32_vi    : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
1350def DS_MAX_SRC2_I32_vi    : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
1351def DS_MIN_SRC2_U32_vi    : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
1352def DS_MAX_SRC2_U32_vi    : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
1353def DS_AND_SRC2_B32_vi    : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
1354def DS_OR_SRC2_B32_vi     : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
1355def DS_XOR_SRC2_B32_vi    : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
1356def DS_WRITE_SRC2_B32_vi  : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
1357def DS_MIN_SRC2_F32_vi    : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
1358def DS_MAX_SRC2_F32_vi    : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
1359def DS_ADD_SRC2_F32_vi    : DS_Real_vi<0x95, DS_ADD_SRC2_F32>;
1360def DS_ADD_SRC2_U64_vi    : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
1361def DS_SUB_SRC2_U64_vi    : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
1362def DS_RSUB_SRC2_U64_vi   : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
1363def DS_INC_SRC2_U64_vi    : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
1364def DS_DEC_SRC2_U64_vi    : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
1365def DS_MIN_SRC2_I64_vi    : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
1366def DS_MAX_SRC2_I64_vi    : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
1367def DS_MIN_SRC2_U64_vi    : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
1368def DS_MAX_SRC2_U64_vi    : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
1369def DS_AND_SRC2_B64_vi    : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
1370def DS_OR_SRC2_B64_vi     : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
1371def DS_XOR_SRC2_B64_vi    : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
1372def DS_WRITE_SRC2_B64_vi  : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
1373def DS_MIN_SRC2_F64_vi    : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
1374def DS_MAX_SRC2_F64_vi    : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
1375def DS_WRITE_B96_vi       : DS_Real_vi<0xde, DS_WRITE_B96>;
1376def DS_WRITE_B128_vi      : DS_Real_vi<0xdf, DS_WRITE_B128>;
1377def DS_READ_B96_vi        : DS_Real_vi<0xfe, DS_READ_B96>;
1378def DS_READ_B128_vi       : DS_Real_vi<0xff, DS_READ_B128>;
1379
1380let SubtargetPredicate = isGFX90APlus in {
1381  def DS_ADD_F64_vi     : DS_Real_vi<0x5c, DS_ADD_F64>;
1382  def DS_ADD_RTN_F64_vi : DS_Real_vi<0x7c, DS_ADD_RTN_F64>;
1383} // End SubtargetPredicate = isGFX90APlus
1384