xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/DSInstructions.td (revision 8bcb0991864975618c09697b1aca10683346d9f0) 
1//===-- DSInstructions.td - DS Instruction Defintions ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
10  InstSI <outs, ins, "", pattern>,
11  SIMCInstr <opName, SIEncodingFamily.NONE> {
12
13  let LGKM_CNT = 1;
14  let DS = 1;
15  let Size = 8;
16  let UseNamedOperandTable = 1;
17
18  // Most instruction load and store data, so set this as the default.
19  let mayLoad = 1;
20  let mayStore = 1;
21  let maybeAtomic = 1;
22
23  let hasSideEffects = 0;
24  let SchedRW = [WriteLDS];
25
26  let isPseudo = 1;
27  let isCodeGenOnly = 1;
28
29  let AsmMatchConverter = "cvtDS";
30
31  string Mnemonic = opName;
32  string AsmOperands = asmOps;
33
34  // Well these bits a kind of hack because it would be more natural
35  // to test "outs" and "ins" dags for the presence of particular operands
36  bits<1> has_vdst = 1;
37  bits<1> has_addr = 1;
38  bits<1> has_data0 = 1;
39  bits<1> has_data1 = 1;
40
41  bits<1> has_gws_data0 = 0; // data0 is encoded as addr
42
43  bits<1> has_offset  = 1; // has "offset" that should be split to offset0,1
44  bits<1> has_offset0 = 1;
45  bits<1> has_offset1 = 1;
46
47  bits<1> has_gds = 1;
48  bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
49
50  bits<1> has_m0_read = 1;
51
52  let Uses = !if(has_m0_read, [M0, EXEC], [EXEC]);
53}
54
55class DS_Real <DS_Pseudo ds> :
56  InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
57  Enc64 {
58
59  let isPseudo = 0;
60  let isCodeGenOnly = 0;
61
62  // copy relevant pseudo op flags
63  let SubtargetPredicate = ds.SubtargetPredicate;
64  let OtherPredicates = ds.OtherPredicates;
65  let AsmMatchConverter  = ds.AsmMatchConverter;
66
67  // encoding fields
68  bits<8> vdst;
69  bits<1> gds;
70  bits<8> addr;
71  bits<8> data0;
72  bits<8> data1;
73  bits<8> offset0;
74  bits<8> offset1;
75
76  bits<16> offset;
77  let offset0 = !if(ds.has_offset, offset{7-0}, ?);
78  let offset1 = !if(ds.has_offset, offset{15-8}, ?);
79}
80
81
82// DS Pseudo instructions
83
84class DS_0A1D_NORET<string opName, RegisterClass rc = VGPR_32>
85: DS_Pseudo<opName,
86  (outs),
87  (ins rc:$data0, offset:$offset, gds:$gds),
88  "$data0$offset$gds"> {
89
90  let has_addr = 0;
91  let has_data1 = 0;
92  let has_vdst = 0;
93}
94
95class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
96: DS_Pseudo<opName,
97  (outs),
98  (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
99  "$addr, $data0$offset$gds"> {
100
101  let has_data1 = 0;
102  let has_vdst = 0;
103}
104
105multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
106  def "" : DS_1A1D_NORET<opName, rc>,
107           AtomicNoRet<opName, 0>;
108
109  let has_m0_read = 0 in {
110    def _gfx9 : DS_1A1D_NORET<opName, rc>,
111                AtomicNoRet<opName#"_gfx9", 0>;
112  }
113}
114
115class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
116: DS_Pseudo<opName,
117  (outs),
118  (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
119  "$addr, $data0, $data1"#"$offset"#"$gds"> {
120
121  let has_vdst = 0;
122}
123
124multiclass DS_1A2D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
125  def "" : DS_1A2D_NORET<opName, rc>,
126           AtomicNoRet<opName, 0>;
127
128  let has_m0_read = 0 in {
129    def _gfx9 : DS_1A2D_NORET<opName, rc>,
130                AtomicNoRet<opName#"_gfx9", 0>;
131  }
132}
133
134class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
135: DS_Pseudo<opName,
136  (outs),
137  (ins VGPR_32:$addr, rc:$data0, rc:$data1,
138       offset0:$offset0, offset1:$offset1, gds:$gds),
139  "$addr, $data0, $data1$offset0$offset1$gds"> {
140
141  let has_vdst = 0;
142  let has_offset = 0;
143  let AsmMatchConverter = "cvtDSOffset01";
144}
145
146multiclass DS_1A2D_Off8_NORET_mc <string opName, RegisterClass rc = VGPR_32> {
147  def "" : DS_1A2D_Off8_NORET<opName, rc>;
148
149  let has_m0_read = 0 in {
150    def _gfx9 : DS_1A2D_Off8_NORET<opName, rc>;
151  }
152}
153
154class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
155: DS_Pseudo<opName,
156  (outs rc:$vdst),
157  (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
158  "$vdst, $addr, $data0$offset$gds"> {
159
160  let hasPostISelHook = 1;
161  let has_data1 = 0;
162}
163
164multiclass DS_1A1D_RET_mc <string opName, RegisterClass rc = VGPR_32,
165                           string NoRetOp = ""> {
166  def "" : DS_1A1D_RET<opName, rc>,
167    AtomicNoRet<NoRetOp, !if(!eq(NoRetOp, ""), 0, 1)>;
168
169  let has_m0_read = 0 in {
170    def _gfx9 : DS_1A1D_RET<opName, rc>,
171      AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp#"_gfx9"),
172                  !if(!eq(NoRetOp, ""), 0, 1)>;
173  }
174}
175
176class DS_1A2D_RET<string opName,
177                  RegisterClass rc = VGPR_32,
178                  RegisterClass src = rc>
179: DS_Pseudo<opName,
180  (outs rc:$vdst),
181  (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
182  "$vdst, $addr, $data0, $data1$offset$gds"> {
183
184  let hasPostISelHook = 1;
185}
186
187multiclass DS_1A2D_RET_mc<string opName,
188                          RegisterClass rc = VGPR_32,
189                          string NoRetOp = "",
190                          RegisterClass src = rc> {
191  def "" : DS_1A2D_RET<opName, rc, src>,
192    AtomicNoRet<NoRetOp, !if(!eq(NoRetOp, ""), 0, 1)>;
193
194  let has_m0_read = 0 in {
195    def _gfx9 : DS_1A2D_RET<opName, rc, src>,
196      AtomicNoRet<NoRetOp#"_gfx9", !if(!eq(NoRetOp, ""), 0, 1)>;
197  }
198}
199
200class DS_1A2D_Off8_RET<string opName,
201                       RegisterClass rc = VGPR_32,
202                       RegisterClass src = rc>
203: DS_Pseudo<opName,
204  (outs rc:$vdst),
205  (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
206  "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
207
208  let has_offset = 0;
209  let AsmMatchConverter = "cvtDSOffset01";
210
211  let hasPostISelHook = 1;
212}
213
214multiclass DS_1A2D_Off8_RET_mc<string opName,
215                               RegisterClass rc = VGPR_32,
216                               RegisterClass src = rc> {
217  def "" : DS_1A2D_Off8_RET<opName, rc, src>;
218
219  let has_m0_read = 0 in {
220    def _gfx9 : DS_1A2D_Off8_RET<opName, rc, src>;
221  }
222}
223
224
225class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset>
226: DS_Pseudo<opName,
227  (outs rc:$vdst),
228  !if(HasTiedOutput,
229    (ins VGPR_32:$addr, ofs:$offset, gds:$gds, rc:$vdst_in),
230    (ins VGPR_32:$addr, ofs:$offset, gds:$gds)),
231  "$vdst, $addr$offset$gds"> {
232  let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
233  let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
234  let has_data0 = 0;
235  let has_data1 = 0;
236}
237
238multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> {
239  def "" : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
240
241  let has_m0_read = 0 in {
242    def _gfx9 : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
243  }
244}
245
246class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> :
247  DS_1A_RET<opName, rc, 1>;
248
249class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
250: DS_Pseudo<opName,
251  (outs rc:$vdst),
252  (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
253  "$vdst, $addr$offset0$offset1$gds"> {
254
255  let has_offset = 0;
256  let has_data0 = 0;
257  let has_data1 = 0;
258  let AsmMatchConverter = "cvtDSOffset01";
259}
260
261multiclass DS_1A_Off8_RET_mc <string opName, RegisterClass rc = VGPR_32> {
262  def "" : DS_1A_Off8_RET<opName, rc>;
263
264  let has_m0_read = 0 in {
265    def _gfx9 : DS_1A_Off8_RET<opName, rc>;
266  }
267}
268
269class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
270  (outs VGPR_32:$vdst),
271  (ins VGPR_32:$addr, offset:$offset),
272  "$vdst, $addr$offset gds"> {
273
274  let has_data0 = 0;
275  let has_data1 = 0;
276  let has_gds = 0;
277  let gdsValue = 1;
278  let AsmMatchConverter = "cvtDSGds";
279}
280
281class DS_0A_RET <string opName> : DS_Pseudo<opName,
282  (outs VGPR_32:$vdst),
283  (ins offset:$offset, gds:$gds),
284  "$vdst$offset$gds"> {
285
286  let mayLoad = 1;
287  let mayStore = 1;
288
289  let has_addr = 0;
290  let has_data0 = 0;
291  let has_data1 = 0;
292}
293
294class DS_1A <string opName> : DS_Pseudo<opName,
295  (outs),
296  (ins VGPR_32:$addr, offset:$offset, gds:$gds),
297  "$addr$offset$gds"> {
298
299  let mayLoad = 1;
300  let mayStore = 1;
301
302  let has_vdst = 0;
303  let has_data0 = 0;
304  let has_data1 = 0;
305}
306
307multiclass DS_1A_mc <string opName> {
308  def "" : DS_1A<opName>;
309
310  let has_m0_read = 0 in {
311    def _gfx9 : DS_1A<opName>;
312  }
313}
314
315
316class DS_GWS <string opName, dag ins, string asmOps>
317: DS_Pseudo<opName, (outs), ins, asmOps> {
318
319  let has_vdst  = 0;
320  let has_addr  = 0;
321  let has_data0 = 0;
322  let has_data1 = 0;
323
324  let has_gds   = 0;
325  let gdsValue  = 1;
326  let AsmMatchConverter = "cvtDSGds";
327}
328
329class DS_GWS_0D <string opName>
330: DS_GWS<opName,
331  (ins offset:$offset, gds:$gds), "$offset gds"> {
332  let hasSideEffects = 1;
333}
334
335class DS_GWS_1D <string opName>
336: DS_GWS<opName,
337  (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
338
339  let has_gws_data0 = 1;
340  let hasSideEffects = 1;
341}
342
343class DS_VOID <string opName> : DS_Pseudo<opName,
344  (outs), (ins), ""> {
345  let mayLoad = 0;
346  let mayStore = 0;
347  let hasSideEffects = 1;
348  let UseNamedOperandTable = 0;
349  let AsmMatchConverter = "";
350
351  let has_vdst = 0;
352  let has_addr = 0;
353  let has_data0 = 0;
354  let has_data1 = 0;
355  let has_offset = 0;
356  let has_offset0 = 0;
357  let has_offset1 = 0;
358  let has_gds = 0;
359}
360
361class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
362: DS_Pseudo<opName,
363  (outs VGPR_32:$vdst),
364  (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
365  "$vdst, $addr, $data0$offset",
366  [(set i32:$vdst,
367   (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
368
369  let mayLoad = 0;
370  let mayStore = 0;
371  let isConvergent = 1;
372
373  let has_data1 = 0;
374  let has_gds = 0;
375}
376
377defm DS_ADD_U32       : DS_1A1D_NORET_mc<"ds_add_u32">;
378defm DS_SUB_U32       : DS_1A1D_NORET_mc<"ds_sub_u32">;
379defm DS_RSUB_U32      : DS_1A1D_NORET_mc<"ds_rsub_u32">;
380defm DS_INC_U32       : DS_1A1D_NORET_mc<"ds_inc_u32">;
381defm DS_DEC_U32       : DS_1A1D_NORET_mc<"ds_dec_u32">;
382defm DS_MIN_I32       : DS_1A1D_NORET_mc<"ds_min_i32">;
383defm DS_MAX_I32       : DS_1A1D_NORET_mc<"ds_max_i32">;
384defm DS_MIN_U32       : DS_1A1D_NORET_mc<"ds_min_u32">;
385defm DS_MAX_U32       : DS_1A1D_NORET_mc<"ds_max_u32">;
386defm DS_AND_B32       : DS_1A1D_NORET_mc<"ds_and_b32">;
387defm DS_OR_B32        : DS_1A1D_NORET_mc<"ds_or_b32">;
388defm DS_XOR_B32       : DS_1A1D_NORET_mc<"ds_xor_b32">;
389defm DS_ADD_F32       : DS_1A1D_NORET_mc<"ds_add_f32">;
390defm DS_MIN_F32       : DS_1A1D_NORET_mc<"ds_min_f32">;
391defm DS_MAX_F32       : DS_1A1D_NORET_mc<"ds_max_f32">;
392
393let mayLoad = 0 in {
394defm DS_WRITE_B8      : DS_1A1D_NORET_mc<"ds_write_b8">;
395defm DS_WRITE_B16     : DS_1A1D_NORET_mc<"ds_write_b16">;
396defm DS_WRITE_B32     : DS_1A1D_NORET_mc<"ds_write_b32">;
397defm DS_WRITE2_B32    : DS_1A2D_Off8_NORET_mc<"ds_write2_b32">;
398defm DS_WRITE2ST64_B32: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b32">;
399
400
401let has_m0_read = 0 in {
402
403let SubtargetPredicate = HasD16LoadStore in {
404def DS_WRITE_B8_D16_HI  : DS_1A1D_NORET<"ds_write_b8_d16_hi">;
405def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">;
406}
407
408} // End has_m0_read = 0
409
410let SubtargetPredicate = HasDSAddTid in {
411def DS_WRITE_ADDTID_B32 : DS_0A1D_NORET<"ds_write_addtid_b32">;
412}
413
414} // End mayLoad = 0
415
416defm DS_MSKOR_B32     : DS_1A2D_NORET_mc<"ds_mskor_b32">;
417defm DS_CMPST_B32     : DS_1A2D_NORET_mc<"ds_cmpst_b32">;
418defm DS_CMPST_F32     : DS_1A2D_NORET_mc<"ds_cmpst_f32">;
419
420defm DS_ADD_U64       : DS_1A1D_NORET_mc<"ds_add_u64", VReg_64>;
421defm DS_SUB_U64       : DS_1A1D_NORET_mc<"ds_sub_u64", VReg_64>;
422defm DS_RSUB_U64      : DS_1A1D_NORET_mc<"ds_rsub_u64", VReg_64>;
423defm DS_INC_U64       : DS_1A1D_NORET_mc<"ds_inc_u64", VReg_64>;
424defm DS_DEC_U64       : DS_1A1D_NORET_mc<"ds_dec_u64", VReg_64>;
425defm DS_MIN_I64       : DS_1A1D_NORET_mc<"ds_min_i64", VReg_64>;
426defm DS_MAX_I64       : DS_1A1D_NORET_mc<"ds_max_i64", VReg_64>;
427defm DS_MIN_U64       : DS_1A1D_NORET_mc<"ds_min_u64", VReg_64>;
428defm DS_MAX_U64       : DS_1A1D_NORET_mc<"ds_max_u64", VReg_64>;
429defm DS_AND_B64       : DS_1A1D_NORET_mc<"ds_and_b64", VReg_64>;
430defm DS_OR_B64        : DS_1A1D_NORET_mc<"ds_or_b64", VReg_64>;
431defm DS_XOR_B64       : DS_1A1D_NORET_mc<"ds_xor_b64", VReg_64>;
432defm DS_MSKOR_B64     : DS_1A2D_NORET_mc<"ds_mskor_b64", VReg_64>;
433let mayLoad = 0 in {
434defm DS_WRITE_B64     : DS_1A1D_NORET_mc<"ds_write_b64", VReg_64>;
435defm DS_WRITE2_B64    : DS_1A2D_Off8_NORET_mc<"ds_write2_b64", VReg_64>;
436defm DS_WRITE2ST64_B64: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b64", VReg_64>;
437}
438defm DS_CMPST_B64     : DS_1A2D_NORET_mc<"ds_cmpst_b64", VReg_64>;
439defm DS_CMPST_F64     : DS_1A2D_NORET_mc<"ds_cmpst_f64", VReg_64>;
440defm DS_MIN_F64       : DS_1A1D_NORET_mc<"ds_min_f64", VReg_64>;
441defm DS_MAX_F64       : DS_1A1D_NORET_mc<"ds_max_f64", VReg_64>;
442
443defm DS_ADD_RTN_U32   : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
444defm DS_ADD_RTN_F32   : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32, "ds_add_f32">;
445defm DS_SUB_RTN_U32   : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
446defm DS_RSUB_RTN_U32  : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
447defm DS_INC_RTN_U32   : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
448defm DS_DEC_RTN_U32   : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
449defm DS_MIN_RTN_I32   : DS_1A1D_RET_mc<"ds_min_rtn_i32", VGPR_32, "ds_min_i32">;
450defm DS_MAX_RTN_I32   : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
451defm DS_MIN_RTN_U32   : DS_1A1D_RET_mc<"ds_min_rtn_u32", VGPR_32, "ds_min_u32">;
452defm DS_MAX_RTN_U32   : DS_1A1D_RET_mc<"ds_max_rtn_u32", VGPR_32, "ds_max_u32">;
453defm DS_AND_RTN_B32   : DS_1A1D_RET_mc<"ds_and_rtn_b32", VGPR_32, "ds_and_b32">;
454defm DS_OR_RTN_B32    : DS_1A1D_RET_mc<"ds_or_rtn_b32", VGPR_32, "ds_or_b32">;
455defm DS_XOR_RTN_B32   : DS_1A1D_RET_mc<"ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">;
456defm DS_MSKOR_RTN_B32 : DS_1A2D_RET_mc<"ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">;
457defm DS_CMPST_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
458defm DS_CMPST_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
459defm DS_MIN_RTN_F32   : DS_1A1D_RET_mc<"ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
460defm DS_MAX_RTN_F32   : DS_1A1D_RET_mc<"ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
461
462defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b32">;
463defm DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>;
464defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>;
465
466defm DS_ADD_RTN_U64  : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64, "ds_add_u64">;
467defm DS_SUB_RTN_U64  : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
468defm DS_RSUB_RTN_U64  : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
469defm DS_INC_RTN_U64   : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
470defm DS_DEC_RTN_U64   : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
471defm DS_MIN_RTN_I64    : DS_1A1D_RET_mc<"ds_min_rtn_i64", VReg_64, "ds_min_i64">;
472defm DS_MAX_RTN_I64    : DS_1A1D_RET_mc<"ds_max_rtn_i64", VReg_64, "ds_max_i64">;
473defm DS_MIN_RTN_U64   : DS_1A1D_RET_mc<"ds_min_rtn_u64", VReg_64, "ds_min_u64">;
474defm DS_MAX_RTN_U64   : DS_1A1D_RET_mc<"ds_max_rtn_u64", VReg_64, "ds_max_u64">;
475defm DS_AND_RTN_B64    : DS_1A1D_RET_mc<"ds_and_rtn_b64", VReg_64, "ds_and_b64">;
476defm DS_OR_RTN_B64     : DS_1A1D_RET_mc<"ds_or_rtn_b64", VReg_64, "ds_or_b64">;
477defm DS_XOR_RTN_B64    : DS_1A1D_RET_mc<"ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
478defm DS_MSKOR_RTN_B64  : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
479defm DS_CMPST_RTN_B64  : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
480defm DS_CMPST_RTN_F64  : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
481defm DS_MIN_RTN_F64    : DS_1A1D_RET_mc<"ds_min_rtn_f64", VReg_64, "ds_min_f64">;
482defm DS_MAX_RTN_F64    : DS_1A1D_RET_mc<"ds_max_rtn_f64", VReg_64, "ds_max_f64">;
483
484defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", VReg_64>;
485defm DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>;
486defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>;
487
488let isConvergent = 1, usesCustomInserter = 1 in {
489def DS_GWS_INIT       : DS_GWS_1D<"ds_gws_init"> {
490  let mayLoad = 0;
491}
492def DS_GWS_SEMA_V     : DS_GWS_0D<"ds_gws_sema_v">;
493def DS_GWS_SEMA_BR    : DS_GWS_1D<"ds_gws_sema_br">;
494def DS_GWS_SEMA_P     : DS_GWS_0D<"ds_gws_sema_p">;
495def DS_GWS_BARRIER    : DS_GWS_1D<"ds_gws_barrier">;
496}
497
498def DS_ADD_SRC2_U32   : DS_1A<"ds_add_src2_u32">;
499def DS_SUB_SRC2_U32   : DS_1A<"ds_sub_src2_u32">;
500def DS_RSUB_SRC2_U32  : DS_1A<"ds_rsub_src2_u32">;
501def DS_INC_SRC2_U32   : DS_1A<"ds_inc_src2_u32">;
502def DS_DEC_SRC2_U32   : DS_1A<"ds_dec_src2_u32">;
503def DS_MIN_SRC2_I32   : DS_1A<"ds_min_src2_i32">;
504def DS_MAX_SRC2_I32   : DS_1A<"ds_max_src2_i32">;
505def DS_MIN_SRC2_U32   : DS_1A<"ds_min_src2_u32">;
506def DS_MAX_SRC2_U32   : DS_1A<"ds_max_src2_u32">;
507def DS_AND_SRC2_B32   : DS_1A<"ds_and_src2_b32">;
508def DS_OR_SRC2_B32    : DS_1A<"ds_or_src2_b32">;
509def DS_XOR_SRC2_B32   : DS_1A<"ds_xor_src2_b32">;
510def DS_MIN_SRC2_F32   : DS_1A<"ds_min_src2_f32">;
511def DS_MAX_SRC2_F32   : DS_1A<"ds_max_src2_f32">;
512
513def DS_ADD_SRC2_U64   : DS_1A<"ds_add_src2_u64">;
514def DS_SUB_SRC2_U64   : DS_1A<"ds_sub_src2_u64">;
515def DS_RSUB_SRC2_U64  : DS_1A<"ds_rsub_src2_u64">;
516def DS_INC_SRC2_U64   : DS_1A<"ds_inc_src2_u64">;
517def DS_DEC_SRC2_U64   : DS_1A<"ds_dec_src2_u64">;
518def DS_MIN_SRC2_I64   : DS_1A<"ds_min_src2_i64">;
519def DS_MAX_SRC2_I64   : DS_1A<"ds_max_src2_i64">;
520def DS_MIN_SRC2_U64   : DS_1A<"ds_min_src2_u64">;
521def DS_MAX_SRC2_U64   : DS_1A<"ds_max_src2_u64">;
522def DS_AND_SRC2_B64   : DS_1A<"ds_and_src2_b64">;
523def DS_OR_SRC2_B64    : DS_1A<"ds_or_src2_b64">;
524def DS_XOR_SRC2_B64   : DS_1A<"ds_xor_src2_b64">;
525def DS_MIN_SRC2_F64   : DS_1A<"ds_min_src2_f64">;
526def DS_MAX_SRC2_F64   : DS_1A<"ds_max_src2_f64">;
527
528def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">;
529def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
530
531let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
532def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>;
533}
534
535let mayStore = 0 in {
536defm DS_READ_I8      : DS_1A_RET_mc<"ds_read_i8">;
537defm DS_READ_U8      : DS_1A_RET_mc<"ds_read_u8">;
538defm DS_READ_I16     : DS_1A_RET_mc<"ds_read_i16">;
539defm DS_READ_U16     : DS_1A_RET_mc<"ds_read_u16">;
540defm DS_READ_B32     : DS_1A_RET_mc<"ds_read_b32">;
541defm DS_READ_B64     : DS_1A_RET_mc<"ds_read_b64", VReg_64>;
542
543defm DS_READ2_B32    : DS_1A_Off8_RET_mc<"ds_read2_b32", VReg_64>;
544defm DS_READ2ST64_B32: DS_1A_Off8_RET_mc<"ds_read2st64_b32", VReg_64>;
545
546defm DS_READ2_B64    : DS_1A_Off8_RET_mc<"ds_read2_b64", VReg_128>;
547defm DS_READ2ST64_B64: DS_1A_Off8_RET_mc<"ds_read2st64_b64", VReg_128>;
548
549let has_m0_read = 0 in {
550let SubtargetPredicate = HasD16LoadStore in {
551def DS_READ_U8_D16     : DS_1A_RET_Tied<"ds_read_u8_d16">;
552def DS_READ_U8_D16_HI  : DS_1A_RET_Tied<"ds_read_u8_d16_hi">;
553def DS_READ_I8_D16     : DS_1A_RET_Tied<"ds_read_i8_d16">;
554def DS_READ_I8_D16_HI  : DS_1A_RET_Tied<"ds_read_i8_d16_hi">;
555def DS_READ_U16_D16    : DS_1A_RET_Tied<"ds_read_u16_d16">;
556def DS_READ_U16_D16_HI : DS_1A_RET_Tied<"ds_read_u16_d16_hi">;
557}
558} // End has_m0_read = 0
559
560let SubtargetPredicate = HasDSAddTid in {
561def DS_READ_ADDTID_B32 : DS_0A_RET<"ds_read_addtid_b32">;
562}
563
564} // End mayStore = 0
565
566def DS_CONSUME       : DS_0A_RET<"ds_consume">;
567def DS_APPEND        : DS_0A_RET<"ds_append">;
568def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
569
570//===----------------------------------------------------------------------===//
571// Instruction definitions for CI and newer.
572//===----------------------------------------------------------------------===//
573
574let SubtargetPredicate = isGFX7Plus in {
575
576defm DS_WRAP_RTN_B32 : DS_1A2D_RET_mc<"ds_wrap_rtn_b32", VGPR_32>;
577defm DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET_mc<"ds_condxchg32_rtn_b64", VReg_64>;
578
579let isConvergent = 1, usesCustomInserter = 1 in {
580def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
581}
582
583let mayStore = 0 in {
584defm DS_READ_B96 : DS_1A_RET_mc<"ds_read_b96", VReg_96>;
585defm DS_READ_B128: DS_1A_RET_mc<"ds_read_b128", VReg_128>;
586} // End mayStore = 0
587
588let mayLoad = 0 in {
589defm DS_WRITE_B96 : DS_1A1D_NORET_mc<"ds_write_b96", VReg_96>;
590defm DS_WRITE_B128 : DS_1A1D_NORET_mc<"ds_write_b128", VReg_128>;
591} // End mayLoad = 0
592
593def DS_NOP : DS_VOID<"ds_nop">;
594
595} // let SubtargetPredicate = isGFX7Plus
596
597//===----------------------------------------------------------------------===//
598// Instruction definitions for VI and newer.
599//===----------------------------------------------------------------------===//
600
601let SubtargetPredicate = isGFX8Plus in {
602
603let Uses = [EXEC] in {
604def DS_PERMUTE_B32  : DS_1A1D_PERMUTE <"ds_permute_b32",
605                                       int_amdgcn_ds_permute>;
606def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
607                                       int_amdgcn_ds_bpermute>;
608}
609
610def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
611
612} // let SubtargetPredicate = isGFX8Plus
613
614//===----------------------------------------------------------------------===//
615// DS Patterns
616//===----------------------------------------------------------------------===//
617
618def : GCNPat <
619  (int_amdgcn_ds_swizzle i32:$src, timm:$offset16),
620  (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
621>;
622
623class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
624  (vt (frag (DS1Addr1Offset i32:$ptr, i16:$offset))),
625  (inst $ptr, offset:$offset, (i1 gds))
626>;
627
628multiclass DSReadPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
629
630  let OtherPredicates = [LDSRequiresM0Init] in {
631    def : DSReadPat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
632  }
633
634  let OtherPredicates = [NotLDSRequiresM0Init] in {
635    def : DSReadPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
636  }
637}
638
639class DSReadPat_D16 <DS_Pseudo inst, PatFrag frag, ValueType vt> : GCNPat <
640  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$in),
641  (inst $ptr, offset:$offset, (i1 0), $in)
642>;
643
644defm : DSReadPat_mc <DS_READ_I8, i32, "sextloadi8_local">;
645defm : DSReadPat_mc <DS_READ_I8,  i16, "sextloadi8_local">;
646defm : DSReadPat_mc <DS_READ_U8,  i32, "extloadi8_local">;
647defm : DSReadPat_mc <DS_READ_U8,  i32, "zextloadi8_local">;
648defm : DSReadPat_mc <DS_READ_U8,  i16, "extloadi8_local">;
649defm : DSReadPat_mc <DS_READ_U8,  i16, "zextloadi8_local">;
650defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
651defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
652defm : DSReadPat_mc <DS_READ_U16, i32, "extloadi16_local">;
653defm : DSReadPat_mc <DS_READ_U16, i32, "zextloadi16_local">;
654defm : DSReadPat_mc <DS_READ_U16, i16, "load_local">;
655
656foreach vt = Reg32Types.types in {
657defm : DSReadPat_mc <DS_READ_B32, vt, "load_local">;
658}
659
660defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_32_local">;
661defm : DSReadPat_mc <DS_READ_B64, i64, "atomic_load_64_local">;
662
663let AddedComplexity = 100 in {
664
665foreach vt = VReg_64.RegTypes in {
666defm : DSReadPat_mc <DS_READ_B64, vt, "load_align8_local">;
667}
668
669defm : DSReadPat_mc <DS_READ_B128, v4i32, "load_align16_local">;
670
671} // End AddedComplexity = 100
672
673let OtherPredicates = [D16PreservesUnusedBits] in {
674def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2i16>;
675def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2f16>;
676def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2i16>;
677def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2f16>;
678def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2i16>;
679def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2f16>;
680
681def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2i16>;
682def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2f16>;
683def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2i16>;
684def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2f16>;
685def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2i16>;
686def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2f16>;
687}
688
689class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
690  (frag vt:$value, (DS1Addr1Offset i32:$ptr, i16:$offset)),
691  (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))
692>;
693
694multiclass DSWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
695  let OtherPredicates = [LDSRequiresM0Init] in {
696    def : DSWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
697  }
698
699  let OtherPredicates = [NotLDSRequiresM0Init] in {
700    def : DSWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
701  }
702}
703
704// Irritatingly, atomic_store reverses the order of operands from a
705// normal store.
706class DSAtomicWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
707  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$value),
708  (inst $ptr, $value, offset:$offset, (i1 0))
709>;
710
711multiclass DSAtomicWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
712  let OtherPredicates = [LDSRequiresM0Init] in {
713    def : DSAtomicWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
714  }
715
716  let OtherPredicates = [NotLDSRequiresM0Init] in {
717    def : DSAtomicWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
718  }
719}
720
721defm : DSWritePat_mc <DS_WRITE_B8, i32, "truncstorei8_local">;
722defm : DSWritePat_mc <DS_WRITE_B16, i32, "truncstorei16_local">;
723defm : DSWritePat_mc <DS_WRITE_B8, i16, "truncstorei8_local">;
724defm : DSWritePat_mc <DS_WRITE_B16, i16, "store_local">;
725
726foreach vt = VGPR_32.RegTypes in {
727defm : DSWritePat_mc <DS_WRITE_B32, vt, "store_local">;
728}
729
730defm : DSAtomicWritePat_mc <DS_WRITE_B32, i32, "atomic_store_local_32">;
731defm : DSAtomicWritePat_mc <DS_WRITE_B64, i64, "atomic_store_local_64">;
732
733let OtherPredicates = [D16PreservesUnusedBits] in {
734def : DSWritePat <DS_WRITE_B16_D16_HI, i32, store_local_hi16>;
735def : DSWritePat <DS_WRITE_B8_D16_HI, i32, truncstorei8_local_hi16>;
736}
737
738
739class DS64Bit4ByteAlignedReadPat<DS_Pseudo inst, PatFrag frag> : GCNPat <
740  (v2i32 (frag (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))),
741  (inst $ptr, $offset0, $offset1, (i1 0))
742>;
743
744class DS64Bit4ByteAlignedWritePat<DS_Pseudo inst, PatFrag frag> : GCNPat<
745  (frag v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1)),
746  (inst $ptr, (i32 (EXTRACT_SUBREG $value, sub0)),
747              (i32 (EXTRACT_SUBREG $value, sub1)), $offset0, $offset1,
748              (i1 0))
749>;
750
751// v2i32 loads are split into i32 loads on SI during lowering, due to a bug
752// related to bounds checking.
753let OtherPredicates = [LDSRequiresM0Init, isGFX7Plus] in {
754def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32, load_local_m0>;
755def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32, store_local_m0>;
756}
757
758let OtherPredicates = [NotLDSRequiresM0Init] in {
759def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32_gfx9, load_local>;
760def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32_gfx9, store_local>;
761}
762
763
764let AddedComplexity = 100 in {
765
766foreach vt = VReg_64.RegTypes in {
767defm : DSWritePat_mc <DS_WRITE_B64, vt, "store_align8_local">;
768}
769
770defm : DSWritePat_mc <DS_WRITE_B128, v4i32, "store_align16_local">;
771
772} // End AddedComplexity = 100
773class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
774  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$value),
775  (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))
776>;
777
778multiclass DSAtomicRetPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
779  let OtherPredicates = [LDSRequiresM0Init] in {
780    def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_local_m0_"#vt.Size)>;
781  }
782
783  let OtherPredicates = [NotLDSRequiresM0Init] in {
784    def : DSAtomicRetPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
785                         !cast<PatFrag>(frag#"_local_"#vt.Size)>;
786  }
787
788  def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_region_m0_"#vt.Size), 1>;
789}
790
791
792
793class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
794  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$cmp, vt:$swap),
795  (inst $ptr, getVregSrcForVT<vt>.ret:$cmp, getVregSrcForVT<vt>.ret:$swap, offset:$offset, (i1 gds))
796>;
797
798multiclass DSAtomicCmpXChg_mc<DS_Pseudo inst, ValueType vt, string frag> {
799  let OtherPredicates = [LDSRequiresM0Init] in {
800    def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_local_m0_"#vt.Size)>;
801  }
802
803  let OtherPredicates = [NotLDSRequiresM0Init] in {
804    def : DSAtomicCmpXChg<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
805                          !cast<PatFrag>(frag#"_local_"#vt.Size)>;
806  }
807
808  def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_region_m0_"#vt.Size), 1>;
809}
810
811
812
813// 32-bit atomics.
814defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B32, i32, "atomic_swap">;
815defm : DSAtomicRetPat_mc<DS_ADD_RTN_U32, i32, "atomic_load_add">;
816defm : DSAtomicRetPat_mc<DS_SUB_RTN_U32, i32, "atomic_load_sub">;
817defm : DSAtomicRetPat_mc<DS_INC_RTN_U32, i32, "atomic_inc">;
818defm : DSAtomicRetPat_mc<DS_DEC_RTN_U32, i32, "atomic_dec">;
819defm : DSAtomicRetPat_mc<DS_AND_RTN_B32, i32, "atomic_load_and">;
820defm : DSAtomicRetPat_mc<DS_OR_RTN_B32, i32, "atomic_load_or">;
821defm : DSAtomicRetPat_mc<DS_XOR_RTN_B32, i32, "atomic_load_xor">;
822defm : DSAtomicRetPat_mc<DS_MIN_RTN_I32, i32, "atomic_load_min">;
823defm : DSAtomicRetPat_mc<DS_MAX_RTN_I32, i32, "atomic_load_max">;
824defm : DSAtomicRetPat_mc<DS_MIN_RTN_U32, i32, "atomic_load_umin">;
825defm : DSAtomicRetPat_mc<DS_MAX_RTN_U32, i32, "atomic_load_umax">;
826defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B32, i32, "atomic_cmp_swap">;
827defm : DSAtomicRetPat_mc<DS_MIN_RTN_F32, f32, "atomic_load_fmin">;
828defm : DSAtomicRetPat_mc<DS_MAX_RTN_F32, f32, "atomic_load_fmax">;
829defm : DSAtomicRetPat_mc<DS_ADD_RTN_F32, f32, "atomic_load_fadd">;
830
831// 64-bit atomics.
832defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B64, i64, "atomic_swap">;
833defm : DSAtomicRetPat_mc<DS_ADD_RTN_U64, i64, "atomic_load_add">;
834defm : DSAtomicRetPat_mc<DS_SUB_RTN_U64, i64, "atomic_load_sub">;
835defm : DSAtomicRetPat_mc<DS_INC_RTN_U64, i64, "atomic_inc">;
836defm : DSAtomicRetPat_mc<DS_DEC_RTN_U64, i64, "atomic_dec">;
837defm : DSAtomicRetPat_mc<DS_AND_RTN_B64, i64, "atomic_load_and">;
838defm : DSAtomicRetPat_mc<DS_OR_RTN_B64, i64, "atomic_load_or">;
839defm : DSAtomicRetPat_mc<DS_XOR_RTN_B64, i64, "atomic_load_xor">;
840defm : DSAtomicRetPat_mc<DS_MIN_RTN_I64, i64, "atomic_load_min">;
841defm : DSAtomicRetPat_mc<DS_MAX_RTN_I64, i64, "atomic_load_max">;
842defm : DSAtomicRetPat_mc<DS_MIN_RTN_U64, i64, "atomic_load_umin">;
843defm : DSAtomicRetPat_mc<DS_MAX_RTN_U64, i64, "atomic_load_umax">;
844
845defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B64, i64, "atomic_cmp_swap">;
846
847def : Pat <
848  (SIds_ordered_count i32:$value, i16:$offset),
849  (DS_ORDERED_COUNT $value, (as_i16imm $offset))
850>;
851
852//===----------------------------------------------------------------------===//
853// Target-specific instruction encodings.
854//===----------------------------------------------------------------------===//
855
856//===----------------------------------------------------------------------===//
857// Base ENC_DS for GFX6, GFX7, GFX10.
858//===----------------------------------------------------------------------===//
859
860class Base_DS_Real_gfx6_gfx7_gfx10<bits<8> op, DS_Pseudo ps, int ef> :
861    DS_Real<ps>, SIMCInstr <ps.Mnemonic, ef> {
862
863  let Inst{7-0}   = !if(ps.has_offset0, offset0, 0);
864  let Inst{15-8}  = !if(ps.has_offset1, offset1, 0);
865  let Inst{17}    = !if(ps.has_gds, gds, ps.gdsValue);
866  let Inst{25-18} = op;
867  let Inst{31-26} = 0x36;
868  let Inst{39-32} = !if(ps.has_addr, addr, !if(ps.has_gws_data0, data0, 0));
869  let Inst{47-40} = !if(ps.has_data0, data0, 0);
870  let Inst{55-48} = !if(ps.has_data1, data1, 0);
871  let Inst{63-56} = !if(ps.has_vdst, vdst, 0);
872}
873
874//===----------------------------------------------------------------------===//
875// GFX10.
876//===----------------------------------------------------------------------===//
877
878let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
879  multiclass DS_Real_gfx10<bits<8> op>  {
880    def _gfx10 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
881                                              SIEncodingFamily.GFX10>;
882  }
883} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
884
885defm DS_ADD_F32          : DS_Real_gfx10<0x015>;
886defm DS_ADD_RTN_F32      : DS_Real_gfx10<0x055>;
887defm DS_ADD_SRC2_F32     : DS_Real_gfx10<0x095>;
888defm DS_WRITE_B8_D16_HI  : DS_Real_gfx10<0x0a0>;
889defm DS_WRITE_B16_D16_HI : DS_Real_gfx10<0x0a1>;
890defm DS_READ_U8_D16      : DS_Real_gfx10<0x0a2>;
891defm DS_READ_U8_D16_HI   : DS_Real_gfx10<0x0a3>;
892defm DS_READ_I8_D16      : DS_Real_gfx10<0x0a4>;
893defm DS_READ_I8_D16_HI   : DS_Real_gfx10<0x0a5>;
894defm DS_READ_U16_D16     : DS_Real_gfx10<0x0a6>;
895defm DS_READ_U16_D16_HI  : DS_Real_gfx10<0x0a7>;
896defm DS_WRITE_ADDTID_B32 : DS_Real_gfx10<0x0b0>;
897defm DS_READ_ADDTID_B32  : DS_Real_gfx10<0x0b1>;
898defm DS_PERMUTE_B32      : DS_Real_gfx10<0x0b2>;
899defm DS_BPERMUTE_B32     : DS_Real_gfx10<0x0b3>;
900
901//===----------------------------------------------------------------------===//
902// GFX7, GFX10.
903//===----------------------------------------------------------------------===//
904
905let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {
906  multiclass DS_Real_gfx7<bits<8> op> {
907    def _gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
908                                             SIEncodingFamily.SI>;
909  }
910} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7"
911
912multiclass DS_Real_gfx7_gfx10<bits<8> op> :
913  DS_Real_gfx7<op>, DS_Real_gfx10<op>;
914
915// FIXME-GFX7: Add tests when upstreaming this part.
916defm DS_GWS_SEMA_RELEASE_ALL : DS_Real_gfx7_gfx10<0x018>;
917defm DS_WRAP_RTN_B32         : DS_Real_gfx7_gfx10<0x034>;
918defm DS_CONDXCHG32_RTN_B64   : DS_Real_gfx7_gfx10<0x07e>;
919defm DS_WRITE_B96            : DS_Real_gfx7_gfx10<0x0de>;
920defm DS_WRITE_B128           : DS_Real_gfx7_gfx10<0x0df>;
921defm DS_READ_B96             : DS_Real_gfx7_gfx10<0x0fe>;
922defm DS_READ_B128            : DS_Real_gfx7_gfx10<0x0ff>;
923
924//===----------------------------------------------------------------------===//
925// GFX6, GFX7, GFX10.
926//===----------------------------------------------------------------------===//
927
928let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
929  multiclass DS_Real_gfx6_gfx7<bits<8> op> {
930    def _gfx6_gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
931                                                  SIEncodingFamily.SI>;
932  }
933} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
934
935multiclass DS_Real_gfx6_gfx7_gfx10<bits<8> op> :
936  DS_Real_gfx6_gfx7<op>, DS_Real_gfx10<op>;
937
938defm DS_ADD_U32             : DS_Real_gfx6_gfx7_gfx10<0x000>;
939defm DS_SUB_U32             : DS_Real_gfx6_gfx7_gfx10<0x001>;
940defm DS_RSUB_U32            : DS_Real_gfx6_gfx7_gfx10<0x002>;
941defm DS_INC_U32             : DS_Real_gfx6_gfx7_gfx10<0x003>;
942defm DS_DEC_U32             : DS_Real_gfx6_gfx7_gfx10<0x004>;
943defm DS_MIN_I32             : DS_Real_gfx6_gfx7_gfx10<0x005>;
944defm DS_MAX_I32             : DS_Real_gfx6_gfx7_gfx10<0x006>;
945defm DS_MIN_U32             : DS_Real_gfx6_gfx7_gfx10<0x007>;
946defm DS_MAX_U32             : DS_Real_gfx6_gfx7_gfx10<0x008>;
947defm DS_AND_B32             : DS_Real_gfx6_gfx7_gfx10<0x009>;
948defm DS_OR_B32              : DS_Real_gfx6_gfx7_gfx10<0x00a>;
949defm DS_XOR_B32             : DS_Real_gfx6_gfx7_gfx10<0x00b>;
950defm DS_MSKOR_B32           : DS_Real_gfx6_gfx7_gfx10<0x00c>;
951defm DS_WRITE_B32           : DS_Real_gfx6_gfx7_gfx10<0x00d>;
952defm DS_WRITE2_B32          : DS_Real_gfx6_gfx7_gfx10<0x00e>;
953defm DS_WRITE2ST64_B32      : DS_Real_gfx6_gfx7_gfx10<0x00f>;
954defm DS_CMPST_B32           : DS_Real_gfx6_gfx7_gfx10<0x010>;
955defm DS_CMPST_F32           : DS_Real_gfx6_gfx7_gfx10<0x011>;
956defm DS_MIN_F32             : DS_Real_gfx6_gfx7_gfx10<0x012>;
957defm DS_MAX_F32             : DS_Real_gfx6_gfx7_gfx10<0x013>;
958defm DS_NOP                 : DS_Real_gfx6_gfx7_gfx10<0x014>;
959defm DS_GWS_INIT            : DS_Real_gfx6_gfx7_gfx10<0x019>;
960defm DS_GWS_SEMA_V          : DS_Real_gfx6_gfx7_gfx10<0x01a>;
961defm DS_GWS_SEMA_BR         : DS_Real_gfx6_gfx7_gfx10<0x01b>;
962defm DS_GWS_SEMA_P          : DS_Real_gfx6_gfx7_gfx10<0x01c>;
963defm DS_GWS_BARRIER         : DS_Real_gfx6_gfx7_gfx10<0x01d>;
964defm DS_WRITE_B8            : DS_Real_gfx6_gfx7_gfx10<0x01e>;
965defm DS_WRITE_B16           : DS_Real_gfx6_gfx7_gfx10<0x01f>;
966defm DS_ADD_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x020>;
967defm DS_SUB_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x021>;
968defm DS_RSUB_RTN_U32        : DS_Real_gfx6_gfx7_gfx10<0x022>;
969defm DS_INC_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x023>;
970defm DS_DEC_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x024>;
971defm DS_MIN_RTN_I32         : DS_Real_gfx6_gfx7_gfx10<0x025>;
972defm DS_MAX_RTN_I32         : DS_Real_gfx6_gfx7_gfx10<0x026>;
973defm DS_MIN_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x027>;
974defm DS_MAX_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x028>;
975defm DS_AND_RTN_B32         : DS_Real_gfx6_gfx7_gfx10<0x029>;
976defm DS_OR_RTN_B32          : DS_Real_gfx6_gfx7_gfx10<0x02a>;
977defm DS_XOR_RTN_B32         : DS_Real_gfx6_gfx7_gfx10<0x02b>;
978defm DS_MSKOR_RTN_B32       : DS_Real_gfx6_gfx7_gfx10<0x02c>;
979defm DS_WRXCHG_RTN_B32      : DS_Real_gfx6_gfx7_gfx10<0x02d>;
980defm DS_WRXCHG2_RTN_B32     : DS_Real_gfx6_gfx7_gfx10<0x02e>;
981defm DS_WRXCHG2ST64_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02f>;
982defm DS_CMPST_RTN_B32       : DS_Real_gfx6_gfx7_gfx10<0x030>;
983defm DS_CMPST_RTN_F32       : DS_Real_gfx6_gfx7_gfx10<0x031>;
984defm DS_MIN_RTN_F32         : DS_Real_gfx6_gfx7_gfx10<0x032>;
985defm DS_MAX_RTN_F32         : DS_Real_gfx6_gfx7_gfx10<0x033>;
986defm DS_SWIZZLE_B32         : DS_Real_gfx6_gfx7_gfx10<0x035>;
987defm DS_READ_B32            : DS_Real_gfx6_gfx7_gfx10<0x036>;
988defm DS_READ2_B32           : DS_Real_gfx6_gfx7_gfx10<0x037>;
989defm DS_READ2ST64_B32       : DS_Real_gfx6_gfx7_gfx10<0x038>;
990defm DS_READ_I8             : DS_Real_gfx6_gfx7_gfx10<0x039>;
991defm DS_READ_U8             : DS_Real_gfx6_gfx7_gfx10<0x03a>;
992defm DS_READ_I16            : DS_Real_gfx6_gfx7_gfx10<0x03b>;
993defm DS_READ_U16            : DS_Real_gfx6_gfx7_gfx10<0x03c>;
994defm DS_CONSUME             : DS_Real_gfx6_gfx7_gfx10<0x03d>;
995defm DS_APPEND              : DS_Real_gfx6_gfx7_gfx10<0x03e>;
996defm DS_ORDERED_COUNT       : DS_Real_gfx6_gfx7_gfx10<0x03f>;
997defm DS_ADD_U64             : DS_Real_gfx6_gfx7_gfx10<0x040>;
998defm DS_SUB_U64             : DS_Real_gfx6_gfx7_gfx10<0x041>;
999defm DS_RSUB_U64            : DS_Real_gfx6_gfx7_gfx10<0x042>;
1000defm DS_INC_U64             : DS_Real_gfx6_gfx7_gfx10<0x043>;
1001defm DS_DEC_U64             : DS_Real_gfx6_gfx7_gfx10<0x044>;
1002defm DS_MIN_I64             : DS_Real_gfx6_gfx7_gfx10<0x045>;
1003defm DS_MAX_I64             : DS_Real_gfx6_gfx7_gfx10<0x046>;
1004defm DS_MIN_U64             : DS_Real_gfx6_gfx7_gfx10<0x047>;
1005defm DS_MAX_U64             : DS_Real_gfx6_gfx7_gfx10<0x048>;
1006defm DS_AND_B64             : DS_Real_gfx6_gfx7_gfx10<0x049>;
1007defm DS_OR_B64              : DS_Real_gfx6_gfx7_gfx10<0x04a>;
1008defm DS_XOR_B64             : DS_Real_gfx6_gfx7_gfx10<0x04b>;
1009defm DS_MSKOR_B64           : DS_Real_gfx6_gfx7_gfx10<0x04c>;
1010defm DS_WRITE_B64           : DS_Real_gfx6_gfx7_gfx10<0x04d>;
1011defm DS_WRITE2_B64          : DS_Real_gfx6_gfx7_gfx10<0x04e>;
1012defm DS_WRITE2ST64_B64      : DS_Real_gfx6_gfx7_gfx10<0x04f>;
1013defm DS_CMPST_B64           : DS_Real_gfx6_gfx7_gfx10<0x050>;
1014defm DS_CMPST_F64           : DS_Real_gfx6_gfx7_gfx10<0x051>;
1015defm DS_MIN_F64             : DS_Real_gfx6_gfx7_gfx10<0x052>;
1016defm DS_MAX_F64             : DS_Real_gfx6_gfx7_gfx10<0x053>;
1017defm DS_ADD_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x060>;
1018defm DS_SUB_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x061>;
1019defm DS_RSUB_RTN_U64        : DS_Real_gfx6_gfx7_gfx10<0x062>;
1020defm DS_INC_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x063>;
1021defm DS_DEC_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x064>;
1022defm DS_MIN_RTN_I64         : DS_Real_gfx6_gfx7_gfx10<0x065>;
1023defm DS_MAX_RTN_I64         : DS_Real_gfx6_gfx7_gfx10<0x066>;
1024defm DS_MIN_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x067>;
1025defm DS_MAX_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x068>;
1026defm DS_AND_RTN_B64         : DS_Real_gfx6_gfx7_gfx10<0x069>;
1027defm DS_OR_RTN_B64          : DS_Real_gfx6_gfx7_gfx10<0x06a>;
1028defm DS_XOR_RTN_B64         : DS_Real_gfx6_gfx7_gfx10<0x06b>;
1029defm DS_MSKOR_RTN_B64       : DS_Real_gfx6_gfx7_gfx10<0x06c>;
1030defm DS_WRXCHG_RTN_B64      : DS_Real_gfx6_gfx7_gfx10<0x06d>;
1031defm DS_WRXCHG2_RTN_B64     : DS_Real_gfx6_gfx7_gfx10<0x06e>;
1032defm DS_WRXCHG2ST64_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06f>;
1033defm DS_CMPST_RTN_B64       : DS_Real_gfx6_gfx7_gfx10<0x070>;
1034defm DS_CMPST_RTN_F64       : DS_Real_gfx6_gfx7_gfx10<0x071>;
1035defm DS_MIN_RTN_F64         : DS_Real_gfx6_gfx7_gfx10<0x072>;
1036defm DS_MAX_RTN_F64         : DS_Real_gfx6_gfx7_gfx10<0x073>;
1037defm DS_READ_B64            : DS_Real_gfx6_gfx7_gfx10<0x076>;
1038defm DS_READ2_B64           : DS_Real_gfx6_gfx7_gfx10<0x077>;
1039defm DS_READ2ST64_B64       : DS_Real_gfx6_gfx7_gfx10<0x078>;
1040defm DS_ADD_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x080>;
1041defm DS_SUB_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x081>;
1042defm DS_RSUB_SRC2_U32       : DS_Real_gfx6_gfx7_gfx10<0x082>;
1043defm DS_INC_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x083>;
1044defm DS_DEC_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x084>;
1045defm DS_MIN_SRC2_I32        : DS_Real_gfx6_gfx7_gfx10<0x085>;
1046defm DS_MAX_SRC2_I32        : DS_Real_gfx6_gfx7_gfx10<0x086>;
1047defm DS_MIN_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x087>;
1048defm DS_MAX_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x088>;
1049defm DS_AND_SRC2_B32        : DS_Real_gfx6_gfx7_gfx10<0x089>;
1050defm DS_OR_SRC2_B32         : DS_Real_gfx6_gfx7_gfx10<0x08a>;
1051defm DS_XOR_SRC2_B32        : DS_Real_gfx6_gfx7_gfx10<0x08b>;
1052defm DS_WRITE_SRC2_B32      : DS_Real_gfx6_gfx7_gfx10<0x08d>;
1053defm DS_MIN_SRC2_F32        : DS_Real_gfx6_gfx7_gfx10<0x092>;
1054defm DS_MAX_SRC2_F32        : DS_Real_gfx6_gfx7_gfx10<0x093>;
1055defm DS_ADD_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c0>;
1056defm DS_SUB_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c1>;
1057defm DS_RSUB_SRC2_U64       : DS_Real_gfx6_gfx7_gfx10<0x0c2>;
1058defm DS_INC_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c3>;
1059defm DS_DEC_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c4>;
1060defm DS_MIN_SRC2_I64        : DS_Real_gfx6_gfx7_gfx10<0x0c5>;
1061defm DS_MAX_SRC2_I64        : DS_Real_gfx6_gfx7_gfx10<0x0c6>;
1062defm DS_MIN_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c7>;
1063defm DS_MAX_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c8>;
1064defm DS_AND_SRC2_B64        : DS_Real_gfx6_gfx7_gfx10<0x0c9>;
1065defm DS_OR_SRC2_B64         : DS_Real_gfx6_gfx7_gfx10<0x0ca>;
1066defm DS_XOR_SRC2_B64        : DS_Real_gfx6_gfx7_gfx10<0x0cb>;
1067defm DS_WRITE_SRC2_B64      : DS_Real_gfx6_gfx7_gfx10<0x0cd>;
1068defm DS_MIN_SRC2_F64        : DS_Real_gfx6_gfx7_gfx10<0x0d2>;
1069defm DS_MAX_SRC2_F64        : DS_Real_gfx6_gfx7_gfx10<0x0d3>;
1070
1071//===----------------------------------------------------------------------===//
1072// GFX8, GFX9 (VI).
1073//===----------------------------------------------------------------------===//
1074
1075class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
1076  DS_Real <ds>,
1077  SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
1078  let AssemblerPredicates = [isGFX8GFX9];
1079  let DecoderNamespace = "GFX8";
1080
1081  // encoding
1082  let Inst{7-0}   = !if(ds.has_offset0, offset0, 0);
1083  let Inst{15-8}  = !if(ds.has_offset1, offset1, 0);
1084  let Inst{16}    = !if(ds.has_gds, gds, ds.gdsValue);
1085  let Inst{24-17} = op;
1086  let Inst{31-26} = 0x36; // ds prefix
1087  let Inst{39-32} = !if(ds.has_addr, addr, !if(ds.has_gws_data0, data0, 0));
1088  let Inst{47-40} = !if(ds.has_data0, data0, 0);
1089  let Inst{55-48} = !if(ds.has_data1, data1, 0);
1090  let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
1091}
1092
1093def DS_ADD_U32_vi         : DS_Real_vi<0x0,  DS_ADD_U32>;
1094def DS_SUB_U32_vi         : DS_Real_vi<0x1,  DS_SUB_U32>;
1095def DS_RSUB_U32_vi        : DS_Real_vi<0x2,  DS_RSUB_U32>;
1096def DS_INC_U32_vi         : DS_Real_vi<0x3,  DS_INC_U32>;
1097def DS_DEC_U32_vi         : DS_Real_vi<0x4,  DS_DEC_U32>;
1098def DS_MIN_I32_vi         : DS_Real_vi<0x5,  DS_MIN_I32>;
1099def DS_MAX_I32_vi         : DS_Real_vi<0x6,  DS_MAX_I32>;
1100def DS_MIN_U32_vi         : DS_Real_vi<0x7,  DS_MIN_U32>;
1101def DS_MAX_U32_vi         : DS_Real_vi<0x8,  DS_MAX_U32>;
1102def DS_AND_B32_vi         : DS_Real_vi<0x9,  DS_AND_B32>;
1103def DS_OR_B32_vi          : DS_Real_vi<0xa,  DS_OR_B32>;
1104def DS_XOR_B32_vi         : DS_Real_vi<0xb,  DS_XOR_B32>;
1105def DS_MSKOR_B32_vi       : DS_Real_vi<0xc,  DS_MSKOR_B32>;
1106def DS_WRITE_B32_vi       : DS_Real_vi<0xd,  DS_WRITE_B32>;
1107def DS_WRITE2_B32_vi      : DS_Real_vi<0xe,  DS_WRITE2_B32>;
1108def DS_WRITE2ST64_B32_vi  : DS_Real_vi<0xf,  DS_WRITE2ST64_B32>;
1109def DS_CMPST_B32_vi       : DS_Real_vi<0x10, DS_CMPST_B32>;
1110def DS_CMPST_F32_vi       : DS_Real_vi<0x11, DS_CMPST_F32>;
1111def DS_MIN_F32_vi         : DS_Real_vi<0x12, DS_MIN_F32>;
1112def DS_MAX_F32_vi         : DS_Real_vi<0x13, DS_MAX_F32>;
1113def DS_NOP_vi             : DS_Real_vi<0x14, DS_NOP>;
1114def DS_ADD_F32_vi         : DS_Real_vi<0x15, DS_ADD_F32>;
1115def DS_GWS_INIT_vi        : DS_Real_vi<0x99, DS_GWS_INIT>;
1116def DS_GWS_SEMA_V_vi      : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
1117def DS_GWS_SEMA_BR_vi     : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
1118def DS_GWS_SEMA_P_vi      : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
1119def DS_GWS_BARRIER_vi     : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
1120def DS_WRITE_ADDTID_B32_vi : DS_Real_vi<0x1d, DS_WRITE_ADDTID_B32>;
1121def DS_WRITE_B8_vi        : DS_Real_vi<0x1e, DS_WRITE_B8>;
1122def DS_WRITE_B16_vi       : DS_Real_vi<0x1f, DS_WRITE_B16>;
1123def DS_ADD_RTN_U32_vi     : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
1124def DS_SUB_RTN_U32_vi     : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
1125def DS_RSUB_RTN_U32_vi    : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
1126def DS_INC_RTN_U32_vi     : DS_Real_vi<0x23, DS_INC_RTN_U32>;
1127def DS_DEC_RTN_U32_vi     : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
1128def DS_MIN_RTN_I32_vi     : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
1129def DS_MAX_RTN_I32_vi     : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
1130def DS_MIN_RTN_U32_vi     : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
1131def DS_MAX_RTN_U32_vi     : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
1132def DS_AND_RTN_B32_vi     : DS_Real_vi<0x29, DS_AND_RTN_B32>;
1133def DS_OR_RTN_B32_vi      : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
1134def DS_XOR_RTN_B32_vi     : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
1135def DS_MSKOR_RTN_B32_vi   : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
1136def DS_WRXCHG_RTN_B32_vi  : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
1137def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
1138def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
1139def DS_CMPST_RTN_B32_vi   : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
1140def DS_CMPST_RTN_F32_vi   : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
1141def DS_MIN_RTN_F32_vi     : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
1142def DS_MAX_RTN_F32_vi     : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
1143def DS_WRAP_RTN_B32_vi    : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
1144def DS_ADD_RTN_F32_vi     : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
1145def DS_READ_B32_vi        : DS_Real_vi<0x36, DS_READ_B32>;
1146def DS_READ2_B32_vi       : DS_Real_vi<0x37, DS_READ2_B32>;
1147def DS_READ2ST64_B32_vi   : DS_Real_vi<0x38, DS_READ2ST64_B32>;
1148def DS_READ_I8_vi         : DS_Real_vi<0x39, DS_READ_I8>;
1149def DS_READ_U8_vi         : DS_Real_vi<0x3a, DS_READ_U8>;
1150def DS_READ_I16_vi        : DS_Real_vi<0x3b, DS_READ_I16>;
1151def DS_READ_U16_vi        : DS_Real_vi<0x3c, DS_READ_U16>;
1152def DS_READ_ADDTID_B32_vi : DS_Real_vi<0xb6, DS_READ_ADDTID_B32>;
1153def DS_CONSUME_vi         : DS_Real_vi<0xbd, DS_CONSUME>;
1154def DS_APPEND_vi          : DS_Real_vi<0xbe, DS_APPEND>;
1155def DS_ORDERED_COUNT_vi   : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
1156def DS_SWIZZLE_B32_vi     : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
1157def DS_PERMUTE_B32_vi     : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
1158def DS_BPERMUTE_B32_vi    : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
1159
1160def DS_ADD_U64_vi         : DS_Real_vi<0x40, DS_ADD_U64>;
1161def DS_SUB_U64_vi         : DS_Real_vi<0x41, DS_SUB_U64>;
1162def DS_RSUB_U64_vi        : DS_Real_vi<0x42, DS_RSUB_U64>;
1163def DS_INC_U64_vi         : DS_Real_vi<0x43, DS_INC_U64>;
1164def DS_DEC_U64_vi         : DS_Real_vi<0x44, DS_DEC_U64>;
1165def DS_MIN_I64_vi         : DS_Real_vi<0x45, DS_MIN_I64>;
1166def DS_MAX_I64_vi         : DS_Real_vi<0x46, DS_MAX_I64>;
1167def DS_MIN_U64_vi         : DS_Real_vi<0x47, DS_MIN_U64>;
1168def DS_MAX_U64_vi         : DS_Real_vi<0x48, DS_MAX_U64>;
1169def DS_AND_B64_vi         : DS_Real_vi<0x49, DS_AND_B64>;
1170def DS_OR_B64_vi          : DS_Real_vi<0x4a, DS_OR_B64>;
1171def DS_XOR_B64_vi         : DS_Real_vi<0x4b, DS_XOR_B64>;
1172def DS_MSKOR_B64_vi       : DS_Real_vi<0x4c, DS_MSKOR_B64>;
1173def DS_WRITE_B64_vi       : DS_Real_vi<0x4d, DS_WRITE_B64>;
1174def DS_WRITE2_B64_vi      : DS_Real_vi<0x4E, DS_WRITE2_B64>;
1175def DS_WRITE2ST64_B64_vi  : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
1176def DS_CMPST_B64_vi       : DS_Real_vi<0x50, DS_CMPST_B64>;
1177def DS_CMPST_F64_vi       : DS_Real_vi<0x51, DS_CMPST_F64>;
1178def DS_MIN_F64_vi         : DS_Real_vi<0x52, DS_MIN_F64>;
1179def DS_MAX_F64_vi         : DS_Real_vi<0x53, DS_MAX_F64>;
1180
1181def DS_WRITE_B8_D16_HI_vi  : DS_Real_vi<0x54, DS_WRITE_B8_D16_HI>;
1182def DS_WRITE_B16_D16_HI_vi : DS_Real_vi<0x55, DS_WRITE_B16_D16_HI>;
1183
1184def DS_READ_U8_D16_vi     : DS_Real_vi<0x56, DS_READ_U8_D16>;
1185def DS_READ_U8_D16_HI_vi  : DS_Real_vi<0x57, DS_READ_U8_D16_HI>;
1186def DS_READ_I8_D16_vi     : DS_Real_vi<0x58, DS_READ_I8_D16>;
1187def DS_READ_I8_D16_HI_vi  : DS_Real_vi<0x59, DS_READ_I8_D16_HI>;
1188def DS_READ_U16_D16_vi    : DS_Real_vi<0x5a, DS_READ_U16_D16>;
1189def DS_READ_U16_D16_HI_vi : DS_Real_vi<0x5b, DS_READ_U16_D16_HI>;
1190
1191def DS_ADD_RTN_U64_vi     : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
1192def DS_SUB_RTN_U64_vi     : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
1193def DS_RSUB_RTN_U64_vi    : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
1194def DS_INC_RTN_U64_vi     : DS_Real_vi<0x63, DS_INC_RTN_U64>;
1195def DS_DEC_RTN_U64_vi     : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
1196def DS_MIN_RTN_I64_vi     : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
1197def DS_MAX_RTN_I64_vi     : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
1198def DS_MIN_RTN_U64_vi     : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
1199def DS_MAX_RTN_U64_vi     : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
1200def DS_AND_RTN_B64_vi     : DS_Real_vi<0x69, DS_AND_RTN_B64>;
1201def DS_OR_RTN_B64_vi      : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
1202def DS_XOR_RTN_B64_vi     : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
1203def DS_MSKOR_RTN_B64_vi   : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
1204def DS_WRXCHG_RTN_B64_vi  : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
1205def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
1206def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
1207def DS_CONDXCHG32_RTN_B64_vi   : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
1208def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
1209def DS_CMPST_RTN_B64_vi   : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
1210def DS_CMPST_RTN_F64_vi   : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
1211def DS_MIN_RTN_F64_vi     : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
1212def DS_MAX_RTN_F64_vi     : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
1213
1214def DS_READ_B64_vi        : DS_Real_vi<0x76, DS_READ_B64>;
1215def DS_READ2_B64_vi       : DS_Real_vi<0x77, DS_READ2_B64>;
1216def DS_READ2ST64_B64_vi   : DS_Real_vi<0x78, DS_READ2ST64_B64>;
1217
1218def DS_ADD_SRC2_U32_vi    : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
1219def DS_SUB_SRC2_U32_vi    : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
1220def DS_RSUB_SRC2_U32_vi   : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
1221def DS_INC_SRC2_U32_vi    : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
1222def DS_DEC_SRC2_U32_vi    : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
1223def DS_MIN_SRC2_I32_vi    : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
1224def DS_MAX_SRC2_I32_vi    : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
1225def DS_MIN_SRC2_U32_vi    : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
1226def DS_MAX_SRC2_U32_vi    : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
1227def DS_AND_SRC2_B32_vi    : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
1228def DS_OR_SRC2_B32_vi     : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
1229def DS_XOR_SRC2_B32_vi    : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
1230def DS_WRITE_SRC2_B32_vi  : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
1231def DS_MIN_SRC2_F32_vi    : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
1232def DS_MAX_SRC2_F32_vi    : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
1233def DS_ADD_SRC2_F32_vi    : DS_Real_vi<0x95, DS_ADD_SRC2_F32>;
1234def DS_ADD_SRC2_U64_vi    : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
1235def DS_SUB_SRC2_U64_vi    : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
1236def DS_RSUB_SRC2_U64_vi   : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
1237def DS_INC_SRC2_U64_vi    : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
1238def DS_DEC_SRC2_U64_vi    : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
1239def DS_MIN_SRC2_I64_vi    : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
1240def DS_MAX_SRC2_I64_vi    : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
1241def DS_MIN_SRC2_U64_vi    : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
1242def DS_MAX_SRC2_U64_vi    : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
1243def DS_AND_SRC2_B64_vi    : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
1244def DS_OR_SRC2_B64_vi     : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
1245def DS_XOR_SRC2_B64_vi    : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
1246def DS_WRITE_SRC2_B64_vi  : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
1247def DS_MIN_SRC2_F64_vi    : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
1248def DS_MAX_SRC2_F64_vi    : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
1249def DS_WRITE_B96_vi       : DS_Real_vi<0xde, DS_WRITE_B96>;
1250def DS_WRITE_B128_vi      : DS_Real_vi<0xdf, DS_WRITE_B128>;
1251def DS_READ_B96_vi        : DS_Real_vi<0xfe, DS_READ_B96>;
1252def DS_READ_B128_vi       : DS_Real_vi<0xff, DS_READ_B128>;
1253