xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/DSInstructions.td (revision 2f513db72b034fd5ef7f080b11be5c711c15186a) 
1//===-- DSInstructions.td - DS Instruction Defintions ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
10  InstSI <outs, ins, "", pattern>,
11  SIMCInstr <opName, SIEncodingFamily.NONE> {
12
13  let LGKM_CNT = 1;
14  let DS = 1;
15  let Size = 8;
16  let UseNamedOperandTable = 1;
17
18  // Most instruction load and store data, so set this as the default.
19  let mayLoad = 1;
20  let mayStore = 1;
21  let maybeAtomic = 1;
22
23  let hasSideEffects = 0;
24  let SchedRW = [WriteLDS];
25
26  let isPseudo = 1;
27  let isCodeGenOnly = 1;
28
29  let AsmMatchConverter = "cvtDS";
30
31  string Mnemonic = opName;
32  string AsmOperands = asmOps;
33
34  // Well these bits a kind of hack because it would be more natural
35  // to test "outs" and "ins" dags for the presence of particular operands
36  bits<1> has_vdst = 1;
37  bits<1> has_addr = 1;
38  bits<1> has_data0 = 1;
39  bits<1> has_data1 = 1;
40
41  bits<1> has_gws_data0 = 0; // data0 is encoded as addr
42
43  bits<1> has_offset  = 1; // has "offset" that should be split to offset0,1
44  bits<1> has_offset0 = 1;
45  bits<1> has_offset1 = 1;
46
47  bits<1> has_gds = 1;
48  bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
49
50  bits<1> has_m0_read = 1;
51
52  let Uses = !if(has_m0_read, [M0, EXEC], [EXEC]);
53}
54
55class DS_Real <DS_Pseudo ds> :
56  InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
57  Enc64 {
58
59  let isPseudo = 0;
60  let isCodeGenOnly = 0;
61
62  // copy relevant pseudo op flags
63  let SubtargetPredicate = ds.SubtargetPredicate;
64  let OtherPredicates = ds.OtherPredicates;
65  let AsmMatchConverter  = ds.AsmMatchConverter;
66
67  // encoding fields
68  bits<8> vdst;
69  bits<1> gds;
70  bits<8> addr;
71  bits<8> data0;
72  bits<8> data1;
73  bits<8> offset0;
74  bits<8> offset1;
75
76  bits<16> offset;
77  let offset0 = !if(ds.has_offset, offset{7-0}, ?);
78  let offset1 = !if(ds.has_offset, offset{15-8}, ?);
79}
80
81
82// DS Pseudo instructions
83
84class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
85: DS_Pseudo<opName,
86  (outs),
87  (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
88  "$addr, $data0$offset$gds"> {
89
90  let has_data1 = 0;
91  let has_vdst = 0;
92}
93
94multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
95  def "" : DS_1A1D_NORET<opName, rc>,
96           AtomicNoRet<opName, 0>;
97
98  let has_m0_read = 0 in {
99    def _gfx9 : DS_1A1D_NORET<opName, rc>,
100                AtomicNoRet<opName#"_gfx9", 0>;
101  }
102}
103
104class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
105: DS_Pseudo<opName,
106  (outs),
107  (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
108  "$addr, $data0, $data1"#"$offset"#"$gds"> {
109
110  let has_vdst = 0;
111}
112
113multiclass DS_1A2D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
114  def "" : DS_1A2D_NORET<opName, rc>,
115           AtomicNoRet<opName, 0>;
116
117  let has_m0_read = 0 in {
118    def _gfx9 : DS_1A2D_NORET<opName, rc>,
119                AtomicNoRet<opName#"_gfx9", 0>;
120  }
121}
122
123class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
124: DS_Pseudo<opName,
125  (outs),
126  (ins VGPR_32:$addr, rc:$data0, rc:$data1,
127       offset0:$offset0, offset1:$offset1, gds:$gds),
128  "$addr, $data0, $data1$offset0$offset1$gds"> {
129
130  let has_vdst = 0;
131  let has_offset = 0;
132  let AsmMatchConverter = "cvtDSOffset01";
133}
134
135multiclass DS_1A2D_Off8_NORET_mc <string opName, RegisterClass rc = VGPR_32> {
136  def "" : DS_1A2D_Off8_NORET<opName, rc>;
137
138  let has_m0_read = 0 in {
139    def _gfx9 : DS_1A2D_Off8_NORET<opName, rc>;
140  }
141}
142
143class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
144: DS_Pseudo<opName,
145  (outs rc:$vdst),
146  (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
147  "$vdst, $addr, $data0$offset$gds"> {
148
149  let hasPostISelHook = 1;
150  let has_data1 = 0;
151}
152
153multiclass DS_1A1D_RET_mc <string opName, RegisterClass rc = VGPR_32,
154                           string NoRetOp = ""> {
155  def "" : DS_1A1D_RET<opName, rc>,
156    AtomicNoRet<NoRetOp, !if(!eq(NoRetOp, ""), 0, 1)>;
157
158  let has_m0_read = 0 in {
159    def _gfx9 : DS_1A1D_RET<opName, rc>,
160      AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp#"_gfx9"),
161                  !if(!eq(NoRetOp, ""), 0, 1)>;
162  }
163}
164
165class DS_1A2D_RET<string opName,
166                  RegisterClass rc = VGPR_32,
167                  RegisterClass src = rc>
168: DS_Pseudo<opName,
169  (outs rc:$vdst),
170  (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
171  "$vdst, $addr, $data0, $data1$offset$gds"> {
172
173  let hasPostISelHook = 1;
174}
175
176multiclass DS_1A2D_RET_mc<string opName,
177                          RegisterClass rc = VGPR_32,
178                          string NoRetOp = "",
179                          RegisterClass src = rc> {
180  def "" : DS_1A2D_RET<opName, rc, src>,
181    AtomicNoRet<NoRetOp, !if(!eq(NoRetOp, ""), 0, 1)>;
182
183  let has_m0_read = 0 in {
184    def _gfx9 : DS_1A2D_RET<opName, rc, src>,
185      AtomicNoRet<NoRetOp#"_gfx9", !if(!eq(NoRetOp, ""), 0, 1)>;
186  }
187}
188
189class DS_1A2D_Off8_RET<string opName,
190                       RegisterClass rc = VGPR_32,
191                       RegisterClass src = rc>
192: DS_Pseudo<opName,
193  (outs rc:$vdst),
194  (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
195  "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
196
197  let has_offset = 0;
198  let AsmMatchConverter = "cvtDSOffset01";
199
200  let hasPostISelHook = 1;
201}
202
203multiclass DS_1A2D_Off8_RET_mc<string opName,
204                               RegisterClass rc = VGPR_32,
205                               RegisterClass src = rc> {
206  def "" : DS_1A2D_Off8_RET<opName, rc, src>;
207
208  let has_m0_read = 0 in {
209    def _gfx9 : DS_1A2D_Off8_RET<opName, rc, src>;
210  }
211}
212
213
214class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset>
215: DS_Pseudo<opName,
216  (outs rc:$vdst),
217  !if(HasTiedOutput,
218    (ins VGPR_32:$addr, ofs:$offset, gds:$gds, rc:$vdst_in),
219    (ins VGPR_32:$addr, ofs:$offset, gds:$gds)),
220  "$vdst, $addr$offset$gds"> {
221  let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
222  let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
223  let has_data0 = 0;
224  let has_data1 = 0;
225}
226
227multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> {
228  def "" : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
229
230  let has_m0_read = 0 in {
231    def _gfx9 : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
232  }
233}
234
235class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> :
236  DS_1A_RET<opName, rc, 1>;
237
238class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
239: DS_Pseudo<opName,
240  (outs rc:$vdst),
241  (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
242  "$vdst, $addr$offset0$offset1$gds"> {
243
244  let has_offset = 0;
245  let has_data0 = 0;
246  let has_data1 = 0;
247  let AsmMatchConverter = "cvtDSOffset01";
248}
249
250multiclass DS_1A_Off8_RET_mc <string opName, RegisterClass rc = VGPR_32> {
251  def "" : DS_1A_Off8_RET<opName, rc>;
252
253  let has_m0_read = 0 in {
254    def _gfx9 : DS_1A_Off8_RET<opName, rc>;
255  }
256}
257
258class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
259  (outs VGPR_32:$vdst),
260  (ins VGPR_32:$addr, offset:$offset),
261  "$vdst, $addr$offset gds"> {
262
263  let has_data0 = 0;
264  let has_data1 = 0;
265  let has_gds = 0;
266  let gdsValue = 1;
267  let AsmMatchConverter = "cvtDSGds";
268}
269
270class DS_0A_RET <string opName> : DS_Pseudo<opName,
271  (outs VGPR_32:$vdst),
272  (ins offset:$offset, gds:$gds),
273  "$vdst$offset$gds"> {
274
275  let mayLoad = 1;
276  let mayStore = 1;
277
278  let has_addr = 0;
279  let has_data0 = 0;
280  let has_data1 = 0;
281}
282
283class DS_1A <string opName> : DS_Pseudo<opName,
284  (outs),
285  (ins VGPR_32:$addr, offset:$offset, gds:$gds),
286  "$addr$offset$gds"> {
287
288  let mayLoad = 1;
289  let mayStore = 1;
290
291  let has_vdst = 0;
292  let has_data0 = 0;
293  let has_data1 = 0;
294}
295
296multiclass DS_1A_mc <string opName> {
297  def "" : DS_1A<opName>;
298
299  let has_m0_read = 0 in {
300    def _gfx9 : DS_1A<opName>;
301  }
302}
303
304
305class DS_GWS <string opName, dag ins, string asmOps>
306: DS_Pseudo<opName, (outs), ins, asmOps> {
307
308  let has_vdst  = 0;
309  let has_addr  = 0;
310  let has_data0 = 0;
311  let has_data1 = 0;
312
313  let has_gds   = 0;
314  let gdsValue  = 1;
315  let AsmMatchConverter = "cvtDSGds";
316}
317
318class DS_GWS_0D <string opName>
319: DS_GWS<opName,
320  (ins offset:$offset, gds:$gds), "$offset gds">;
321
322class DS_GWS_1D <string opName>
323: DS_GWS<opName,
324  (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
325
326  let has_gws_data0 = 1;
327}
328
329class DS_VOID <string opName> : DS_Pseudo<opName,
330  (outs), (ins), ""> {
331  let mayLoad = 0;
332  let mayStore = 0;
333  let hasSideEffects = 1;
334  let UseNamedOperandTable = 0;
335  let AsmMatchConverter = "";
336
337  let has_vdst = 0;
338  let has_addr = 0;
339  let has_data0 = 0;
340  let has_data1 = 0;
341  let has_offset = 0;
342  let has_offset0 = 0;
343  let has_offset1 = 0;
344  let has_gds = 0;
345}
346
347class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
348: DS_Pseudo<opName,
349  (outs VGPR_32:$vdst),
350  (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
351  "$vdst, $addr, $data0$offset",
352  [(set i32:$vdst,
353   (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
354
355  let mayLoad = 0;
356  let mayStore = 0;
357  let isConvergent = 1;
358
359  let has_data1 = 0;
360  let has_gds = 0;
361}
362
363defm DS_ADD_U32       : DS_1A1D_NORET_mc<"ds_add_u32">;
364defm DS_SUB_U32       : DS_1A1D_NORET_mc<"ds_sub_u32">;
365defm DS_RSUB_U32      : DS_1A1D_NORET_mc<"ds_rsub_u32">;
366defm DS_INC_U32       : DS_1A1D_NORET_mc<"ds_inc_u32">;
367defm DS_DEC_U32       : DS_1A1D_NORET_mc<"ds_dec_u32">;
368defm DS_MIN_I32       : DS_1A1D_NORET_mc<"ds_min_i32">;
369defm DS_MAX_I32       : DS_1A1D_NORET_mc<"ds_max_i32">;
370defm DS_MIN_U32       : DS_1A1D_NORET_mc<"ds_min_u32">;
371defm DS_MAX_U32       : DS_1A1D_NORET_mc<"ds_max_u32">;
372defm DS_AND_B32       : DS_1A1D_NORET_mc<"ds_and_b32">;
373defm DS_OR_B32        : DS_1A1D_NORET_mc<"ds_or_b32">;
374defm DS_XOR_B32       : DS_1A1D_NORET_mc<"ds_xor_b32">;
375defm DS_ADD_F32       : DS_1A1D_NORET_mc<"ds_add_f32">;
376defm DS_MIN_F32       : DS_1A1D_NORET_mc<"ds_min_f32">;
377defm DS_MAX_F32       : DS_1A1D_NORET_mc<"ds_max_f32">;
378
379let mayLoad = 0 in {
380defm DS_WRITE_B8      : DS_1A1D_NORET_mc<"ds_write_b8">;
381defm DS_WRITE_B16     : DS_1A1D_NORET_mc<"ds_write_b16">;
382defm DS_WRITE_B32     : DS_1A1D_NORET_mc<"ds_write_b32">;
383defm DS_WRITE2_B32    : DS_1A2D_Off8_NORET_mc<"ds_write2_b32">;
384defm DS_WRITE2ST64_B32: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b32">;
385
386
387let has_m0_read = 0 in {
388
389let SubtargetPredicate = HasD16LoadStore in {
390def DS_WRITE_B8_D16_HI  : DS_1A1D_NORET<"ds_write_b8_d16_hi">;
391def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">;
392}
393
394let SubtargetPredicate = HasDSAddTid in {
395def DS_WRITE_ADDTID_B32 : DS_1A1D_NORET<"ds_write_addtid_b32">;
396}
397
398} // End has_m0_read = 0
399} // End mayLoad = 0
400
401defm DS_MSKOR_B32     : DS_1A2D_NORET_mc<"ds_mskor_b32">;
402defm DS_CMPST_B32     : DS_1A2D_NORET_mc<"ds_cmpst_b32">;
403defm DS_CMPST_F32     : DS_1A2D_NORET_mc<"ds_cmpst_f32">;
404
405defm DS_ADD_U64       : DS_1A1D_NORET_mc<"ds_add_u64", VReg_64>;
406defm DS_SUB_U64       : DS_1A1D_NORET_mc<"ds_sub_u64", VReg_64>;
407defm DS_RSUB_U64      : DS_1A1D_NORET_mc<"ds_rsub_u64", VReg_64>;
408defm DS_INC_U64       : DS_1A1D_NORET_mc<"ds_inc_u64", VReg_64>;
409defm DS_DEC_U64       : DS_1A1D_NORET_mc<"ds_dec_u64", VReg_64>;
410defm DS_MIN_I64       : DS_1A1D_NORET_mc<"ds_min_i64", VReg_64>;
411defm DS_MAX_I64       : DS_1A1D_NORET_mc<"ds_max_i64", VReg_64>;
412defm DS_MIN_U64       : DS_1A1D_NORET_mc<"ds_min_u64", VReg_64>;
413defm DS_MAX_U64       : DS_1A1D_NORET_mc<"ds_max_u64", VReg_64>;
414defm DS_AND_B64       : DS_1A1D_NORET_mc<"ds_and_b64", VReg_64>;
415defm DS_OR_B64        : DS_1A1D_NORET_mc<"ds_or_b64", VReg_64>;
416defm DS_XOR_B64       : DS_1A1D_NORET_mc<"ds_xor_b64", VReg_64>;
417defm DS_MSKOR_B64     : DS_1A2D_NORET_mc<"ds_mskor_b64", VReg_64>;
418let mayLoad = 0 in {
419defm DS_WRITE_B64     : DS_1A1D_NORET_mc<"ds_write_b64", VReg_64>;
420defm DS_WRITE2_B64    : DS_1A2D_Off8_NORET_mc<"ds_write2_b64", VReg_64>;
421defm DS_WRITE2ST64_B64: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b64", VReg_64>;
422}
423defm DS_CMPST_B64     : DS_1A2D_NORET_mc<"ds_cmpst_b64", VReg_64>;
424defm DS_CMPST_F64     : DS_1A2D_NORET_mc<"ds_cmpst_f64", VReg_64>;
425defm DS_MIN_F64       : DS_1A1D_NORET_mc<"ds_min_f64", VReg_64>;
426defm DS_MAX_F64       : DS_1A1D_NORET_mc<"ds_max_f64", VReg_64>;
427
428defm DS_ADD_RTN_U32   : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
429defm DS_ADD_RTN_F32   : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32, "ds_add_f32">;
430defm DS_SUB_RTN_U32   : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
431defm DS_RSUB_RTN_U32  : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
432defm DS_INC_RTN_U32   : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
433defm DS_DEC_RTN_U32   : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
434defm DS_MIN_RTN_I32   : DS_1A1D_RET_mc<"ds_min_rtn_i32", VGPR_32, "ds_min_i32">;
435defm DS_MAX_RTN_I32   : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
436defm DS_MIN_RTN_U32   : DS_1A1D_RET_mc<"ds_min_rtn_u32", VGPR_32, "ds_min_u32">;
437defm DS_MAX_RTN_U32   : DS_1A1D_RET_mc<"ds_max_rtn_u32", VGPR_32, "ds_max_u32">;
438defm DS_AND_RTN_B32   : DS_1A1D_RET_mc<"ds_and_rtn_b32", VGPR_32, "ds_and_b32">;
439defm DS_OR_RTN_B32    : DS_1A1D_RET_mc<"ds_or_rtn_b32", VGPR_32, "ds_or_b32">;
440defm DS_XOR_RTN_B32   : DS_1A1D_RET_mc<"ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">;
441defm DS_MSKOR_RTN_B32 : DS_1A2D_RET_mc<"ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">;
442defm DS_CMPST_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
443defm DS_CMPST_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
444defm DS_MIN_RTN_F32   : DS_1A1D_RET_mc<"ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
445defm DS_MAX_RTN_F32   : DS_1A1D_RET_mc<"ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
446
447defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b32">;
448defm DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>;
449defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>;
450
451defm DS_ADD_RTN_U64  : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64, "ds_add_u64">;
452defm DS_SUB_RTN_U64  : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
453defm DS_RSUB_RTN_U64  : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
454defm DS_INC_RTN_U64   : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
455defm DS_DEC_RTN_U64   : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
456defm DS_MIN_RTN_I64    : DS_1A1D_RET_mc<"ds_min_rtn_i64", VReg_64, "ds_min_i64">;
457defm DS_MAX_RTN_I64    : DS_1A1D_RET_mc<"ds_max_rtn_i64", VReg_64, "ds_max_i64">;
458defm DS_MIN_RTN_U64   : DS_1A1D_RET_mc<"ds_min_rtn_u64", VReg_64, "ds_min_u64">;
459defm DS_MAX_RTN_U64   : DS_1A1D_RET_mc<"ds_max_rtn_u64", VReg_64, "ds_max_u64">;
460defm DS_AND_RTN_B64    : DS_1A1D_RET_mc<"ds_and_rtn_b64", VReg_64, "ds_and_b64">;
461defm DS_OR_RTN_B64     : DS_1A1D_RET_mc<"ds_or_rtn_b64", VReg_64, "ds_or_b64">;
462defm DS_XOR_RTN_B64    : DS_1A1D_RET_mc<"ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
463defm DS_MSKOR_RTN_B64  : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
464defm DS_CMPST_RTN_B64  : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
465defm DS_CMPST_RTN_F64  : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
466defm DS_MIN_RTN_F64    : DS_1A1D_RET_mc<"ds_min_rtn_f64", VReg_64, "ds_min_f64">;
467defm DS_MAX_RTN_F64    : DS_1A1D_RET_mc<"ds_max_rtn_f64", VReg_64, "ds_max_f64">;
468
469defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", VReg_64>;
470defm DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>;
471defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>;
472
473let isConvergent = 1, usesCustomInserter = 1 in {
474def DS_GWS_INIT       : DS_GWS_1D<"ds_gws_init"> {
475  let mayLoad = 0;
476}
477def DS_GWS_SEMA_V     : DS_GWS_0D<"ds_gws_sema_v">;
478def DS_GWS_SEMA_BR    : DS_GWS_1D<"ds_gws_sema_br">;
479def DS_GWS_SEMA_P     : DS_GWS_0D<"ds_gws_sema_p">;
480def DS_GWS_BARRIER    : DS_GWS_1D<"ds_gws_barrier">;
481}
482
483def DS_ADD_SRC2_U32   : DS_1A<"ds_add_src2_u32">;
484def DS_SUB_SRC2_U32   : DS_1A<"ds_sub_src2_u32">;
485def DS_RSUB_SRC2_U32  : DS_1A<"ds_rsub_src2_u32">;
486def DS_INC_SRC2_U32   : DS_1A<"ds_inc_src2_u32">;
487def DS_DEC_SRC2_U32   : DS_1A<"ds_dec_src2_u32">;
488def DS_MIN_SRC2_I32   : DS_1A<"ds_min_src2_i32">;
489def DS_MAX_SRC2_I32   : DS_1A<"ds_max_src2_i32">;
490def DS_MIN_SRC2_U32   : DS_1A<"ds_min_src2_u32">;
491def DS_MAX_SRC2_U32   : DS_1A<"ds_max_src2_u32">;
492def DS_AND_SRC2_B32   : DS_1A<"ds_and_src2_b32">;
493def DS_OR_SRC2_B32    : DS_1A<"ds_or_src2_b32">;
494def DS_XOR_SRC2_B32   : DS_1A<"ds_xor_src2_b32">;
495def DS_MIN_SRC2_F32   : DS_1A<"ds_min_src2_f32">;
496def DS_MAX_SRC2_F32   : DS_1A<"ds_max_src2_f32">;
497
498def DS_ADD_SRC2_U64   : DS_1A<"ds_add_src2_u64">;
499def DS_SUB_SRC2_U64   : DS_1A<"ds_sub_src2_u64">;
500def DS_RSUB_SRC2_U64  : DS_1A<"ds_rsub_src2_u64">;
501def DS_INC_SRC2_U64   : DS_1A<"ds_inc_src2_u64">;
502def DS_DEC_SRC2_U64   : DS_1A<"ds_dec_src2_u64">;
503def DS_MIN_SRC2_I64   : DS_1A<"ds_min_src2_i64">;
504def DS_MAX_SRC2_I64   : DS_1A<"ds_max_src2_i64">;
505def DS_MIN_SRC2_U64   : DS_1A<"ds_min_src2_u64">;
506def DS_MAX_SRC2_U64   : DS_1A<"ds_max_src2_u64">;
507def DS_AND_SRC2_B64   : DS_1A<"ds_and_src2_b64">;
508def DS_OR_SRC2_B64    : DS_1A<"ds_or_src2_b64">;
509def DS_XOR_SRC2_B64   : DS_1A<"ds_xor_src2_b64">;
510def DS_MIN_SRC2_F64   : DS_1A<"ds_min_src2_f64">;
511def DS_MAX_SRC2_F64   : DS_1A<"ds_max_src2_f64">;
512
513def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">;
514def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
515
516let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
517def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>;
518}
519
520let mayStore = 0 in {
521defm DS_READ_I8      : DS_1A_RET_mc<"ds_read_i8">;
522defm DS_READ_U8      : DS_1A_RET_mc<"ds_read_u8">;
523defm DS_READ_I16     : DS_1A_RET_mc<"ds_read_i16">;
524defm DS_READ_U16     : DS_1A_RET_mc<"ds_read_u16">;
525defm DS_READ_B32     : DS_1A_RET_mc<"ds_read_b32">;
526defm DS_READ_B64     : DS_1A_RET_mc<"ds_read_b64", VReg_64>;
527
528defm DS_READ2_B32    : DS_1A_Off8_RET_mc<"ds_read2_b32", VReg_64>;
529defm DS_READ2ST64_B32: DS_1A_Off8_RET_mc<"ds_read2st64_b32", VReg_64>;
530
531defm DS_READ2_B64    : DS_1A_Off8_RET_mc<"ds_read2_b64", VReg_128>;
532defm DS_READ2ST64_B64: DS_1A_Off8_RET_mc<"ds_read2st64_b64", VReg_128>;
533
534let has_m0_read = 0 in {
535let SubtargetPredicate = HasD16LoadStore in {
536def DS_READ_U8_D16     : DS_1A_RET_Tied<"ds_read_u8_d16">;
537def DS_READ_U8_D16_HI  : DS_1A_RET_Tied<"ds_read_u8_d16_hi">;
538def DS_READ_I8_D16     : DS_1A_RET_Tied<"ds_read_i8_d16">;
539def DS_READ_I8_D16_HI  : DS_1A_RET_Tied<"ds_read_i8_d16_hi">;
540def DS_READ_U16_D16    : DS_1A_RET_Tied<"ds_read_u16_d16">;
541def DS_READ_U16_D16_HI : DS_1A_RET_Tied<"ds_read_u16_d16_hi">;
542}
543
544let SubtargetPredicate = HasDSAddTid in {
545def DS_READ_ADDTID_B32 : DS_1A_RET<"ds_read_addtid_b32">;
546}
547} // End has_m0_read = 0
548}
549
550def DS_CONSUME       : DS_0A_RET<"ds_consume">;
551def DS_APPEND        : DS_0A_RET<"ds_append">;
552def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
553
554//===----------------------------------------------------------------------===//
555// Instruction definitions for CI and newer.
556//===----------------------------------------------------------------------===//
557
558let SubtargetPredicate = isGFX7Plus in {
559
560defm DS_WRAP_RTN_B32 : DS_1A2D_RET_mc<"ds_wrap_rtn_b32", VGPR_32>;
561defm DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET_mc<"ds_condxchg32_rtn_b64", VReg_64>;
562
563let isConvergent = 1, usesCustomInserter = 1 in {
564def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
565}
566
567let mayStore = 0 in {
568defm DS_READ_B96 : DS_1A_RET_mc<"ds_read_b96", VReg_96>;
569defm DS_READ_B128: DS_1A_RET_mc<"ds_read_b128", VReg_128>;
570} // End mayStore = 0
571
572let mayLoad = 0 in {
573defm DS_WRITE_B96 : DS_1A1D_NORET_mc<"ds_write_b96", VReg_96>;
574defm DS_WRITE_B128 : DS_1A1D_NORET_mc<"ds_write_b128", VReg_128>;
575} // End mayLoad = 0
576
577def DS_NOP : DS_VOID<"ds_nop">;
578
579} // let SubtargetPredicate = isGFX7Plus
580
581//===----------------------------------------------------------------------===//
582// Instruction definitions for VI and newer.
583//===----------------------------------------------------------------------===//
584
585let SubtargetPredicate = isGFX8Plus in {
586
587let Uses = [EXEC] in {
588def DS_PERMUTE_B32  : DS_1A1D_PERMUTE <"ds_permute_b32",
589                                       int_amdgcn_ds_permute>;
590def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
591                                       int_amdgcn_ds_bpermute>;
592}
593
594def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
595
596} // let SubtargetPredicate = isGFX8Plus
597
598//===----------------------------------------------------------------------===//
599// DS Patterns
600//===----------------------------------------------------------------------===//
601
602def : GCNPat <
603  (int_amdgcn_ds_swizzle i32:$src, imm:$offset16),
604  (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
605>;
606
607class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
608  (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
609  (inst $ptr, (as_i16imm $offset), (i1 gds))
610>;
611
612multiclass DSReadPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
613
614  let OtherPredicates = [LDSRequiresM0Init] in {
615    def : DSReadPat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
616  }
617
618  let OtherPredicates = [NotLDSRequiresM0Init] in {
619    def : DSReadPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
620  }
621}
622
623class DSReadPat_D16 <DS_Pseudo inst, PatFrag frag, ValueType vt> : GCNPat <
624  (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$in),
625  (inst $ptr, (as_i16imm $offset), (i1 0), $in)
626>;
627
628defm : DSReadPat_mc <DS_READ_I8, i32, "sextloadi8_local">;
629defm : DSReadPat_mc <DS_READ_I8,  i16, "sextloadi8_local">;
630defm : DSReadPat_mc <DS_READ_U8,  i32, "extloadi8_local">;
631defm : DSReadPat_mc <DS_READ_U8,  i32, "zextloadi8_local">;
632defm : DSReadPat_mc <DS_READ_U8,  i16, "extloadi8_local">;
633defm : DSReadPat_mc <DS_READ_U8,  i16, "zextloadi8_local">;
634defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
635defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
636defm : DSReadPat_mc <DS_READ_U16, i32, "extloadi16_local">;
637defm : DSReadPat_mc <DS_READ_U16, i32, "zextloadi16_local">;
638defm : DSReadPat_mc <DS_READ_U16, i16, "load_local">;
639defm : DSReadPat_mc <DS_READ_B32, i32, "load_local">;
640defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_32_local">;
641defm : DSReadPat_mc <DS_READ_B64, i64, "atomic_load_64_local">;
642
643let AddedComplexity = 100 in {
644
645defm : DSReadPat_mc <DS_READ_B64, v2i32, "load_align8_local">;
646defm : DSReadPat_mc <DS_READ_B128, v4i32, "load_align16_local">;
647
648} // End AddedComplexity = 100
649
650let OtherPredicates = [D16PreservesUnusedBits] in {
651def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2i16>;
652def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2f16>;
653def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2i16>;
654def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2f16>;
655def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2i16>;
656def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2f16>;
657
658def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2i16>;
659def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2f16>;
660def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2i16>;
661def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2f16>;
662def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2i16>;
663def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2f16>;
664}
665
666class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
667  (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
668  (inst $ptr, $value, (as_i16imm $offset), (i1 gds))
669>;
670
671multiclass DSWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
672  let OtherPredicates = [LDSRequiresM0Init] in {
673    def : DSWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
674  }
675
676  let OtherPredicates = [NotLDSRequiresM0Init] in {
677    def : DSWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
678  }
679}
680
681// Irritatingly, atomic_store reverses the order of operands from a
682// normal store.
683class DSAtomicWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
684  (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
685  (inst $ptr, $value, (as_i16imm $offset), (i1 0))
686>;
687
688multiclass DSAtomicWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
689  let OtherPredicates = [LDSRequiresM0Init] in {
690    def : DSAtomicWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
691  }
692
693  let OtherPredicates = [NotLDSRequiresM0Init] in {
694    def : DSAtomicWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
695  }
696}
697
698defm : DSWritePat_mc <DS_WRITE_B8, i32, "truncstorei8_local">;
699defm : DSWritePat_mc <DS_WRITE_B16, i32, "truncstorei16_local">;
700defm : DSWritePat_mc <DS_WRITE_B8, i16, "truncstorei8_local">;
701defm : DSWritePat_mc <DS_WRITE_B16, i16, "store_local">;
702defm : DSWritePat_mc <DS_WRITE_B32, i32, "store_local">;
703defm : DSAtomicWritePat_mc <DS_WRITE_B32, i32, "atomic_store_local">;
704defm : DSAtomicWritePat_mc <DS_WRITE_B64, i64, "atomic_store_local">;
705
706let OtherPredicates = [D16PreservesUnusedBits] in {
707def : DSWritePat <DS_WRITE_B16_D16_HI, i32, store_local_hi16>;
708def : DSWritePat <DS_WRITE_B8_D16_HI, i32, truncstorei8_local_hi16>;
709}
710
711
712class DS64Bit4ByteAlignedReadPat<DS_Pseudo inst, PatFrag frag> : GCNPat <
713  (v2i32 (frag (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))),
714  (inst $ptr, $offset0, $offset1, (i1 0))
715>;
716
717class DS64Bit4ByteAlignedWritePat<DS_Pseudo inst, PatFrag frag> : GCNPat<
718  (frag v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1)),
719  (inst $ptr, (i32 (EXTRACT_SUBREG $value, sub0)),
720              (i32 (EXTRACT_SUBREG $value, sub1)), $offset0, $offset1,
721              (i1 0))
722>;
723
724// v2i32 loads are split into i32 loads on SI during lowering, due to a bug
725// related to bounds checking.
726let OtherPredicates = [LDSRequiresM0Init, isGFX7Plus] in {
727def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32, load_local_m0>;
728def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32, store_local_m0>;
729}
730
731let OtherPredicates = [NotLDSRequiresM0Init] in {
732def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32_gfx9, load_local>;
733def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32_gfx9, store_local>;
734}
735
736
737let AddedComplexity = 100 in {
738
739defm : DSWritePat_mc <DS_WRITE_B64, v2i32, "store_align8_local">;
740defm : DSWritePat_mc <DS_WRITE_B128, v4i32, "store_align16_local">;
741
742} // End AddedComplexity = 100
743class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
744  (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
745  (inst $ptr, $value, (as_i16imm $offset), (i1 gds))
746>;
747
748multiclass DSAtomicRetPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
749  let OtherPredicates = [LDSRequiresM0Init] in {
750    def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_local_m0")>;
751  }
752
753  let OtherPredicates = [NotLDSRequiresM0Init] in {
754    def : DSAtomicRetPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
755                         !cast<PatFrag>(frag#"_local")>;
756  }
757
758  def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_region_m0"), 1>;
759}
760
761
762
763class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
764  (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
765  (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 gds))
766>;
767
768multiclass DSAtomicCmpXChg_mc<DS_Pseudo inst, ValueType vt, string frag> {
769  let OtherPredicates = [LDSRequiresM0Init] in {
770    def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_local_m0")>;
771  }
772
773  let OtherPredicates = [NotLDSRequiresM0Init] in {
774    def : DSAtomicCmpXChg<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
775                          !cast<PatFrag>(frag#"_local")>;
776  }
777
778  def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_region_m0"), 1>;
779}
780
781
782
783// 32-bit atomics.
784defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B32, i32, "atomic_swap">;
785defm : DSAtomicRetPat_mc<DS_ADD_RTN_U32, i32, "atomic_load_add">;
786defm : DSAtomicRetPat_mc<DS_SUB_RTN_U32, i32, "atomic_load_sub">;
787defm : DSAtomicRetPat_mc<DS_INC_RTN_U32, i32, "atomic_inc">;
788defm : DSAtomicRetPat_mc<DS_DEC_RTN_U32, i32, "atomic_dec">;
789defm : DSAtomicRetPat_mc<DS_AND_RTN_B32, i32, "atomic_load_and">;
790defm : DSAtomicRetPat_mc<DS_OR_RTN_B32, i32, "atomic_load_or">;
791defm : DSAtomicRetPat_mc<DS_XOR_RTN_B32, i32, "atomic_load_xor">;
792defm : DSAtomicRetPat_mc<DS_MIN_RTN_I32, i32, "atomic_load_min">;
793defm : DSAtomicRetPat_mc<DS_MAX_RTN_I32, i32, "atomic_load_max">;
794defm : DSAtomicRetPat_mc<DS_MIN_RTN_U32, i32, "atomic_load_umin">;
795defm : DSAtomicRetPat_mc<DS_MAX_RTN_U32, i32, "atomic_load_umax">;
796defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B32, i32, "atomic_cmp_swap">;
797defm : DSAtomicRetPat_mc<DS_MIN_RTN_F32, f32, "atomic_load_fmin">;
798defm : DSAtomicRetPat_mc<DS_MAX_RTN_F32, f32, "atomic_load_fmax">;
799defm : DSAtomicRetPat_mc<DS_ADD_RTN_F32, f32, "atomic_load_fadd">;
800
801// 64-bit atomics.
802defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B64, i64, "atomic_swap">;
803defm : DSAtomicRetPat_mc<DS_ADD_RTN_U64, i64, "atomic_load_add">;
804defm : DSAtomicRetPat_mc<DS_SUB_RTN_U64, i64, "atomic_load_sub">;
805defm : DSAtomicRetPat_mc<DS_INC_RTN_U64, i64, "atomic_inc">;
806defm : DSAtomicRetPat_mc<DS_DEC_RTN_U64, i64, "atomic_dec">;
807defm : DSAtomicRetPat_mc<DS_AND_RTN_B64, i64, "atomic_load_and">;
808defm : DSAtomicRetPat_mc<DS_OR_RTN_B64, i64, "atomic_load_or">;
809defm : DSAtomicRetPat_mc<DS_XOR_RTN_B64, i64, "atomic_load_xor">;
810defm : DSAtomicRetPat_mc<DS_MIN_RTN_I64, i64, "atomic_load_min">;
811defm : DSAtomicRetPat_mc<DS_MAX_RTN_I64, i64, "atomic_load_max">;
812defm : DSAtomicRetPat_mc<DS_MIN_RTN_U64, i64, "atomic_load_umin">;
813defm : DSAtomicRetPat_mc<DS_MAX_RTN_U64, i64, "atomic_load_umax">;
814
815defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B64, i64, "atomic_cmp_swap">;
816
817def : Pat <
818  (SIds_ordered_count i32:$value, i16:$offset),
819  (DS_ORDERED_COUNT $value, (as_i16imm $offset))
820>;
821
822//===----------------------------------------------------------------------===//
823// Target-specific instruction encodings.
824//===----------------------------------------------------------------------===//
825
826//===----------------------------------------------------------------------===//
827// Base ENC_DS for GFX6, GFX7, GFX10.
828//===----------------------------------------------------------------------===//
829
830class Base_DS_Real_gfx6_gfx7_gfx10<bits<8> op, DS_Pseudo ps, int ef> :
831    DS_Real<ps>, SIMCInstr <ps.Mnemonic, ef> {
832
833  let Inst{7-0}   = !if(ps.has_offset0, offset0, 0);
834  let Inst{15-8}  = !if(ps.has_offset1, offset1, 0);
835  let Inst{17}    = !if(ps.has_gds, gds, ps.gdsValue);
836  let Inst{25-18} = op;
837  let Inst{31-26} = 0x36;
838  let Inst{39-32} = !if(ps.has_addr, addr, !if(ps.has_gws_data0, data0, 0));
839  let Inst{47-40} = !if(ps.has_data0, data0, 0);
840  let Inst{55-48} = !if(ps.has_data1, data1, 0);
841  let Inst{63-56} = !if(ps.has_vdst, vdst, 0);
842}
843
844//===----------------------------------------------------------------------===//
845// GFX10.
846//===----------------------------------------------------------------------===//
847
848let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
849  multiclass DS_Real_gfx10<bits<8> op>  {
850    def _gfx10 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
851                                              SIEncodingFamily.GFX10>;
852  }
853} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
854
855defm DS_ADD_F32          : DS_Real_gfx10<0x015>;
856defm DS_ADD_RTN_F32      : DS_Real_gfx10<0x055>;
857defm DS_ADD_SRC2_F32     : DS_Real_gfx10<0x095>;
858defm DS_WRITE_B8_D16_HI  : DS_Real_gfx10<0x0a0>;
859defm DS_WRITE_B16_D16_HI : DS_Real_gfx10<0x0a1>;
860defm DS_READ_U8_D16      : DS_Real_gfx10<0x0a2>;
861defm DS_READ_U8_D16_HI   : DS_Real_gfx10<0x0a3>;
862defm DS_READ_I8_D16      : DS_Real_gfx10<0x0a4>;
863defm DS_READ_I8_D16_HI   : DS_Real_gfx10<0x0a5>;
864defm DS_READ_U16_D16     : DS_Real_gfx10<0x0a6>;
865defm DS_READ_U16_D16_HI  : DS_Real_gfx10<0x0a7>;
866defm DS_WRITE_ADDTID_B32 : DS_Real_gfx10<0x0b0>;
867defm DS_READ_ADDTID_B32  : DS_Real_gfx10<0x0b1>;
868defm DS_PERMUTE_B32      : DS_Real_gfx10<0x0b2>;
869defm DS_BPERMUTE_B32     : DS_Real_gfx10<0x0b3>;
870
871//===----------------------------------------------------------------------===//
872// GFX7, GFX10.
873//===----------------------------------------------------------------------===//
874
875let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {
876  multiclass DS_Real_gfx7<bits<8> op> {
877    def _gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
878                                             SIEncodingFamily.SI>;
879  }
880} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7"
881
882multiclass DS_Real_gfx7_gfx10<bits<8> op> :
883  DS_Real_gfx7<op>, DS_Real_gfx10<op>;
884
885// FIXME-GFX7: Add tests when upstreaming this part.
886defm DS_GWS_SEMA_RELEASE_ALL : DS_Real_gfx7_gfx10<0x018>;
887defm DS_WRAP_RTN_B32         : DS_Real_gfx7_gfx10<0x034>;
888defm DS_CONDXCHG32_RTN_B64   : DS_Real_gfx7_gfx10<0x07e>;
889defm DS_WRITE_B96            : DS_Real_gfx7_gfx10<0x0de>;
890defm DS_WRITE_B128           : DS_Real_gfx7_gfx10<0x0df>;
891defm DS_READ_B96             : DS_Real_gfx7_gfx10<0x0fe>;
892defm DS_READ_B128            : DS_Real_gfx7_gfx10<0x0ff>;
893
894//===----------------------------------------------------------------------===//
895// GFX6, GFX7, GFX10.
896//===----------------------------------------------------------------------===//
897
898let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
899  multiclass DS_Real_gfx6_gfx7<bits<8> op> {
900    def _gfx6_gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
901                                                  SIEncodingFamily.SI>;
902  }
903} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
904
905multiclass DS_Real_gfx6_gfx7_gfx10<bits<8> op> :
906  DS_Real_gfx6_gfx7<op>, DS_Real_gfx10<op>;
907
908defm DS_ADD_U32             : DS_Real_gfx6_gfx7_gfx10<0x000>;
909defm DS_SUB_U32             : DS_Real_gfx6_gfx7_gfx10<0x001>;
910defm DS_RSUB_U32            : DS_Real_gfx6_gfx7_gfx10<0x002>;
911defm DS_INC_U32             : DS_Real_gfx6_gfx7_gfx10<0x003>;
912defm DS_DEC_U32             : DS_Real_gfx6_gfx7_gfx10<0x004>;
913defm DS_MIN_I32             : DS_Real_gfx6_gfx7_gfx10<0x005>;
914defm DS_MAX_I32             : DS_Real_gfx6_gfx7_gfx10<0x006>;
915defm DS_MIN_U32             : DS_Real_gfx6_gfx7_gfx10<0x007>;
916defm DS_MAX_U32             : DS_Real_gfx6_gfx7_gfx10<0x008>;
917defm DS_AND_B32             : DS_Real_gfx6_gfx7_gfx10<0x009>;
918defm DS_OR_B32              : DS_Real_gfx6_gfx7_gfx10<0x00a>;
919defm DS_XOR_B32             : DS_Real_gfx6_gfx7_gfx10<0x00b>;
920defm DS_MSKOR_B32           : DS_Real_gfx6_gfx7_gfx10<0x00c>;
921defm DS_WRITE_B32           : DS_Real_gfx6_gfx7_gfx10<0x00d>;
922defm DS_WRITE2_B32          : DS_Real_gfx6_gfx7_gfx10<0x00e>;
923defm DS_WRITE2ST64_B32      : DS_Real_gfx6_gfx7_gfx10<0x00f>;
924defm DS_CMPST_B32           : DS_Real_gfx6_gfx7_gfx10<0x010>;
925defm DS_CMPST_F32           : DS_Real_gfx6_gfx7_gfx10<0x011>;
926defm DS_MIN_F32             : DS_Real_gfx6_gfx7_gfx10<0x012>;
927defm DS_MAX_F32             : DS_Real_gfx6_gfx7_gfx10<0x013>;
928defm DS_NOP                 : DS_Real_gfx6_gfx7_gfx10<0x014>;
929defm DS_GWS_INIT            : DS_Real_gfx6_gfx7_gfx10<0x019>;
930defm DS_GWS_SEMA_V          : DS_Real_gfx6_gfx7_gfx10<0x01a>;
931defm DS_GWS_SEMA_BR         : DS_Real_gfx6_gfx7_gfx10<0x01b>;
932defm DS_GWS_SEMA_P          : DS_Real_gfx6_gfx7_gfx10<0x01c>;
933defm DS_GWS_BARRIER         : DS_Real_gfx6_gfx7_gfx10<0x01d>;
934defm DS_WRITE_B8            : DS_Real_gfx6_gfx7_gfx10<0x01e>;
935defm DS_WRITE_B16           : DS_Real_gfx6_gfx7_gfx10<0x01f>;
936defm DS_ADD_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x020>;
937defm DS_SUB_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x021>;
938defm DS_RSUB_RTN_U32        : DS_Real_gfx6_gfx7_gfx10<0x022>;
939defm DS_INC_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x023>;
940defm DS_DEC_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x024>;
941defm DS_MIN_RTN_I32         : DS_Real_gfx6_gfx7_gfx10<0x025>;
942defm DS_MAX_RTN_I32         : DS_Real_gfx6_gfx7_gfx10<0x026>;
943defm DS_MIN_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x027>;
944defm DS_MAX_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x028>;
945defm DS_AND_RTN_B32         : DS_Real_gfx6_gfx7_gfx10<0x029>;
946defm DS_OR_RTN_B32          : DS_Real_gfx6_gfx7_gfx10<0x02a>;
947defm DS_XOR_RTN_B32         : DS_Real_gfx6_gfx7_gfx10<0x02b>;
948defm DS_MSKOR_RTN_B32       : DS_Real_gfx6_gfx7_gfx10<0x02c>;
949defm DS_WRXCHG_RTN_B32      : DS_Real_gfx6_gfx7_gfx10<0x02d>;
950defm DS_WRXCHG2_RTN_B32     : DS_Real_gfx6_gfx7_gfx10<0x02e>;
951defm DS_WRXCHG2ST64_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02f>;
952defm DS_CMPST_RTN_B32       : DS_Real_gfx6_gfx7_gfx10<0x030>;
953defm DS_CMPST_RTN_F32       : DS_Real_gfx6_gfx7_gfx10<0x031>;
954defm DS_MIN_RTN_F32         : DS_Real_gfx6_gfx7_gfx10<0x032>;
955defm DS_MAX_RTN_F32         : DS_Real_gfx6_gfx7_gfx10<0x033>;
956defm DS_SWIZZLE_B32         : DS_Real_gfx6_gfx7_gfx10<0x035>;
957defm DS_READ_B32            : DS_Real_gfx6_gfx7_gfx10<0x036>;
958defm DS_READ2_B32           : DS_Real_gfx6_gfx7_gfx10<0x037>;
959defm DS_READ2ST64_B32       : DS_Real_gfx6_gfx7_gfx10<0x038>;
960defm DS_READ_I8             : DS_Real_gfx6_gfx7_gfx10<0x039>;
961defm DS_READ_U8             : DS_Real_gfx6_gfx7_gfx10<0x03a>;
962defm DS_READ_I16            : DS_Real_gfx6_gfx7_gfx10<0x03b>;
963defm DS_READ_U16            : DS_Real_gfx6_gfx7_gfx10<0x03c>;
964defm DS_CONSUME             : DS_Real_gfx6_gfx7_gfx10<0x03d>;
965defm DS_APPEND              : DS_Real_gfx6_gfx7_gfx10<0x03e>;
966defm DS_ORDERED_COUNT       : DS_Real_gfx6_gfx7_gfx10<0x03f>;
967defm DS_ADD_U64             : DS_Real_gfx6_gfx7_gfx10<0x040>;
968defm DS_SUB_U64             : DS_Real_gfx6_gfx7_gfx10<0x041>;
969defm DS_RSUB_U64            : DS_Real_gfx6_gfx7_gfx10<0x042>;
970defm DS_INC_U64             : DS_Real_gfx6_gfx7_gfx10<0x043>;
971defm DS_DEC_U64             : DS_Real_gfx6_gfx7_gfx10<0x044>;
972defm DS_MIN_I64             : DS_Real_gfx6_gfx7_gfx10<0x045>;
973defm DS_MAX_I64             : DS_Real_gfx6_gfx7_gfx10<0x046>;
974defm DS_MIN_U64             : DS_Real_gfx6_gfx7_gfx10<0x047>;
975defm DS_MAX_U64             : DS_Real_gfx6_gfx7_gfx10<0x048>;
976defm DS_AND_B64             : DS_Real_gfx6_gfx7_gfx10<0x049>;
977defm DS_OR_B64              : DS_Real_gfx6_gfx7_gfx10<0x04a>;
978defm DS_XOR_B64             : DS_Real_gfx6_gfx7_gfx10<0x04b>;
979defm DS_MSKOR_B64           : DS_Real_gfx6_gfx7_gfx10<0x04c>;
980defm DS_WRITE_B64           : DS_Real_gfx6_gfx7_gfx10<0x04d>;
981defm DS_WRITE2_B64          : DS_Real_gfx6_gfx7_gfx10<0x04e>;
982defm DS_WRITE2ST64_B64      : DS_Real_gfx6_gfx7_gfx10<0x04f>;
983defm DS_CMPST_B64           : DS_Real_gfx6_gfx7_gfx10<0x050>;
984defm DS_CMPST_F64           : DS_Real_gfx6_gfx7_gfx10<0x051>;
985defm DS_MIN_F64             : DS_Real_gfx6_gfx7_gfx10<0x052>;
986defm DS_MAX_F64             : DS_Real_gfx6_gfx7_gfx10<0x053>;
987defm DS_ADD_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x060>;
988defm DS_SUB_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x061>;
989defm DS_RSUB_RTN_U64        : DS_Real_gfx6_gfx7_gfx10<0x062>;
990defm DS_INC_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x063>;
991defm DS_DEC_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x064>;
992defm DS_MIN_RTN_I64         : DS_Real_gfx6_gfx7_gfx10<0x065>;
993defm DS_MAX_RTN_I64         : DS_Real_gfx6_gfx7_gfx10<0x066>;
994defm DS_MIN_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x067>;
995defm DS_MAX_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x068>;
996defm DS_AND_RTN_B64         : DS_Real_gfx6_gfx7_gfx10<0x069>;
997defm DS_OR_RTN_B64          : DS_Real_gfx6_gfx7_gfx10<0x06a>;
998defm DS_XOR_RTN_B64         : DS_Real_gfx6_gfx7_gfx10<0x06b>;
999defm DS_MSKOR_RTN_B64       : DS_Real_gfx6_gfx7_gfx10<0x06c>;
1000defm DS_WRXCHG_RTN_B64      : DS_Real_gfx6_gfx7_gfx10<0x06d>;
1001defm DS_WRXCHG2_RTN_B64     : DS_Real_gfx6_gfx7_gfx10<0x06e>;
1002defm DS_WRXCHG2ST64_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06f>;
1003defm DS_CMPST_RTN_B64       : DS_Real_gfx6_gfx7_gfx10<0x070>;
1004defm DS_CMPST_RTN_F64       : DS_Real_gfx6_gfx7_gfx10<0x071>;
1005defm DS_MIN_RTN_F64         : DS_Real_gfx6_gfx7_gfx10<0x072>;
1006defm DS_MAX_RTN_F64         : DS_Real_gfx6_gfx7_gfx10<0x073>;
1007defm DS_READ_B64            : DS_Real_gfx6_gfx7_gfx10<0x076>;
1008defm DS_READ2_B64           : DS_Real_gfx6_gfx7_gfx10<0x077>;
1009defm DS_READ2ST64_B64       : DS_Real_gfx6_gfx7_gfx10<0x078>;
1010defm DS_ADD_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x080>;
1011defm DS_SUB_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x081>;
1012defm DS_RSUB_SRC2_U32       : DS_Real_gfx6_gfx7_gfx10<0x082>;
1013defm DS_INC_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x083>;
1014defm DS_DEC_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x084>;
1015defm DS_MIN_SRC2_I32        : DS_Real_gfx6_gfx7_gfx10<0x085>;
1016defm DS_MAX_SRC2_I32        : DS_Real_gfx6_gfx7_gfx10<0x086>;
1017defm DS_MIN_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x087>;
1018defm DS_MAX_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x088>;
1019defm DS_AND_SRC2_B32        : DS_Real_gfx6_gfx7_gfx10<0x089>;
1020defm DS_OR_SRC2_B32         : DS_Real_gfx6_gfx7_gfx10<0x08a>;
1021defm DS_XOR_SRC2_B32        : DS_Real_gfx6_gfx7_gfx10<0x08b>;
1022defm DS_WRITE_SRC2_B32      : DS_Real_gfx6_gfx7_gfx10<0x08d>;
1023defm DS_MIN_SRC2_F32        : DS_Real_gfx6_gfx7_gfx10<0x092>;
1024defm DS_MAX_SRC2_F32        : DS_Real_gfx6_gfx7_gfx10<0x093>;
1025defm DS_ADD_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c0>;
1026defm DS_SUB_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c1>;
1027defm DS_RSUB_SRC2_U64       : DS_Real_gfx6_gfx7_gfx10<0x0c2>;
1028defm DS_INC_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c3>;
1029defm DS_DEC_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c4>;
1030defm DS_MIN_SRC2_I64        : DS_Real_gfx6_gfx7_gfx10<0x0c5>;
1031defm DS_MAX_SRC2_I64        : DS_Real_gfx6_gfx7_gfx10<0x0c6>;
1032defm DS_MIN_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c7>;
1033defm DS_MAX_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c8>;
1034defm DS_AND_SRC2_B64        : DS_Real_gfx6_gfx7_gfx10<0x0c9>;
1035defm DS_OR_SRC2_B64         : DS_Real_gfx6_gfx7_gfx10<0x0ca>;
1036defm DS_XOR_SRC2_B64        : DS_Real_gfx6_gfx7_gfx10<0x0cb>;
1037defm DS_WRITE_SRC2_B64      : DS_Real_gfx6_gfx7_gfx10<0x0cd>;
1038defm DS_MIN_SRC2_F64        : DS_Real_gfx6_gfx7_gfx10<0x0d2>;
1039defm DS_MAX_SRC2_F64        : DS_Real_gfx6_gfx7_gfx10<0x0d3>;
1040
1041//===----------------------------------------------------------------------===//
1042// GFX8, GFX9 (VI).
1043//===----------------------------------------------------------------------===//
1044
1045class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
1046  DS_Real <ds>,
1047  SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
1048  let AssemblerPredicates = [isGFX8GFX9];
1049  let DecoderNamespace = "GFX8";
1050
1051  // encoding
1052  let Inst{7-0}   = !if(ds.has_offset0, offset0, 0);
1053  let Inst{15-8}  = !if(ds.has_offset1, offset1, 0);
1054  let Inst{16}    = !if(ds.has_gds, gds, ds.gdsValue);
1055  let Inst{24-17} = op;
1056  let Inst{31-26} = 0x36; // ds prefix
1057  let Inst{39-32} = !if(ds.has_addr, addr, !if(ds.has_gws_data0, data0, 0));
1058  let Inst{47-40} = !if(ds.has_data0, data0, 0);
1059  let Inst{55-48} = !if(ds.has_data1, data1, 0);
1060  let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
1061}
1062
1063def DS_ADD_U32_vi         : DS_Real_vi<0x0,  DS_ADD_U32>;
1064def DS_SUB_U32_vi         : DS_Real_vi<0x1,  DS_SUB_U32>;
1065def DS_RSUB_U32_vi        : DS_Real_vi<0x2,  DS_RSUB_U32>;
1066def DS_INC_U32_vi         : DS_Real_vi<0x3,  DS_INC_U32>;
1067def DS_DEC_U32_vi         : DS_Real_vi<0x4,  DS_DEC_U32>;
1068def DS_MIN_I32_vi         : DS_Real_vi<0x5,  DS_MIN_I32>;
1069def DS_MAX_I32_vi         : DS_Real_vi<0x6,  DS_MAX_I32>;
1070def DS_MIN_U32_vi         : DS_Real_vi<0x7,  DS_MIN_U32>;
1071def DS_MAX_U32_vi         : DS_Real_vi<0x8,  DS_MAX_U32>;
1072def DS_AND_B32_vi         : DS_Real_vi<0x9,  DS_AND_B32>;
1073def DS_OR_B32_vi          : DS_Real_vi<0xa,  DS_OR_B32>;
1074def DS_XOR_B32_vi         : DS_Real_vi<0xb,  DS_XOR_B32>;
1075def DS_MSKOR_B32_vi       : DS_Real_vi<0xc,  DS_MSKOR_B32>;
1076def DS_WRITE_B32_vi       : DS_Real_vi<0xd,  DS_WRITE_B32>;
1077def DS_WRITE2_B32_vi      : DS_Real_vi<0xe,  DS_WRITE2_B32>;
1078def DS_WRITE2ST64_B32_vi  : DS_Real_vi<0xf,  DS_WRITE2ST64_B32>;
1079def DS_CMPST_B32_vi       : DS_Real_vi<0x10, DS_CMPST_B32>;
1080def DS_CMPST_F32_vi       : DS_Real_vi<0x11, DS_CMPST_F32>;
1081def DS_MIN_F32_vi         : DS_Real_vi<0x12, DS_MIN_F32>;
1082def DS_MAX_F32_vi         : DS_Real_vi<0x13, DS_MAX_F32>;
1083def DS_NOP_vi             : DS_Real_vi<0x14, DS_NOP>;
1084def DS_ADD_F32_vi         : DS_Real_vi<0x15, DS_ADD_F32>;
1085def DS_GWS_INIT_vi        : DS_Real_vi<0x99, DS_GWS_INIT>;
1086def DS_GWS_SEMA_V_vi      : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
1087def DS_GWS_SEMA_BR_vi     : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
1088def DS_GWS_SEMA_P_vi      : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
1089def DS_GWS_BARRIER_vi     : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
1090def DS_WRITE_ADDTID_B32_vi : DS_Real_vi<0x1d, DS_WRITE_ADDTID_B32>;
1091def DS_WRITE_B8_vi        : DS_Real_vi<0x1e, DS_WRITE_B8>;
1092def DS_WRITE_B16_vi       : DS_Real_vi<0x1f, DS_WRITE_B16>;
1093def DS_ADD_RTN_U32_vi     : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
1094def DS_SUB_RTN_U32_vi     : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
1095def DS_RSUB_RTN_U32_vi    : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
1096def DS_INC_RTN_U32_vi     : DS_Real_vi<0x23, DS_INC_RTN_U32>;
1097def DS_DEC_RTN_U32_vi     : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
1098def DS_MIN_RTN_I32_vi     : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
1099def DS_MAX_RTN_I32_vi     : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
1100def DS_MIN_RTN_U32_vi     : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
1101def DS_MAX_RTN_U32_vi     : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
1102def DS_AND_RTN_B32_vi     : DS_Real_vi<0x29, DS_AND_RTN_B32>;
1103def DS_OR_RTN_B32_vi      : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
1104def DS_XOR_RTN_B32_vi     : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
1105def DS_MSKOR_RTN_B32_vi   : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
1106def DS_WRXCHG_RTN_B32_vi  : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
1107def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
1108def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
1109def DS_CMPST_RTN_B32_vi   : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
1110def DS_CMPST_RTN_F32_vi   : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
1111def DS_MIN_RTN_F32_vi     : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
1112def DS_MAX_RTN_F32_vi     : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
1113def DS_WRAP_RTN_B32_vi    : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
1114def DS_ADD_RTN_F32_vi     : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
1115def DS_READ_B32_vi        : DS_Real_vi<0x36, DS_READ_B32>;
1116def DS_READ2_B32_vi       : DS_Real_vi<0x37, DS_READ2_B32>;
1117def DS_READ2ST64_B32_vi   : DS_Real_vi<0x38, DS_READ2ST64_B32>;
1118def DS_READ_I8_vi         : DS_Real_vi<0x39, DS_READ_I8>;
1119def DS_READ_U8_vi         : DS_Real_vi<0x3a, DS_READ_U8>;
1120def DS_READ_I16_vi        : DS_Real_vi<0x3b, DS_READ_I16>;
1121def DS_READ_U16_vi        : DS_Real_vi<0x3c, DS_READ_U16>;
1122def DS_READ_ADDTID_B32_vi : DS_Real_vi<0xb6, DS_READ_ADDTID_B32>;
1123def DS_CONSUME_vi         : DS_Real_vi<0xbd, DS_CONSUME>;
1124def DS_APPEND_vi          : DS_Real_vi<0xbe, DS_APPEND>;
1125def DS_ORDERED_COUNT_vi   : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
1126def DS_SWIZZLE_B32_vi     : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
1127def DS_PERMUTE_B32_vi     : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
1128def DS_BPERMUTE_B32_vi    : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
1129
1130def DS_ADD_U64_vi         : DS_Real_vi<0x40, DS_ADD_U64>;
1131def DS_SUB_U64_vi         : DS_Real_vi<0x41, DS_SUB_U64>;
1132def DS_RSUB_U64_vi        : DS_Real_vi<0x42, DS_RSUB_U64>;
1133def DS_INC_U64_vi         : DS_Real_vi<0x43, DS_INC_U64>;
1134def DS_DEC_U64_vi         : DS_Real_vi<0x44, DS_DEC_U64>;
1135def DS_MIN_I64_vi         : DS_Real_vi<0x45, DS_MIN_I64>;
1136def DS_MAX_I64_vi         : DS_Real_vi<0x46, DS_MAX_I64>;
1137def DS_MIN_U64_vi         : DS_Real_vi<0x47, DS_MIN_U64>;
1138def DS_MAX_U64_vi         : DS_Real_vi<0x48, DS_MAX_U64>;
1139def DS_AND_B64_vi         : DS_Real_vi<0x49, DS_AND_B64>;
1140def DS_OR_B64_vi          : DS_Real_vi<0x4a, DS_OR_B64>;
1141def DS_XOR_B64_vi         : DS_Real_vi<0x4b, DS_XOR_B64>;
1142def DS_MSKOR_B64_vi       : DS_Real_vi<0x4c, DS_MSKOR_B64>;
1143def DS_WRITE_B64_vi       : DS_Real_vi<0x4d, DS_WRITE_B64>;
1144def DS_WRITE2_B64_vi      : DS_Real_vi<0x4E, DS_WRITE2_B64>;
1145def DS_WRITE2ST64_B64_vi  : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
1146def DS_CMPST_B64_vi       : DS_Real_vi<0x50, DS_CMPST_B64>;
1147def DS_CMPST_F64_vi       : DS_Real_vi<0x51, DS_CMPST_F64>;
1148def DS_MIN_F64_vi         : DS_Real_vi<0x52, DS_MIN_F64>;
1149def DS_MAX_F64_vi         : DS_Real_vi<0x53, DS_MAX_F64>;
1150
1151def DS_WRITE_B8_D16_HI_vi  : DS_Real_vi<0x54, DS_WRITE_B8_D16_HI>;
1152def DS_WRITE_B16_D16_HI_vi : DS_Real_vi<0x55, DS_WRITE_B16_D16_HI>;
1153
1154def DS_READ_U8_D16_vi     : DS_Real_vi<0x56, DS_READ_U8_D16>;
1155def DS_READ_U8_D16_HI_vi  : DS_Real_vi<0x57, DS_READ_U8_D16_HI>;
1156def DS_READ_I8_D16_vi     : DS_Real_vi<0x58, DS_READ_I8_D16>;
1157def DS_READ_I8_D16_HI_vi  : DS_Real_vi<0x59, DS_READ_I8_D16_HI>;
1158def DS_READ_U16_D16_vi    : DS_Real_vi<0x5a, DS_READ_U16_D16>;
1159def DS_READ_U16_D16_HI_vi : DS_Real_vi<0x5b, DS_READ_U16_D16_HI>;
1160
1161def DS_ADD_RTN_U64_vi     : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
1162def DS_SUB_RTN_U64_vi     : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
1163def DS_RSUB_RTN_U64_vi    : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
1164def DS_INC_RTN_U64_vi     : DS_Real_vi<0x63, DS_INC_RTN_U64>;
1165def DS_DEC_RTN_U64_vi     : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
1166def DS_MIN_RTN_I64_vi     : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
1167def DS_MAX_RTN_I64_vi     : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
1168def DS_MIN_RTN_U64_vi     : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
1169def DS_MAX_RTN_U64_vi     : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
1170def DS_AND_RTN_B64_vi     : DS_Real_vi<0x69, DS_AND_RTN_B64>;
1171def DS_OR_RTN_B64_vi      : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
1172def DS_XOR_RTN_B64_vi     : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
1173def DS_MSKOR_RTN_B64_vi   : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
1174def DS_WRXCHG_RTN_B64_vi  : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
1175def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
1176def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
1177def DS_CONDXCHG32_RTN_B64_vi   : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
1178def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
1179def DS_CMPST_RTN_B64_vi   : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
1180def DS_CMPST_RTN_F64_vi   : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
1181def DS_MIN_RTN_F64_vi     : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
1182def DS_MAX_RTN_F64_vi     : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
1183
1184def DS_READ_B64_vi        : DS_Real_vi<0x76, DS_READ_B64>;
1185def DS_READ2_B64_vi       : DS_Real_vi<0x77, DS_READ2_B64>;
1186def DS_READ2ST64_B64_vi   : DS_Real_vi<0x78, DS_READ2ST64_B64>;
1187
1188def DS_ADD_SRC2_U32_vi    : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
1189def DS_SUB_SRC2_U32_vi    : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
1190def DS_RSUB_SRC2_U32_vi   : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
1191def DS_INC_SRC2_U32_vi    : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
1192def DS_DEC_SRC2_U32_vi    : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
1193def DS_MIN_SRC2_I32_vi    : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
1194def DS_MAX_SRC2_I32_vi    : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
1195def DS_MIN_SRC2_U32_vi    : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
1196def DS_MAX_SRC2_U32_vi    : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
1197def DS_AND_SRC2_B32_vi    : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
1198def DS_OR_SRC2_B32_vi     : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
1199def DS_XOR_SRC2_B32_vi    : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
1200def DS_WRITE_SRC2_B32_vi  : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
1201def DS_MIN_SRC2_F32_vi    : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
1202def DS_MAX_SRC2_F32_vi    : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
1203def DS_ADD_SRC2_F32_vi    : DS_Real_vi<0x95, DS_ADD_SRC2_F32>;
1204def DS_ADD_SRC2_U64_vi    : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
1205def DS_SUB_SRC2_U64_vi    : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
1206def DS_RSUB_SRC2_U64_vi   : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
1207def DS_INC_SRC2_U64_vi    : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
1208def DS_DEC_SRC2_U64_vi    : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
1209def DS_MIN_SRC2_I64_vi    : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
1210def DS_MAX_SRC2_I64_vi    : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
1211def DS_MIN_SRC2_U64_vi    : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
1212def DS_MAX_SRC2_U64_vi    : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
1213def DS_AND_SRC2_B64_vi    : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
1214def DS_OR_SRC2_B64_vi     : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
1215def DS_XOR_SRC2_B64_vi    : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
1216def DS_WRITE_SRC2_B64_vi  : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
1217def DS_MIN_SRC2_F64_vi    : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
1218def DS_MAX_SRC2_F64_vi    : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
1219def DS_WRITE_B96_vi       : DS_Real_vi<0xde, DS_WRITE_B96>;
1220def DS_WRITE_B128_vi      : DS_Real_vi<0xdf, DS_WRITE_B128>;
1221def DS_READ_B96_vi        : DS_Real_vi<0xfe, DS_READ_B96>;
1222def DS_READ_B128_vi       : DS_Real_vi<0xff, DS_READ_B128>;
1223