1 //===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// The AMDGPU TargetMachine interface definition for hw codgen targets. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H 15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H 16 17 #include "GCNSubtarget.h" 18 #include "llvm/CodeGen/TargetPassConfig.h" 19 #include "llvm/Target/TargetMachine.h" 20 #include <utility> 21 22 namespace llvm { 23 24 //===----------------------------------------------------------------------===// 25 // AMDGPU Target Machine (R600+) 26 //===----------------------------------------------------------------------===// 27 28 class AMDGPUTargetMachine : public LLVMTargetMachine { 29 protected: 30 std::unique_ptr<TargetLoweringObjectFile> TLOF; 31 32 StringRef getGPUName(const Function &F) const; 33 StringRef getFeatureString(const Function &F) const; 34 35 public: 36 static bool EnableLateStructurizeCFG; 37 static bool EnableFunctionCalls; 38 static bool EnableLowerModuleLDS; 39 40 AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU, 41 StringRef FS, TargetOptions Options, 42 Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, 43 CodeGenOpt::Level OL); 44 ~AMDGPUTargetMachine() override; 45 46 const TargetSubtargetInfo *getSubtargetImpl() const; 47 const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override = 0; 48 49 TargetLoweringObjectFile *getObjFileLowering() const override { 50 return TLOF.get(); 51 } 52 53 void adjustPassManager(PassManagerBuilder &) override; 54 55 void registerPassBuilderCallbacks(PassBuilder &PB) override; 56 void registerDefaultAliasAnalyses(AAManager &) override; 57 58 /// Get the integer value of a null pointer in the given address space. 59 static int64_t getNullPointerValue(unsigned AddrSpace); 60 61 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 62 63 unsigned getAssumedAddrSpace(const Value *V) const override; 64 65 std::pair<const Value *, unsigned> 66 getPredicatedAddrSpace(const Value *V) const override; 67 }; 68 69 //===----------------------------------------------------------------------===// 70 // GCN Target Machine (SI+) 71 //===----------------------------------------------------------------------===// 72 73 class GCNTargetMachine final : public AMDGPUTargetMachine { 74 private: 75 mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap; 76 77 public: 78 GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, 79 StringRef FS, TargetOptions Options, 80 Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, 81 CodeGenOpt::Level OL, bool JIT); 82 83 TargetPassConfig *createPassConfig(PassManagerBase &PM) override; 84 85 const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override; 86 87 TargetTransformInfo getTargetTransformInfo(const Function &F) override; 88 89 bool useIPRA() const override { 90 return true; 91 } 92 93 yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override; 94 yaml::MachineFunctionInfo * 95 convertFuncInfoToYAML(const MachineFunction &MF) const override; 96 bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, 97 PerFunctionMIParsingState &PFS, 98 SMDiagnostic &Error, 99 SMRange &SourceRange) const override; 100 }; 101 102 //===----------------------------------------------------------------------===// 103 // AMDGPU Pass Setup 104 //===----------------------------------------------------------------------===// 105 106 class AMDGPUPassConfig : public TargetPassConfig { 107 public: 108 AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM); 109 110 AMDGPUTargetMachine &getAMDGPUTargetMachine() const { 111 return getTM<AMDGPUTargetMachine>(); 112 } 113 114 ScheduleDAGInstrs * 115 createMachineScheduler(MachineSchedContext *C) const override; 116 117 void addEarlyCSEOrGVNPass(); 118 void addStraightLineScalarOptimizationPasses(); 119 void addIRPasses() override; 120 void addCodeGenPrepare() override; 121 bool addPreISel() override; 122 bool addInstSelector() override; 123 bool addGCPasses() override; 124 125 std::unique_ptr<CSEConfigBase> getCSEConfig() const override; 126 127 /// Check if a pass is enabled given \p Opt option. The option always 128 /// overrides defaults if explicitly used. Otherwise its default will 129 /// be used given that a pass shall work at an optimization \p Level 130 /// minimum. 131 bool isPassEnabled(const cl::opt<bool> &Opt, 132 CodeGenOpt::Level Level = CodeGenOpt::Default) const { 133 if (Opt.getNumOccurrences()) 134 return Opt; 135 if (TM->getOptLevel() < Level) 136 return false; 137 return Opt; 138 } 139 }; 140 141 } // end namespace llvm 142 143 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H 144