1 //===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// The AMDGPU TargetMachine interface definition for hw codegen targets. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H 15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H 16 17 #include "GCNSubtarget.h" 18 #include "llvm/CodeGen/TargetPassConfig.h" 19 #include "llvm/Target/TargetMachine.h" 20 #include <optional> 21 #include <utility> 22 23 namespace llvm { 24 25 //===----------------------------------------------------------------------===// 26 // AMDGPU Target Machine (R600+) 27 //===----------------------------------------------------------------------===// 28 29 class AMDGPUTargetMachine : public LLVMTargetMachine { 30 protected: 31 std::unique_ptr<TargetLoweringObjectFile> TLOF; 32 33 StringRef getGPUName(const Function &F) const; 34 StringRef getFeatureString(const Function &F) const; 35 36 public: 37 static bool EnableLateStructurizeCFG; 38 static bool EnableFunctionCalls; 39 static bool EnableLowerModuleLDS; 40 41 AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU, 42 StringRef FS, TargetOptions Options, 43 std::optional<Reloc::Model> RM, 44 std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL); 45 ~AMDGPUTargetMachine() override; 46 47 const TargetSubtargetInfo *getSubtargetImpl() const; 48 const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override = 0; 49 50 TargetLoweringObjectFile *getObjFileLowering() const override { 51 return TLOF.get(); 52 } 53 54 void registerPassBuilderCallbacks(PassBuilder &PB) override; 55 void registerDefaultAliasAnalyses(AAManager &) override; 56 57 /// Get the integer value of a null pointer in the given address space. 58 static int64_t getNullPointerValue(unsigned AddrSpace); 59 60 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 61 62 unsigned getAssumedAddrSpace(const Value *V) const override; 63 64 std::pair<const Value *, unsigned> 65 getPredicatedAddrSpace(const Value *V) const override; 66 67 unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override; 68 }; 69 70 //===----------------------------------------------------------------------===// 71 // GCN Target Machine (SI+) 72 //===----------------------------------------------------------------------===// 73 74 class GCNTargetMachine final : public AMDGPUTargetMachine { 75 private: 76 mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap; 77 78 public: 79 GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, 80 StringRef FS, TargetOptions Options, 81 std::optional<Reloc::Model> RM, 82 std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, 83 bool JIT); 84 85 TargetPassConfig *createPassConfig(PassManagerBase &PM) override; 86 87 const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override; 88 89 TargetTransformInfo getTargetTransformInfo(const Function &F) const override; 90 91 bool useIPRA() const override { 92 return true; 93 } 94 95 void registerMachineRegisterInfoCallback(MachineFunction &MF) const override; 96 97 MachineFunctionInfo * 98 createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, 99 const TargetSubtargetInfo *STI) const override; 100 101 yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override; 102 yaml::MachineFunctionInfo * 103 convertFuncInfoToYAML(const MachineFunction &MF) const override; 104 bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, 105 PerFunctionMIParsingState &PFS, 106 SMDiagnostic &Error, 107 SMRange &SourceRange) const override; 108 }; 109 110 //===----------------------------------------------------------------------===// 111 // AMDGPU Pass Setup 112 //===----------------------------------------------------------------------===// 113 114 class AMDGPUPassConfig : public TargetPassConfig { 115 public: 116 AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM); 117 118 AMDGPUTargetMachine &getAMDGPUTargetMachine() const { 119 return getTM<AMDGPUTargetMachine>(); 120 } 121 122 ScheduleDAGInstrs * 123 createMachineScheduler(MachineSchedContext *C) const override; 124 125 void addEarlyCSEOrGVNPass(); 126 void addStraightLineScalarOptimizationPasses(); 127 void addIRPasses() override; 128 void addCodeGenPrepare() override; 129 bool addPreISel() override; 130 bool addInstSelector() override; 131 bool addGCPasses() override; 132 133 std::unique_ptr<CSEConfigBase> getCSEConfig() const override; 134 135 /// Check if a pass is enabled given \p Opt option. The option always 136 /// overrides defaults if explicitly used. Otherwise its default will 137 /// be used given that a pass shall work at an optimization \p Level 138 /// minimum. 139 bool isPassEnabled(const cl::opt<bool> &Opt, 140 CodeGenOpt::Level Level = CodeGenOpt::Default) const { 141 if (Opt.getNumOccurrences()) 142 return Opt; 143 if (TM->getOptLevel() < Level) 144 return false; 145 return Opt; 146 } 147 }; 148 149 } // end namespace llvm 150 151 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H 152