1 //===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// The AMDGPU TargetMachine interface definition for hw codegen targets. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H 15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H 16 17 #include "GCNSubtarget.h" 18 #include "llvm/CodeGen/TargetPassConfig.h" 19 #include "llvm/Target/TargetMachine.h" 20 #include <utility> 21 22 namespace llvm { 23 24 //===----------------------------------------------------------------------===// 25 // AMDGPU Target Machine (R600+) 26 //===----------------------------------------------------------------------===// 27 28 class AMDGPUTargetMachine : public LLVMTargetMachine { 29 protected: 30 std::unique_ptr<TargetLoweringObjectFile> TLOF; 31 32 StringRef getGPUName(const Function &F) const; 33 StringRef getFeatureString(const Function &F) const; 34 35 public: 36 static bool EnableLateStructurizeCFG; 37 static bool EnableFunctionCalls; 38 static bool EnableLowerModuleLDS; 39 40 AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU, 41 StringRef FS, TargetOptions Options, 42 Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, 43 CodeGenOpt::Level OL); 44 ~AMDGPUTargetMachine() override; 45 46 const TargetSubtargetInfo *getSubtargetImpl() const; 47 const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override = 0; 48 49 TargetLoweringObjectFile *getObjFileLowering() const override { 50 return TLOF.get(); 51 } 52 53 void adjustPassManager(PassManagerBuilder &) override; 54 55 void registerPassBuilderCallbacks(PassBuilder &PB) override; 56 void registerDefaultAliasAnalyses(AAManager &) override; 57 58 /// Get the integer value of a null pointer in the given address space. 59 static int64_t getNullPointerValue(unsigned AddrSpace); 60 61 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 62 63 unsigned getAssumedAddrSpace(const Value *V) const override; 64 65 std::pair<const Value *, unsigned> 66 getPredicatedAddrSpace(const Value *V) const override; 67 68 unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override; 69 }; 70 71 //===----------------------------------------------------------------------===// 72 // GCN Target Machine (SI+) 73 //===----------------------------------------------------------------------===// 74 75 class GCNTargetMachine final : public AMDGPUTargetMachine { 76 private: 77 mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap; 78 79 public: 80 GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, 81 StringRef FS, TargetOptions Options, 82 Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, 83 CodeGenOpt::Level OL, bool JIT); 84 85 TargetPassConfig *createPassConfig(PassManagerBase &PM) override; 86 87 const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override; 88 89 TargetTransformInfo getTargetTransformInfo(const Function &F) const override; 90 91 bool useIPRA() const override { 92 return true; 93 } 94 95 yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override; 96 yaml::MachineFunctionInfo * 97 convertFuncInfoToYAML(const MachineFunction &MF) const override; 98 bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, 99 PerFunctionMIParsingState &PFS, 100 SMDiagnostic &Error, 101 SMRange &SourceRange) const override; 102 }; 103 104 //===----------------------------------------------------------------------===// 105 // AMDGPU Pass Setup 106 //===----------------------------------------------------------------------===// 107 108 class AMDGPUPassConfig : public TargetPassConfig { 109 public: 110 AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM); 111 112 AMDGPUTargetMachine &getAMDGPUTargetMachine() const { 113 return getTM<AMDGPUTargetMachine>(); 114 } 115 116 ScheduleDAGInstrs * 117 createMachineScheduler(MachineSchedContext *C) const override; 118 119 void addEarlyCSEOrGVNPass(); 120 void addStraightLineScalarOptimizationPasses(); 121 void addIRPasses() override; 122 void addCodeGenPrepare() override; 123 bool addPreISel() override; 124 bool addInstSelector() override; 125 bool addGCPasses() override; 126 127 std::unique_ptr<CSEConfigBase> getCSEConfig() const override; 128 129 /// Check if a pass is enabled given \p Opt option. The option always 130 /// overrides defaults if explicitly used. Otherwise its default will 131 /// be used given that a pass shall work at an optimization \p Level 132 /// minimum. 133 bool isPassEnabled(const cl::opt<bool> &Opt, 134 CodeGenOpt::Level Level = CodeGenOpt::Default) const { 135 if (Opt.getNumOccurrences()) 136 return Opt; 137 if (TM->getOptLevel() < Level) 138 return false; 139 return Opt; 140 } 141 }; 142 143 } // end namespace llvm 144 145 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H 146