xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (revision 5e801ac66d24704442eba426ed13c3effb8a34e7) 
1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for SI+ GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMacroFusion.h"
20 #include "AMDGPUTargetObjectFile.h"
21 #include "AMDGPUTargetTransformInfo.h"
22 #include "GCNIterativeScheduler.h"
23 #include "GCNSchedStrategy.h"
24 #include "R600.h"
25 #include "R600TargetMachine.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "SIMachineScheduler.h"
28 #include "TargetInfo/AMDGPUTargetInfo.h"
29 #include "llvm/Analysis/CGSCCPassManager.h"
30 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
31 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
32 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
33 #include "llvm/CodeGen/GlobalISel/Localizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MIRParser/MIParser.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/RegAllocRegistry.h"
38 #include "llvm/CodeGen/TargetPassConfig.h"
39 #include "llvm/IR/IntrinsicsAMDGPU.h"
40 #include "llvm/IR/LegacyPassManager.h"
41 #include "llvm/IR/PassManager.h"
42 #include "llvm/IR/PatternMatch.h"
43 #include "llvm/InitializePasses.h"
44 #include "llvm/MC/TargetRegistry.h"
45 #include "llvm/Passes/PassBuilder.h"
46 #include "llvm/Transforms/IPO.h"
47 #include "llvm/Transforms/IPO/AlwaysInliner.h"
48 #include "llvm/Transforms/IPO/GlobalDCE.h"
49 #include "llvm/Transforms/IPO/Internalize.h"
50 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
51 #include "llvm/Transforms/Scalar.h"
52 #include "llvm/Transforms/Scalar/GVN.h"
53 #include "llvm/Transforms/Scalar/InferAddressSpaces.h"
54 #include "llvm/Transforms/Utils.h"
55 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
56 #include "llvm/Transforms/Vectorize.h"
57 
58 using namespace llvm;
59 
60 namespace {
61 class SGPRRegisterRegAlloc : public RegisterRegAllocBase<SGPRRegisterRegAlloc> {
62 public:
63   SGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
64     : RegisterRegAllocBase(N, D, C) {}
65 };
66 
67 class VGPRRegisterRegAlloc : public RegisterRegAllocBase<VGPRRegisterRegAlloc> {
68 public:
69   VGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
70     : RegisterRegAllocBase(N, D, C) {}
71 };
72 
73 static bool onlyAllocateSGPRs(const TargetRegisterInfo &TRI,
74                               const TargetRegisterClass &RC) {
75   return static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
76 }
77 
78 static bool onlyAllocateVGPRs(const TargetRegisterInfo &TRI,
79                               const TargetRegisterClass &RC) {
80   return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
81 }
82 
83 
84 /// -{sgpr|vgpr}-regalloc=... command line option.
85 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
86 
87 /// A dummy default pass factory indicates whether the register allocator is
88 /// overridden on the command line.
89 static llvm::once_flag InitializeDefaultSGPRRegisterAllocatorFlag;
90 static llvm::once_flag InitializeDefaultVGPRRegisterAllocatorFlag;
91 
92 static SGPRRegisterRegAlloc
93 defaultSGPRRegAlloc("default",
94                     "pick SGPR register allocator based on -O option",
95                     useDefaultRegisterAllocator);
96 
97 static cl::opt<SGPRRegisterRegAlloc::FunctionPassCtor, false,
98                RegisterPassParser<SGPRRegisterRegAlloc>>
99 SGPRRegAlloc("sgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
100              cl::desc("Register allocator to use for SGPRs"));
101 
102 static cl::opt<VGPRRegisterRegAlloc::FunctionPassCtor, false,
103                RegisterPassParser<VGPRRegisterRegAlloc>>
104 VGPRRegAlloc("vgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
105              cl::desc("Register allocator to use for VGPRs"));
106 
107 
108 static void initializeDefaultSGPRRegisterAllocatorOnce() {
109   RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
110 
111   if (!Ctor) {
112     Ctor = SGPRRegAlloc;
113     SGPRRegisterRegAlloc::setDefault(SGPRRegAlloc);
114   }
115 }
116 
117 static void initializeDefaultVGPRRegisterAllocatorOnce() {
118   RegisterRegAlloc::FunctionPassCtor Ctor = VGPRRegisterRegAlloc::getDefault();
119 
120   if (!Ctor) {
121     Ctor = VGPRRegAlloc;
122     VGPRRegisterRegAlloc::setDefault(VGPRRegAlloc);
123   }
124 }
125 
126 static FunctionPass *createBasicSGPRRegisterAllocator() {
127   return createBasicRegisterAllocator(onlyAllocateSGPRs);
128 }
129 
130 static FunctionPass *createGreedySGPRRegisterAllocator() {
131   return createGreedyRegisterAllocator(onlyAllocateSGPRs);
132 }
133 
134 static FunctionPass *createFastSGPRRegisterAllocator() {
135   return createFastRegisterAllocator(onlyAllocateSGPRs, false);
136 }
137 
138 static FunctionPass *createBasicVGPRRegisterAllocator() {
139   return createBasicRegisterAllocator(onlyAllocateVGPRs);
140 }
141 
142 static FunctionPass *createGreedyVGPRRegisterAllocator() {
143   return createGreedyRegisterAllocator(onlyAllocateVGPRs);
144 }
145 
146 static FunctionPass *createFastVGPRRegisterAllocator() {
147   return createFastRegisterAllocator(onlyAllocateVGPRs, true);
148 }
149 
150 static SGPRRegisterRegAlloc basicRegAllocSGPR(
151   "basic", "basic register allocator", createBasicSGPRRegisterAllocator);
152 static SGPRRegisterRegAlloc greedyRegAllocSGPR(
153   "greedy", "greedy register allocator", createGreedySGPRRegisterAllocator);
154 
155 static SGPRRegisterRegAlloc fastRegAllocSGPR(
156   "fast", "fast register allocator", createFastSGPRRegisterAllocator);
157 
158 
159 static VGPRRegisterRegAlloc basicRegAllocVGPR(
160   "basic", "basic register allocator", createBasicVGPRRegisterAllocator);
161 static VGPRRegisterRegAlloc greedyRegAllocVGPR(
162   "greedy", "greedy register allocator", createGreedyVGPRRegisterAllocator);
163 
164 static VGPRRegisterRegAlloc fastRegAllocVGPR(
165   "fast", "fast register allocator", createFastVGPRRegisterAllocator);
166 }
167 
168 static cl::opt<bool> EnableSROA(
169   "amdgpu-sroa",
170   cl::desc("Run SROA after promote alloca pass"),
171   cl::ReallyHidden,
172   cl::init(true));
173 
174 static cl::opt<bool>
175 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
176                         cl::desc("Run early if-conversion"),
177                         cl::init(false));
178 
179 static cl::opt<bool>
180 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
181             cl::desc("Run pre-RA exec mask optimizations"),
182             cl::init(true));
183 
184 // Option to disable vectorizer for tests.
185 static cl::opt<bool> EnableLoadStoreVectorizer(
186   "amdgpu-load-store-vectorizer",
187   cl::desc("Enable load store vectorizer"),
188   cl::init(true),
189   cl::Hidden);
190 
191 // Option to control global loads scalarization
192 static cl::opt<bool> ScalarizeGlobal(
193   "amdgpu-scalarize-global-loads",
194   cl::desc("Enable global load scalarization"),
195   cl::init(true),
196   cl::Hidden);
197 
198 // Option to run internalize pass.
199 static cl::opt<bool> InternalizeSymbols(
200   "amdgpu-internalize-symbols",
201   cl::desc("Enable elimination of non-kernel functions and unused globals"),
202   cl::init(false),
203   cl::Hidden);
204 
205 // Option to inline all early.
206 static cl::opt<bool> EarlyInlineAll(
207   "amdgpu-early-inline-all",
208   cl::desc("Inline all functions early"),
209   cl::init(false),
210   cl::Hidden);
211 
212 static cl::opt<bool> EnableSDWAPeephole(
213   "amdgpu-sdwa-peephole",
214   cl::desc("Enable SDWA peepholer"),
215   cl::init(true));
216 
217 static cl::opt<bool> EnableDPPCombine(
218   "amdgpu-dpp-combine",
219   cl::desc("Enable DPP combiner"),
220   cl::init(true));
221 
222 // Enable address space based alias analysis
223 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
224   cl::desc("Enable AMDGPU Alias Analysis"),
225   cl::init(true));
226 
227 // Option to run late CFG structurizer
228 static cl::opt<bool, true> LateCFGStructurize(
229   "amdgpu-late-structurize",
230   cl::desc("Enable late CFG structurization"),
231   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
232   cl::Hidden);
233 
234 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
235   "amdgpu-fixed-function-abi",
236   cl::desc("Enable all implicit function arguments"),
237   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
238   cl::init(false),
239   cl::Hidden);
240 
241 // Enable lib calls simplifications
242 static cl::opt<bool> EnableLibCallSimplify(
243   "amdgpu-simplify-libcall",
244   cl::desc("Enable amdgpu library simplifications"),
245   cl::init(true),
246   cl::Hidden);
247 
248 static cl::opt<bool> EnableLowerKernelArguments(
249   "amdgpu-ir-lower-kernel-arguments",
250   cl::desc("Lower kernel argument loads in IR pass"),
251   cl::init(true),
252   cl::Hidden);
253 
254 static cl::opt<bool> EnableRegReassign(
255   "amdgpu-reassign-regs",
256   cl::desc("Enable register reassign optimizations on gfx10+"),
257   cl::init(true),
258   cl::Hidden);
259 
260 static cl::opt<bool> OptVGPRLiveRange(
261     "amdgpu-opt-vgpr-liverange",
262     cl::desc("Enable VGPR liverange optimizations for if-else structure"),
263     cl::init(true), cl::Hidden);
264 
265 // Enable atomic optimization
266 static cl::opt<bool> EnableAtomicOptimizations(
267   "amdgpu-atomic-optimizations",
268   cl::desc("Enable atomic optimizations"),
269   cl::init(false),
270   cl::Hidden);
271 
272 // Enable Mode register optimization
273 static cl::opt<bool> EnableSIModeRegisterPass(
274   "amdgpu-mode-register",
275   cl::desc("Enable mode register pass"),
276   cl::init(true),
277   cl::Hidden);
278 
279 // Option is used in lit tests to prevent deadcoding of patterns inspected.
280 static cl::opt<bool>
281 EnableDCEInRA("amdgpu-dce-in-ra",
282     cl::init(true), cl::Hidden,
283     cl::desc("Enable machine DCE inside regalloc"));
284 
285 static cl::opt<bool> EnableScalarIRPasses(
286   "amdgpu-scalar-ir-passes",
287   cl::desc("Enable scalar IR passes"),
288   cl::init(true),
289   cl::Hidden);
290 
291 static cl::opt<bool> EnableStructurizerWorkarounds(
292     "amdgpu-enable-structurizer-workarounds",
293     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
294     cl::Hidden);
295 
296 static cl::opt<bool> EnableLDSReplaceWithPointer(
297     "amdgpu-enable-lds-replace-with-pointer",
298     cl::desc("Enable LDS replace with pointer pass"), cl::init(false),
299     cl::Hidden);
300 
301 static cl::opt<bool, true> EnableLowerModuleLDS(
302     "amdgpu-enable-lower-module-lds", cl::desc("Enable lower module lds pass"),
303     cl::location(AMDGPUTargetMachine::EnableLowerModuleLDS), cl::init(true),
304     cl::Hidden);
305 
306 static cl::opt<bool> EnablePreRAOptimizations(
307     "amdgpu-enable-pre-ra-optimizations",
308     cl::desc("Enable Pre-RA optimizations pass"), cl::init(true),
309     cl::Hidden);
310 
311 static cl::opt<bool> EnablePromoteKernelArguments(
312     "amdgpu-enable-promote-kernel-arguments",
313     cl::desc("Enable promotion of flat kernel pointer arguments to global"),
314     cl::Hidden, cl::init(true));
315 
316 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
317   // Register the target
318   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
319   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
320 
321   PassRegistry *PR = PassRegistry::getPassRegistry();
322   initializeR600ClauseMergePassPass(*PR);
323   initializeR600ControlFlowFinalizerPass(*PR);
324   initializeR600PacketizerPass(*PR);
325   initializeR600ExpandSpecialInstrsPassPass(*PR);
326   initializeR600VectorRegMergerPass(*PR);
327   initializeGlobalISel(*PR);
328   initializeAMDGPUDAGToDAGISelPass(*PR);
329   initializeGCNDPPCombinePass(*PR);
330   initializeSILowerI1CopiesPass(*PR);
331   initializeSILowerSGPRSpillsPass(*PR);
332   initializeSIFixSGPRCopiesPass(*PR);
333   initializeSIFixVGPRCopiesPass(*PR);
334   initializeSIFoldOperandsPass(*PR);
335   initializeSIPeepholeSDWAPass(*PR);
336   initializeSIShrinkInstructionsPass(*PR);
337   initializeSIOptimizeExecMaskingPreRAPass(*PR);
338   initializeSIOptimizeVGPRLiveRangePass(*PR);
339   initializeSILoadStoreOptimizerPass(*PR);
340   initializeAMDGPUFixFunctionBitcastsPass(*PR);
341   initializeAMDGPUCtorDtorLoweringPass(*PR);
342   initializeAMDGPUAlwaysInlinePass(*PR);
343   initializeAMDGPUAttributorPass(*PR);
344   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
345   initializeAMDGPUAnnotateUniformValuesPass(*PR);
346   initializeAMDGPUArgumentUsageInfoPass(*PR);
347   initializeAMDGPUAtomicOptimizerPass(*PR);
348   initializeAMDGPULowerKernelArgumentsPass(*PR);
349   initializeAMDGPUPromoteKernelArgumentsPass(*PR);
350   initializeAMDGPULowerKernelAttributesPass(*PR);
351   initializeAMDGPULowerIntrinsicsPass(*PR);
352   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
353   initializeAMDGPUPostLegalizerCombinerPass(*PR);
354   initializeAMDGPUPreLegalizerCombinerPass(*PR);
355   initializeAMDGPURegBankCombinerPass(*PR);
356   initializeAMDGPUPromoteAllocaPass(*PR);
357   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
358   initializeAMDGPUCodeGenPreparePass(*PR);
359   initializeAMDGPULateCodeGenPreparePass(*PR);
360   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
361   initializeAMDGPUPropagateAttributesLatePass(*PR);
362   initializeAMDGPUReplaceLDSUseWithPointerPass(*PR);
363   initializeAMDGPULowerModuleLDSPass(*PR);
364   initializeAMDGPURewriteOutArgumentsPass(*PR);
365   initializeAMDGPUUnifyMetadataPass(*PR);
366   initializeSIAnnotateControlFlowPass(*PR);
367   initializeSIInsertHardClausesPass(*PR);
368   initializeSIInsertWaitcntsPass(*PR);
369   initializeSIModeRegisterPass(*PR);
370   initializeSIWholeQuadModePass(*PR);
371   initializeSILowerControlFlowPass(*PR);
372   initializeSIPreEmitPeepholePass(*PR);
373   initializeSILateBranchLoweringPass(*PR);
374   initializeSIMemoryLegalizerPass(*PR);
375   initializeSIOptimizeExecMaskingPass(*PR);
376   initializeSIPreAllocateWWMRegsPass(*PR);
377   initializeSIFormMemoryClausesPass(*PR);
378   initializeSIPostRABundlerPass(*PR);
379   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
380   initializeAMDGPUAAWrapperPassPass(*PR);
381   initializeAMDGPUExternalAAWrapperPass(*PR);
382   initializeAMDGPUUseNativeCallsPass(*PR);
383   initializeAMDGPUSimplifyLibCallsPass(*PR);
384   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
385   initializeAMDGPUResourceUsageAnalysisPass(*PR);
386   initializeGCNNSAReassignPass(*PR);
387   initializeGCNPreRAOptimizationsPass(*PR);
388 }
389 
390 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
391   return std::make_unique<AMDGPUTargetObjectFile>();
392 }
393 
394 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
395   return new SIScheduleDAGMI(C);
396 }
397 
398 static ScheduleDAGInstrs *
399 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
400   ScheduleDAGMILive *DAG =
401     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
402   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
403   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
404   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
405   return DAG;
406 }
407 
408 static ScheduleDAGInstrs *
409 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
410   auto DAG = new GCNIterativeScheduler(C,
411     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
412   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
413   return DAG;
414 }
415 
416 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
417   return new GCNIterativeScheduler(C,
418     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
419 }
420 
421 static ScheduleDAGInstrs *
422 createIterativeILPMachineScheduler(MachineSchedContext *C) {
423   auto DAG = new GCNIterativeScheduler(C,
424     GCNIterativeScheduler::SCHEDULE_ILP);
425   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
426   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
427   return DAG;
428 }
429 
430 static MachineSchedRegistry
431 SISchedRegistry("si", "Run SI's custom scheduler",
432                 createSIMachineScheduler);
433 
434 static MachineSchedRegistry
435 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
436                              "Run GCN scheduler to maximize occupancy",
437                              createGCNMaxOccupancyMachineScheduler);
438 
439 static MachineSchedRegistry
440 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
441   "Run GCN scheduler to maximize occupancy (experimental)",
442   createIterativeGCNMaxOccupancyMachineScheduler);
443 
444 static MachineSchedRegistry
445 GCNMinRegSchedRegistry("gcn-minreg",
446   "Run GCN iterative scheduler for minimal register usage (experimental)",
447   createMinRegScheduler);
448 
449 static MachineSchedRegistry
450 GCNILPSchedRegistry("gcn-ilp",
451   "Run GCN iterative scheduler for ILP scheduling (experimental)",
452   createIterativeILPMachineScheduler);
453 
454 static StringRef computeDataLayout(const Triple &TT) {
455   if (TT.getArch() == Triple::r600) {
456     // 32-bit pointers.
457     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
458            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
459   }
460 
461   // 32-bit private, local, and region pointers. 64-bit global, constant and
462   // flat, non-integral buffer fat pointers.
463   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
464          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
465          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
466          "-ni:7";
467 }
468 
469 LLVM_READNONE
470 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
471   if (!GPU.empty())
472     return GPU;
473 
474   // Need to default to a target with flat support for HSA.
475   if (TT.getArch() == Triple::amdgcn)
476     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
477 
478   return "r600";
479 }
480 
481 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
482   // The AMDGPU toolchain only supports generating shared objects, so we
483   // must always use PIC.
484   return Reloc::PIC_;
485 }
486 
487 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
488                                          StringRef CPU, StringRef FS,
489                                          TargetOptions Options,
490                                          Optional<Reloc::Model> RM,
491                                          Optional<CodeModel::Model> CM,
492                                          CodeGenOpt::Level OptLevel)
493     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
494                         FS, Options, getEffectiveRelocModel(RM),
495                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
496       TLOF(createTLOF(getTargetTriple())) {
497   initAsmInfo();
498   if (TT.getArch() == Triple::amdgcn) {
499     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
500       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
501     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
502       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
503   }
504 }
505 
506 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
507 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
508 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
509 bool AMDGPUTargetMachine::EnableLowerModuleLDS = true;
510 
511 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
512 
513 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
514   Attribute GPUAttr = F.getFnAttribute("target-cpu");
515   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
516 }
517 
518 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
519   Attribute FSAttr = F.getFnAttribute("target-features");
520 
521   return FSAttr.isValid() ? FSAttr.getValueAsString()
522                           : getTargetFeatureString();
523 }
524 
525 /// Predicate for Internalize pass.
526 static bool mustPreserveGV(const GlobalValue &GV) {
527   if (const Function *F = dyn_cast<Function>(&GV))
528     return F->isDeclaration() || F->getName().startswith("__asan_") ||
529            F->getName().startswith("__sanitizer_") ||
530            AMDGPU::isEntryFunctionCC(F->getCallingConv());
531 
532   GV.removeDeadConstantUsers();
533   return !GV.use_empty();
534 }
535 
536 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
537   Builder.DivergentTarget = true;
538 
539   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
540   bool Internalize = InternalizeSymbols;
541   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
542   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
543   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
544   bool PromoteKernelArguments =
545       EnablePromoteKernelArguments && getOptLevel() > CodeGenOpt::Less;
546 
547   if (EnableFunctionCalls) {
548     delete Builder.Inliner;
549     Builder.Inliner = createFunctionInliningPass();
550   }
551 
552   Builder.addExtension(
553     PassManagerBuilder::EP_ModuleOptimizerEarly,
554     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
555                                                legacy::PassManagerBase &PM) {
556       if (AMDGPUAA) {
557         PM.add(createAMDGPUAAWrapperPass());
558         PM.add(createAMDGPUExternalAAWrapperPass());
559       }
560       PM.add(createAMDGPUUnifyMetadataPass());
561       PM.add(createAMDGPUPrintfRuntimeBinding());
562       if (Internalize)
563         PM.add(createInternalizePass(mustPreserveGV));
564       PM.add(createAMDGPUPropagateAttributesLatePass(this));
565       if (Internalize)
566         PM.add(createGlobalDCEPass());
567       if (EarlyInline)
568         PM.add(createAMDGPUAlwaysInlinePass(false));
569   });
570 
571   Builder.addExtension(
572     PassManagerBuilder::EP_EarlyAsPossible,
573     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
574                                       legacy::PassManagerBase &PM) {
575       if (AMDGPUAA) {
576         PM.add(createAMDGPUAAWrapperPass());
577         PM.add(createAMDGPUExternalAAWrapperPass());
578       }
579       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
580       PM.add(llvm::createAMDGPUUseNativeCallsPass());
581       if (LibCallSimplify)
582         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
583   });
584 
585   Builder.addExtension(
586     PassManagerBuilder::EP_CGSCCOptimizerLate,
587     [EnableOpt, PromoteKernelArguments](const PassManagerBuilder &,
588                                         legacy::PassManagerBase &PM) {
589       // Add promote kernel arguments pass to the opt pipeline right before
590       // infer address spaces which is needed to do actual address space
591       // rewriting.
592       if (PromoteKernelArguments)
593         PM.add(createAMDGPUPromoteKernelArgumentsPass());
594 
595       // Add infer address spaces pass to the opt pipeline after inlining
596       // but before SROA to increase SROA opportunities.
597       PM.add(createInferAddressSpacesPass());
598 
599       // This should run after inlining to have any chance of doing anything,
600       // and before other cleanup optimizations.
601       PM.add(createAMDGPULowerKernelAttributesPass());
602 
603       // Promote alloca to vector before SROA and loop unroll. If we manage
604       // to eliminate allocas before unroll we may choose to unroll less.
605       if (EnableOpt)
606         PM.add(createAMDGPUPromoteAllocaToVector());
607   });
608 }
609 
610 void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
611   AAM.registerFunctionAnalysis<AMDGPUAA>();
612 }
613 
614 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
615   PB.registerPipelineParsingCallback(
616       [this](StringRef PassName, ModulePassManager &PM,
617              ArrayRef<PassBuilder::PipelineElement>) {
618         if (PassName == "amdgpu-propagate-attributes-late") {
619           PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
620           return true;
621         }
622         if (PassName == "amdgpu-unify-metadata") {
623           PM.addPass(AMDGPUUnifyMetadataPass());
624           return true;
625         }
626         if (PassName == "amdgpu-printf-runtime-binding") {
627           PM.addPass(AMDGPUPrintfRuntimeBindingPass());
628           return true;
629         }
630         if (PassName == "amdgpu-always-inline") {
631           PM.addPass(AMDGPUAlwaysInlinePass());
632           return true;
633         }
634         if (PassName == "amdgpu-replace-lds-use-with-pointer") {
635           PM.addPass(AMDGPUReplaceLDSUseWithPointerPass());
636           return true;
637         }
638         if (PassName == "amdgpu-lower-module-lds") {
639           PM.addPass(AMDGPULowerModuleLDSPass());
640           return true;
641         }
642         return false;
643       });
644   PB.registerPipelineParsingCallback(
645       [this](StringRef PassName, FunctionPassManager &PM,
646              ArrayRef<PassBuilder::PipelineElement>) {
647         if (PassName == "amdgpu-simplifylib") {
648           PM.addPass(AMDGPUSimplifyLibCallsPass(*this));
649           return true;
650         }
651         if (PassName == "amdgpu-usenative") {
652           PM.addPass(AMDGPUUseNativeCallsPass());
653           return true;
654         }
655         if (PassName == "amdgpu-promote-alloca") {
656           PM.addPass(AMDGPUPromoteAllocaPass(*this));
657           return true;
658         }
659         if (PassName == "amdgpu-promote-alloca-to-vector") {
660           PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
661           return true;
662         }
663         if (PassName == "amdgpu-lower-kernel-attributes") {
664           PM.addPass(AMDGPULowerKernelAttributesPass());
665           return true;
666         }
667         if (PassName == "amdgpu-propagate-attributes-early") {
668           PM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
669           return true;
670         }
671         if (PassName == "amdgpu-promote-kernel-arguments") {
672           PM.addPass(AMDGPUPromoteKernelArgumentsPass());
673           return true;
674         }
675         return false;
676       });
677 
678   PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
679     FAM.registerPass([&] { return AMDGPUAA(); });
680   });
681 
682   PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
683     if (AAName == "amdgpu-aa") {
684       AAM.registerFunctionAnalysis<AMDGPUAA>();
685       return true;
686     }
687     return false;
688   });
689 
690   PB.registerPipelineStartEPCallback(
691       [this](ModulePassManager &PM, OptimizationLevel Level) {
692         FunctionPassManager FPM;
693         FPM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
694         FPM.addPass(AMDGPUUseNativeCallsPass());
695         if (EnableLibCallSimplify && Level != OptimizationLevel::O0)
696           FPM.addPass(AMDGPUSimplifyLibCallsPass(*this));
697         PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
698       });
699 
700   PB.registerPipelineEarlySimplificationEPCallback(
701       [this](ModulePassManager &PM, OptimizationLevel Level) {
702         if (Level == OptimizationLevel::O0)
703           return;
704 
705         PM.addPass(AMDGPUUnifyMetadataPass());
706         PM.addPass(AMDGPUPrintfRuntimeBindingPass());
707 
708         if (InternalizeSymbols) {
709           PM.addPass(InternalizePass(mustPreserveGV));
710         }
711         PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
712         if (InternalizeSymbols) {
713           PM.addPass(GlobalDCEPass());
714         }
715         if (EarlyInlineAll && !EnableFunctionCalls)
716           PM.addPass(AMDGPUAlwaysInlinePass());
717       });
718 
719   PB.registerCGSCCOptimizerLateEPCallback(
720       [this](CGSCCPassManager &PM, OptimizationLevel Level) {
721         if (Level == OptimizationLevel::O0)
722           return;
723 
724         FunctionPassManager FPM;
725 
726         // Add promote kernel arguments pass to the opt pipeline right before
727         // infer address spaces which is needed to do actual address space
728         // rewriting.
729         if (Level.getSpeedupLevel() > OptimizationLevel::O1.getSpeedupLevel() &&
730             EnablePromoteKernelArguments)
731           FPM.addPass(AMDGPUPromoteKernelArgumentsPass());
732 
733         // Add infer address spaces pass to the opt pipeline after inlining
734         // but before SROA to increase SROA opportunities.
735         FPM.addPass(InferAddressSpacesPass());
736 
737         // This should run after inlining to have any chance of doing
738         // anything, and before other cleanup optimizations.
739         FPM.addPass(AMDGPULowerKernelAttributesPass());
740 
741         if (Level != OptimizationLevel::O0) {
742           // Promote alloca to vector before SROA and loop unroll. If we
743           // manage to eliminate allocas before unroll we may choose to unroll
744           // less.
745           FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
746         }
747 
748         PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));
749       });
750 }
751 
752 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
753   return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
754           AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
755           AddrSpace == AMDGPUAS::REGION_ADDRESS)
756              ? -1
757              : 0;
758 }
759 
760 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
761                                               unsigned DestAS) const {
762   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
763          AMDGPU::isFlatGlobalAddrSpace(DestAS);
764 }
765 
766 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
767   const auto *LD = dyn_cast<LoadInst>(V);
768   if (!LD)
769     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
770 
771   // It must be a generic pointer loaded.
772   assert(V->getType()->isPointerTy() &&
773          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
774 
775   const auto *Ptr = LD->getPointerOperand();
776   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
777     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
778   // For a generic pointer loaded from the constant memory, it could be assumed
779   // as a global pointer since the constant memory is only populated on the
780   // host side. As implied by the offload programming model, only global
781   // pointers could be referenced on the host side.
782   return AMDGPUAS::GLOBAL_ADDRESS;
783 }
784 
785 std::pair<const Value *, unsigned>
786 AMDGPUTargetMachine::getPredicatedAddrSpace(const Value *V) const {
787   if (auto *II = dyn_cast<IntrinsicInst>(V)) {
788     switch (II->getIntrinsicID()) {
789     case Intrinsic::amdgcn_is_shared:
790       return std::make_pair(II->getArgOperand(0), AMDGPUAS::LOCAL_ADDRESS);
791     case Intrinsic::amdgcn_is_private:
792       return std::make_pair(II->getArgOperand(0), AMDGPUAS::PRIVATE_ADDRESS);
793     default:
794       break;
795     }
796     return std::make_pair(nullptr, -1);
797   }
798   // Check the global pointer predication based on
799   // (!is_share(p) && !is_private(p)). Note that logic 'and' is commutative and
800   // the order of 'is_shared' and 'is_private' is not significant.
801   Value *Ptr;
802   if (match(
803           const_cast<Value *>(V),
804           m_c_And(m_Not(m_Intrinsic<Intrinsic::amdgcn_is_shared>(m_Value(Ptr))),
805                   m_Not(m_Intrinsic<Intrinsic::amdgcn_is_private>(
806                       m_Deferred(Ptr))))))
807     return std::make_pair(Ptr, AMDGPUAS::GLOBAL_ADDRESS);
808 
809   return std::make_pair(nullptr, -1);
810 }
811 
812 //===----------------------------------------------------------------------===//
813 // GCN Target Machine (SI+)
814 //===----------------------------------------------------------------------===//
815 
816 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
817                                    StringRef CPU, StringRef FS,
818                                    TargetOptions Options,
819                                    Optional<Reloc::Model> RM,
820                                    Optional<CodeModel::Model> CM,
821                                    CodeGenOpt::Level OL, bool JIT)
822     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
823 
824 const TargetSubtargetInfo *
825 GCNTargetMachine::getSubtargetImpl(const Function &F) const {
826   StringRef GPU = getGPUName(F);
827   StringRef FS = getFeatureString(F);
828 
829   SmallString<128> SubtargetKey(GPU);
830   SubtargetKey.append(FS);
831 
832   auto &I = SubtargetMap[SubtargetKey];
833   if (!I) {
834     // This needs to be done before we create a new subtarget since any
835     // creation will depend on the TM and the code generation flags on the
836     // function that reside in TargetOptions.
837     resetTargetOptions(F);
838     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
839   }
840 
841   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
842 
843   return I.get();
844 }
845 
846 TargetTransformInfo
847 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
848   return TargetTransformInfo(GCNTTIImpl(this, F));
849 }
850 
851 //===----------------------------------------------------------------------===//
852 // AMDGPU Pass Setup
853 //===----------------------------------------------------------------------===//
854 
855 std::unique_ptr<CSEConfigBase> llvm::AMDGPUPassConfig::getCSEConfig() const {
856   return getStandardCSEConfigForOpt(TM->getOptLevel());
857 }
858 
859 namespace {
860 
861 class GCNPassConfig final : public AMDGPUPassConfig {
862 public:
863   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
864     : AMDGPUPassConfig(TM, PM) {
865     // It is necessary to know the register usage of the entire call graph.  We
866     // allow calls without EnableAMDGPUFunctionCalls if they are marked
867     // noinline, so this is always required.
868     setRequiresCodeGenSCCOrder(true);
869     substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
870   }
871 
872   GCNTargetMachine &getGCNTargetMachine() const {
873     return getTM<GCNTargetMachine>();
874   }
875 
876   ScheduleDAGInstrs *
877   createMachineScheduler(MachineSchedContext *C) const override;
878 
879   ScheduleDAGInstrs *
880   createPostMachineScheduler(MachineSchedContext *C) const override {
881     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
882     const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
883     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
884     DAG->addMutation(ST.createFillMFMAShadowMutation(DAG->TII));
885     return DAG;
886   }
887 
888   bool addPreISel() override;
889   void addMachineSSAOptimization() override;
890   bool addILPOpts() override;
891   bool addInstSelector() override;
892   bool addIRTranslator() override;
893   void addPreLegalizeMachineIR() override;
894   bool addLegalizeMachineIR() override;
895   void addPreRegBankSelect() override;
896   bool addRegBankSelect() override;
897   void addPreGlobalInstructionSelect() override;
898   bool addGlobalInstructionSelect() override;
899   void addFastRegAlloc() override;
900   void addOptimizedRegAlloc() override;
901 
902   FunctionPass *createSGPRAllocPass(bool Optimized);
903   FunctionPass *createVGPRAllocPass(bool Optimized);
904   FunctionPass *createRegAllocPass(bool Optimized) override;
905 
906   bool addRegAssignAndRewriteFast() override;
907   bool addRegAssignAndRewriteOptimized() override;
908 
909   void addPreRegAlloc() override;
910   bool addPreRewrite() override;
911   void addPostRegAlloc() override;
912   void addPreSched2() override;
913   void addPreEmitPass() override;
914 };
915 
916 } // end anonymous namespace
917 
918 AMDGPUPassConfig::AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
919     : TargetPassConfig(TM, PM) {
920   // Exceptions and StackMaps are not supported, so these passes will never do
921   // anything.
922   disablePass(&StackMapLivenessID);
923   disablePass(&FuncletLayoutID);
924   // Garbage collection is not supported.
925   disablePass(&GCLoweringID);
926   disablePass(&ShadowStackGCLoweringID);
927 }
928 
929 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
930   if (getOptLevel() == CodeGenOpt::Aggressive)
931     addPass(createGVNPass());
932   else
933     addPass(createEarlyCSEPass());
934 }
935 
936 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
937   addPass(createLICMPass());
938   addPass(createSeparateConstOffsetFromGEPPass());
939   addPass(createSpeculativeExecutionPass());
940   // ReassociateGEPs exposes more opportunities for SLSR. See
941   // the example in reassociate-geps-and-slsr.ll.
942   addPass(createStraightLineStrengthReducePass());
943   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
944   // EarlyCSE can reuse.
945   addEarlyCSEOrGVNPass();
946   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
947   addPass(createNaryReassociatePass());
948   // NaryReassociate on GEPs creates redundant common expressions, so run
949   // EarlyCSE after it.
950   addPass(createEarlyCSEPass());
951 }
952 
953 void AMDGPUPassConfig::addIRPasses() {
954   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
955 
956   // There is no reason to run these.
957   disablePass(&StackMapLivenessID);
958   disablePass(&FuncletLayoutID);
959   disablePass(&PatchableFunctionID);
960 
961   addPass(createAMDGPUPrintfRuntimeBinding());
962   addPass(createAMDGPUCtorDtorLoweringPass());
963 
964   // This must occur before inlining, as the inliner will not look through
965   // bitcast calls.
966   addPass(createAMDGPUFixFunctionBitcastsPass());
967 
968   // A call to propagate attributes pass in the backend in case opt was not run.
969   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
970 
971   addPass(createAMDGPULowerIntrinsicsPass());
972 
973   // Function calls are not supported, so make sure we inline everything.
974   addPass(createAMDGPUAlwaysInlinePass());
975   addPass(createAlwaysInlinerLegacyPass());
976   // We need to add the barrier noop pass, otherwise adding the function
977   // inlining pass will cause all of the PassConfigs passes to be run
978   // one function at a time, which means if we have a nodule with two
979   // functions, then we will generate code for the first function
980   // without ever running any passes on the second.
981   addPass(createBarrierNoopPass());
982 
983   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
984   if (TM.getTargetTriple().getArch() == Triple::r600)
985     addPass(createR600OpenCLImageTypeLoweringPass());
986 
987   // Replace OpenCL enqueued block function pointers with global variables.
988   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
989 
990   // Can increase LDS used by kernel so runs before PromoteAlloca
991   if (EnableLowerModuleLDS) {
992     // The pass "amdgpu-replace-lds-use-with-pointer" need to be run before the
993     // pass "amdgpu-lower-module-lds", and also it required to be run only if
994     // "amdgpu-lower-module-lds" pass is enabled.
995     if (EnableLDSReplaceWithPointer)
996       addPass(createAMDGPUReplaceLDSUseWithPointerPass());
997 
998     addPass(createAMDGPULowerModuleLDSPass());
999   }
1000 
1001   if (TM.getOptLevel() > CodeGenOpt::None)
1002     addPass(createInferAddressSpacesPass());
1003 
1004   addPass(createAtomicExpandPass());
1005 
1006   if (TM.getOptLevel() > CodeGenOpt::None) {
1007     addPass(createAMDGPUPromoteAlloca());
1008 
1009     if (EnableSROA)
1010       addPass(createSROAPass());
1011     if (isPassEnabled(EnableScalarIRPasses))
1012       addStraightLineScalarOptimizationPasses();
1013 
1014     if (EnableAMDGPUAliasAnalysis) {
1015       addPass(createAMDGPUAAWrapperPass());
1016       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
1017                                              AAResults &AAR) {
1018         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
1019           AAR.addAAResult(WrapperPass->getResult());
1020         }));
1021     }
1022 
1023     if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
1024       // TODO: May want to move later or split into an early and late one.
1025       addPass(createAMDGPUCodeGenPreparePass());
1026     }
1027   }
1028 
1029   TargetPassConfig::addIRPasses();
1030 
1031   // EarlyCSE is not always strong enough to clean up what LSR produces. For
1032   // example, GVN can combine
1033   //
1034   //   %0 = add %a, %b
1035   //   %1 = add %b, %a
1036   //
1037   // and
1038   //
1039   //   %0 = shl nsw %a, 2
1040   //   %1 = shl %a, 2
1041   //
1042   // but EarlyCSE can do neither of them.
1043   if (isPassEnabled(EnableScalarIRPasses))
1044     addEarlyCSEOrGVNPass();
1045 }
1046 
1047 void AMDGPUPassConfig::addCodeGenPrepare() {
1048   if (TM->getTargetTriple().getArch() == Triple::amdgcn) {
1049     addPass(createAMDGPUAttributorPass());
1050 
1051     // FIXME: This pass adds 2 hacky attributes that can be replaced with an
1052     // analysis, and should be removed.
1053     addPass(createAMDGPUAnnotateKernelFeaturesPass());
1054   }
1055 
1056   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
1057       EnableLowerKernelArguments)
1058     addPass(createAMDGPULowerKernelArgumentsPass());
1059 
1060   TargetPassConfig::addCodeGenPrepare();
1061 
1062   if (isPassEnabled(EnableLoadStoreVectorizer))
1063     addPass(createLoadStoreVectorizerPass());
1064 
1065   // LowerSwitch pass may introduce unreachable blocks that can
1066   // cause unexpected behavior for subsequent passes. Placing it
1067   // here seems better that these blocks would get cleaned up by
1068   // UnreachableBlockElim inserted next in the pass flow.
1069   addPass(createLowerSwitchPass());
1070 }
1071 
1072 bool AMDGPUPassConfig::addPreISel() {
1073   if (TM->getOptLevel() > CodeGenOpt::None)
1074     addPass(createFlattenCFGPass());
1075   return false;
1076 }
1077 
1078 bool AMDGPUPassConfig::addInstSelector() {
1079   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
1080   return false;
1081 }
1082 
1083 bool AMDGPUPassConfig::addGCPasses() {
1084   // Do nothing. GC is not supported.
1085   return false;
1086 }
1087 
1088 llvm::ScheduleDAGInstrs *
1089 AMDGPUPassConfig::createMachineScheduler(MachineSchedContext *C) const {
1090   ScheduleDAGMILive *DAG = createGenericSchedLive(C);
1091   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1092   return DAG;
1093 }
1094 
1095 //===----------------------------------------------------------------------===//
1096 // GCN Pass Setup
1097 //===----------------------------------------------------------------------===//
1098 
1099 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1100   MachineSchedContext *C) const {
1101   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1102   if (ST.enableSIScheduler())
1103     return createSIMachineScheduler(C);
1104   return createGCNMaxOccupancyMachineScheduler(C);
1105 }
1106 
1107 bool GCNPassConfig::addPreISel() {
1108   AMDGPUPassConfig::addPreISel();
1109 
1110   if (TM->getOptLevel() > CodeGenOpt::None)
1111     addPass(createAMDGPULateCodeGenPreparePass());
1112 
1113   if (isPassEnabled(EnableAtomicOptimizations, CodeGenOpt::Less)) {
1114     addPass(createAMDGPUAtomicOptimizerPass());
1115   }
1116 
1117   if (TM->getOptLevel() > CodeGenOpt::None)
1118     addPass(createSinkingPass());
1119 
1120   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1121   // regions formed by them.
1122   addPass(&AMDGPUUnifyDivergentExitNodesID);
1123   if (!LateCFGStructurize) {
1124     if (EnableStructurizerWorkarounds) {
1125       addPass(createFixIrreduciblePass());
1126       addPass(createUnifyLoopExitsPass());
1127     }
1128     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1129   }
1130   addPass(createAMDGPUAnnotateUniformValues());
1131   if (!LateCFGStructurize) {
1132     addPass(createSIAnnotateControlFlowPass());
1133   }
1134   addPass(createLCSSAPass());
1135 
1136   if (TM->getOptLevel() > CodeGenOpt::Less)
1137     addPass(&AMDGPUPerfHintAnalysisID);
1138 
1139   return false;
1140 }
1141 
1142 void GCNPassConfig::addMachineSSAOptimization() {
1143   TargetPassConfig::addMachineSSAOptimization();
1144 
1145   // We want to fold operands after PeepholeOptimizer has run (or as part of
1146   // it), because it will eliminate extra copies making it easier to fold the
1147   // real source operand. We want to eliminate dead instructions after, so that
1148   // we see fewer uses of the copies. We then need to clean up the dead
1149   // instructions leftover after the operands are folded as well.
1150   //
1151   // XXX - Can we get away without running DeadMachineInstructionElim again?
1152   addPass(&SIFoldOperandsID);
1153   if (EnableDPPCombine)
1154     addPass(&GCNDPPCombineID);
1155   addPass(&SILoadStoreOptimizerID);
1156   if (isPassEnabled(EnableSDWAPeephole)) {
1157     addPass(&SIPeepholeSDWAID);
1158     addPass(&EarlyMachineLICMID);
1159     addPass(&MachineCSEID);
1160     addPass(&SIFoldOperandsID);
1161   }
1162   addPass(&DeadMachineInstructionElimID);
1163   addPass(createSIShrinkInstructionsPass());
1164 }
1165 
1166 bool GCNPassConfig::addILPOpts() {
1167   if (EnableEarlyIfConversion)
1168     addPass(&EarlyIfConverterID);
1169 
1170   TargetPassConfig::addILPOpts();
1171   return false;
1172 }
1173 
1174 bool GCNPassConfig::addInstSelector() {
1175   AMDGPUPassConfig::addInstSelector();
1176   addPass(&SIFixSGPRCopiesID);
1177   addPass(createSILowerI1CopiesPass());
1178   return false;
1179 }
1180 
1181 bool GCNPassConfig::addIRTranslator() {
1182   addPass(new IRTranslator(getOptLevel()));
1183   return false;
1184 }
1185 
1186 void GCNPassConfig::addPreLegalizeMachineIR() {
1187   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1188   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1189   addPass(new Localizer());
1190 }
1191 
1192 bool GCNPassConfig::addLegalizeMachineIR() {
1193   addPass(new Legalizer());
1194   return false;
1195 }
1196 
1197 void GCNPassConfig::addPreRegBankSelect() {
1198   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1199   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1200 }
1201 
1202 bool GCNPassConfig::addRegBankSelect() {
1203   addPass(new RegBankSelect());
1204   return false;
1205 }
1206 
1207 void GCNPassConfig::addPreGlobalInstructionSelect() {
1208   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1209   addPass(createAMDGPURegBankCombiner(IsOptNone));
1210 }
1211 
1212 bool GCNPassConfig::addGlobalInstructionSelect() {
1213   addPass(new InstructionSelect(getOptLevel()));
1214   return false;
1215 }
1216 
1217 void GCNPassConfig::addPreRegAlloc() {
1218   if (LateCFGStructurize) {
1219     addPass(createAMDGPUMachineCFGStructurizerPass());
1220   }
1221 }
1222 
1223 void GCNPassConfig::addFastRegAlloc() {
1224   // FIXME: We have to disable the verifier here because of PHIElimination +
1225   // TwoAddressInstructions disabling it.
1226 
1227   // This must be run immediately after phi elimination and before
1228   // TwoAddressInstructions, otherwise the processing of the tied operand of
1229   // SI_ELSE will introduce a copy of the tied operand source after the else.
1230   insertPass(&PHIEliminationID, &SILowerControlFlowID);
1231 
1232   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1233   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1234 
1235   TargetPassConfig::addFastRegAlloc();
1236 }
1237 
1238 void GCNPassConfig::addOptimizedRegAlloc() {
1239   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1240   // instructions that cause scheduling barriers.
1241   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1242   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1243 
1244   if (OptExecMaskPreRA)
1245     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1246 
1247   if (isPassEnabled(EnablePreRAOptimizations))
1248     insertPass(&RenameIndependentSubregsID, &GCNPreRAOptimizationsID);
1249 
1250   // This is not an essential optimization and it has a noticeable impact on
1251   // compilation time, so we only enable it from O2.
1252   if (TM->getOptLevel() > CodeGenOpt::Less)
1253     insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1254 
1255   // FIXME: when an instruction has a Killed operand, and the instruction is
1256   // inside a bundle, seems only the BUNDLE instruction appears as the Kills of
1257   // the register in LiveVariables, this would trigger a failure in verifier,
1258   // we should fix it and enable the verifier.
1259   if (OptVGPRLiveRange)
1260     insertPass(&LiveVariablesID, &SIOptimizeVGPRLiveRangeID);
1261   // This must be run immediately after phi elimination and before
1262   // TwoAddressInstructions, otherwise the processing of the tied operand of
1263   // SI_ELSE will introduce a copy of the tied operand source after the else.
1264   insertPass(&PHIEliminationID, &SILowerControlFlowID);
1265 
1266   if (EnableDCEInRA)
1267     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1268 
1269   TargetPassConfig::addOptimizedRegAlloc();
1270 }
1271 
1272 bool GCNPassConfig::addPreRewrite() {
1273   if (EnableRegReassign)
1274     addPass(&GCNNSAReassignID);
1275   return true;
1276 }
1277 
1278 FunctionPass *GCNPassConfig::createSGPRAllocPass(bool Optimized) {
1279   // Initialize the global default.
1280   llvm::call_once(InitializeDefaultSGPRRegisterAllocatorFlag,
1281                   initializeDefaultSGPRRegisterAllocatorOnce);
1282 
1283   RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
1284   if (Ctor != useDefaultRegisterAllocator)
1285     return Ctor();
1286 
1287   if (Optimized)
1288     return createGreedyRegisterAllocator(onlyAllocateSGPRs);
1289 
1290   return createFastRegisterAllocator(onlyAllocateSGPRs, false);
1291 }
1292 
1293 FunctionPass *GCNPassConfig::createVGPRAllocPass(bool Optimized) {
1294   // Initialize the global default.
1295   llvm::call_once(InitializeDefaultVGPRRegisterAllocatorFlag,
1296                   initializeDefaultVGPRRegisterAllocatorOnce);
1297 
1298   RegisterRegAlloc::FunctionPassCtor Ctor = VGPRRegisterRegAlloc::getDefault();
1299   if (Ctor != useDefaultRegisterAllocator)
1300     return Ctor();
1301 
1302   if (Optimized)
1303     return createGreedyVGPRRegisterAllocator();
1304 
1305   return createFastVGPRRegisterAllocator();
1306 }
1307 
1308 FunctionPass *GCNPassConfig::createRegAllocPass(bool Optimized) {
1309   llvm_unreachable("should not be used");
1310 }
1311 
1312 static const char RegAllocOptNotSupportedMessage[] =
1313   "-regalloc not supported with amdgcn. Use -sgpr-regalloc and -vgpr-regalloc";
1314 
1315 bool GCNPassConfig::addRegAssignAndRewriteFast() {
1316   if (!usingDefaultRegAlloc())
1317     report_fatal_error(RegAllocOptNotSupportedMessage);
1318 
1319   addPass(createSGPRAllocPass(false));
1320 
1321   // Equivalent of PEI for SGPRs.
1322   addPass(&SILowerSGPRSpillsID);
1323 
1324   addPass(createVGPRAllocPass(false));
1325   return true;
1326 }
1327 
1328 bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
1329   if (!usingDefaultRegAlloc())
1330     report_fatal_error(RegAllocOptNotSupportedMessage);
1331 
1332   addPass(createSGPRAllocPass(true));
1333 
1334   // Commit allocated register changes. This is mostly necessary because too
1335   // many things rely on the use lists of the physical registers, such as the
1336   // verifier. This is only necessary with allocators which use LiveIntervals,
1337   // since FastRegAlloc does the replacements itself.
1338   addPass(createVirtRegRewriter(false));
1339 
1340   // Equivalent of PEI for SGPRs.
1341   addPass(&SILowerSGPRSpillsID);
1342 
1343   addPass(createVGPRAllocPass(true));
1344 
1345   addPreRewrite();
1346   addPass(&VirtRegRewriterID);
1347 
1348   return true;
1349 }
1350 
1351 void GCNPassConfig::addPostRegAlloc() {
1352   addPass(&SIFixVGPRCopiesID);
1353   if (getOptLevel() > CodeGenOpt::None)
1354     addPass(&SIOptimizeExecMaskingID);
1355   TargetPassConfig::addPostRegAlloc();
1356 }
1357 
1358 void GCNPassConfig::addPreSched2() {
1359   if (TM->getOptLevel() > CodeGenOpt::None)
1360     addPass(createSIShrinkInstructionsPass());
1361   addPass(&SIPostRABundlerID);
1362 }
1363 
1364 void GCNPassConfig::addPreEmitPass() {
1365   addPass(createSIMemoryLegalizerPass());
1366   addPass(createSIInsertWaitcntsPass());
1367 
1368   addPass(createSIModeRegisterPass());
1369 
1370   if (getOptLevel() > CodeGenOpt::None)
1371     addPass(&SIInsertHardClausesID);
1372 
1373   addPass(&SILateBranchLoweringPassID);
1374   if (getOptLevel() > CodeGenOpt::None)
1375     addPass(&SIPreEmitPeepholeID);
1376   // The hazard recognizer that runs as part of the post-ra scheduler does not
1377   // guarantee to be able handle all hazards correctly. This is because if there
1378   // are multiple scheduling regions in a basic block, the regions are scheduled
1379   // bottom up, so when we begin to schedule a region we don't know what
1380   // instructions were emitted directly before it.
1381   //
1382   // Here we add a stand-alone hazard recognizer pass which can handle all
1383   // cases.
1384   addPass(&PostRAHazardRecognizerID);
1385   addPass(&BranchRelaxationPassID);
1386 }
1387 
1388 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1389   return new GCNPassConfig(*this, PM);
1390 }
1391 
1392 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1393   return new yaml::SIMachineFunctionInfo();
1394 }
1395 
1396 yaml::MachineFunctionInfo *
1397 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1398   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1399   return new yaml::SIMachineFunctionInfo(
1400       *MFI, *MF.getSubtarget().getRegisterInfo(), MF);
1401 }
1402 
1403 bool GCNTargetMachine::parseMachineFunctionInfo(
1404     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1405     SMDiagnostic &Error, SMRange &SourceRange) const {
1406   const yaml::SIMachineFunctionInfo &YamlMFI =
1407       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1408   MachineFunction &MF = PFS.MF;
1409   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1410 
1411   if (MFI->initializeBaseYamlFields(YamlMFI, MF, PFS, Error, SourceRange))
1412     return true;
1413 
1414   if (MFI->Occupancy == 0) {
1415     // Fixup the subtarget dependent default value.
1416     const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1417     MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1418   }
1419 
1420   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1421     Register TempReg;
1422     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1423       SourceRange = RegName.SourceRange;
1424       return true;
1425     }
1426     RegVal = TempReg;
1427 
1428     return false;
1429   };
1430 
1431   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1432     // Create a diagnostic for a the register string literal.
1433     const MemoryBuffer &Buffer =
1434         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1435     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1436                          RegName.Value.size(), SourceMgr::DK_Error,
1437                          "incorrect register class for field", RegName.Value,
1438                          None, None);
1439     SourceRange = RegName.SourceRange;
1440     return true;
1441   };
1442 
1443   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1444       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1445       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1446     return true;
1447 
1448   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1449       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1450     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1451   }
1452 
1453   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1454       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1455     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1456   }
1457 
1458   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1459       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1460     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1461   }
1462 
1463   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1464                                    const TargetRegisterClass &RC,
1465                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1466                                    unsigned SystemSGPRs) {
1467     // Skip parsing if it's not present.
1468     if (!A)
1469       return false;
1470 
1471     if (A->IsRegister) {
1472       Register Reg;
1473       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1474         SourceRange = A->RegisterName.SourceRange;
1475         return true;
1476       }
1477       if (!RC.contains(Reg))
1478         return diagnoseRegisterClass(A->RegisterName);
1479       Arg = ArgDescriptor::createRegister(Reg);
1480     } else
1481       Arg = ArgDescriptor::createStack(A->StackOffset);
1482     // Check and apply the optional mask.
1483     if (A->Mask)
1484       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1485 
1486     MFI->NumUserSGPRs += UserSGPRs;
1487     MFI->NumSystemSGPRs += SystemSGPRs;
1488     return false;
1489   };
1490 
1491   if (YamlMFI.ArgInfo &&
1492       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1493                              AMDGPU::SGPR_128RegClass,
1494                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1495        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1496                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1497                              2, 0) ||
1498        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1499                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1500        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1501                              AMDGPU::SReg_64RegClass,
1502                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1503        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1504                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1505                              2, 0) ||
1506        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1507                              AMDGPU::SReg_64RegClass,
1508                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1509        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1510                              AMDGPU::SGPR_32RegClass,
1511                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1512        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1513                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1514                              0, 1) ||
1515        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1516                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1517                              0, 1) ||
1518        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1519                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1520                              0, 1) ||
1521        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1522                              AMDGPU::SGPR_32RegClass,
1523                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1524        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1525                              AMDGPU::SGPR_32RegClass,
1526                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1527        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1528                              AMDGPU::SReg_64RegClass,
1529                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1530        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1531                              AMDGPU::SReg_64RegClass,
1532                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1533        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1534                              AMDGPU::VGPR_32RegClass,
1535                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1536        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1537                              AMDGPU::VGPR_32RegClass,
1538                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1539        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1540                              AMDGPU::VGPR_32RegClass,
1541                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1542     return true;
1543 
1544   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1545   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1546   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1547   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1548   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1549   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1550 
1551   return false;
1552 }
1553