xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (revision 06c3fb2749bda94cb5201f81ffdb8fa6c3161b2e) 
1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for SI+ GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCtorDtorLowering.h"
19 #include "AMDGPUExportClustering.h"
20 #include "AMDGPUIGroupLP.h"
21 #include "AMDGPUMacroFusion.h"
22 #include "AMDGPURegBankSelect.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "AMDGPUUnifyDivergentExitNodes.h"
26 #include "GCNIterativeScheduler.h"
27 #include "GCNSchedStrategy.h"
28 #include "GCNVOPDUtils.h"
29 #include "R600.h"
30 #include "R600MachineFunctionInfo.h"
31 #include "R600TargetMachine.h"
32 #include "SIMachineFunctionInfo.h"
33 #include "SIMachineScheduler.h"
34 #include "TargetInfo/AMDGPUTargetInfo.h"
35 #include "Utils/AMDGPUBaseInfo.h"
36 #include "llvm/Analysis/CGSCCPassManager.h"
37 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
38 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
39 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
40 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
41 #include "llvm/CodeGen/GlobalISel/Localizer.h"
42 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
43 #include "llvm/CodeGen/MIRParser/MIParser.h"
44 #include "llvm/CodeGen/Passes.h"
45 #include "llvm/CodeGen/RegAllocRegistry.h"
46 #include "llvm/CodeGen/TargetPassConfig.h"
47 #include "llvm/IR/IntrinsicsAMDGPU.h"
48 #include "llvm/IR/PassManager.h"
49 #include "llvm/IR/PatternMatch.h"
50 #include "llvm/InitializePasses.h"
51 #include "llvm/MC/TargetRegistry.h"
52 #include "llvm/Passes/PassBuilder.h"
53 #include "llvm/Transforms/IPO.h"
54 #include "llvm/Transforms/IPO/AlwaysInliner.h"
55 #include "llvm/Transforms/IPO/GlobalDCE.h"
56 #include "llvm/Transforms/IPO/Internalize.h"
57 #include "llvm/Transforms/Scalar.h"
58 #include "llvm/Transforms/Scalar/GVN.h"
59 #include "llvm/Transforms/Scalar/InferAddressSpaces.h"
60 #include "llvm/Transforms/Utils.h"
61 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
62 #include "llvm/Transforms/Vectorize/LoadStoreVectorizer.h"
63 #include <optional>
64 
65 using namespace llvm;
66 using namespace llvm::PatternMatch;
67 
68 namespace {
69 class SGPRRegisterRegAlloc : public RegisterRegAllocBase<SGPRRegisterRegAlloc> {
70 public:
71   SGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
72     : RegisterRegAllocBase(N, D, C) {}
73 };
74 
75 class VGPRRegisterRegAlloc : public RegisterRegAllocBase<VGPRRegisterRegAlloc> {
76 public:
77   VGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
78     : RegisterRegAllocBase(N, D, C) {}
79 };
80 
81 static bool onlyAllocateSGPRs(const TargetRegisterInfo &TRI,
82                               const TargetRegisterClass &RC) {
83   return static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
84 }
85 
86 static bool onlyAllocateVGPRs(const TargetRegisterInfo &TRI,
87                               const TargetRegisterClass &RC) {
88   return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
89 }
90 
91 
92 /// -{sgpr|vgpr}-regalloc=... command line option.
93 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
94 
95 /// A dummy default pass factory indicates whether the register allocator is
96 /// overridden on the command line.
97 static llvm::once_flag InitializeDefaultSGPRRegisterAllocatorFlag;
98 static llvm::once_flag InitializeDefaultVGPRRegisterAllocatorFlag;
99 
100 static SGPRRegisterRegAlloc
101 defaultSGPRRegAlloc("default",
102                     "pick SGPR register allocator based on -O option",
103                     useDefaultRegisterAllocator);
104 
105 static cl::opt<SGPRRegisterRegAlloc::FunctionPassCtor, false,
106                RegisterPassParser<SGPRRegisterRegAlloc>>
107 SGPRRegAlloc("sgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
108              cl::desc("Register allocator to use for SGPRs"));
109 
110 static cl::opt<VGPRRegisterRegAlloc::FunctionPassCtor, false,
111                RegisterPassParser<VGPRRegisterRegAlloc>>
112 VGPRRegAlloc("vgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
113              cl::desc("Register allocator to use for VGPRs"));
114 
115 
116 static void initializeDefaultSGPRRegisterAllocatorOnce() {
117   RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
118 
119   if (!Ctor) {
120     Ctor = SGPRRegAlloc;
121     SGPRRegisterRegAlloc::setDefault(SGPRRegAlloc);
122   }
123 }
124 
125 static void initializeDefaultVGPRRegisterAllocatorOnce() {
126   RegisterRegAlloc::FunctionPassCtor Ctor = VGPRRegisterRegAlloc::getDefault();
127 
128   if (!Ctor) {
129     Ctor = VGPRRegAlloc;
130     VGPRRegisterRegAlloc::setDefault(VGPRRegAlloc);
131   }
132 }
133 
134 static FunctionPass *createBasicSGPRRegisterAllocator() {
135   return createBasicRegisterAllocator(onlyAllocateSGPRs);
136 }
137 
138 static FunctionPass *createGreedySGPRRegisterAllocator() {
139   return createGreedyRegisterAllocator(onlyAllocateSGPRs);
140 }
141 
142 static FunctionPass *createFastSGPRRegisterAllocator() {
143   return createFastRegisterAllocator(onlyAllocateSGPRs, false);
144 }
145 
146 static FunctionPass *createBasicVGPRRegisterAllocator() {
147   return createBasicRegisterAllocator(onlyAllocateVGPRs);
148 }
149 
150 static FunctionPass *createGreedyVGPRRegisterAllocator() {
151   return createGreedyRegisterAllocator(onlyAllocateVGPRs);
152 }
153 
154 static FunctionPass *createFastVGPRRegisterAllocator() {
155   return createFastRegisterAllocator(onlyAllocateVGPRs, true);
156 }
157 
158 static SGPRRegisterRegAlloc basicRegAllocSGPR(
159   "basic", "basic register allocator", createBasicSGPRRegisterAllocator);
160 static SGPRRegisterRegAlloc greedyRegAllocSGPR(
161   "greedy", "greedy register allocator", createGreedySGPRRegisterAllocator);
162 
163 static SGPRRegisterRegAlloc fastRegAllocSGPR(
164   "fast", "fast register allocator", createFastSGPRRegisterAllocator);
165 
166 
167 static VGPRRegisterRegAlloc basicRegAllocVGPR(
168   "basic", "basic register allocator", createBasicVGPRRegisterAllocator);
169 static VGPRRegisterRegAlloc greedyRegAllocVGPR(
170   "greedy", "greedy register allocator", createGreedyVGPRRegisterAllocator);
171 
172 static VGPRRegisterRegAlloc fastRegAllocVGPR(
173   "fast", "fast register allocator", createFastVGPRRegisterAllocator);
174 }
175 
176 static cl::opt<bool> EnableSROA(
177   "amdgpu-sroa",
178   cl::desc("Run SROA after promote alloca pass"),
179   cl::ReallyHidden,
180   cl::init(true));
181 
182 static cl::opt<bool>
183 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
184                         cl::desc("Run early if-conversion"),
185                         cl::init(false));
186 
187 static cl::opt<bool>
188 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
189             cl::desc("Run pre-RA exec mask optimizations"),
190             cl::init(true));
191 
192 static cl::opt<bool>
193     LowerCtorDtor("amdgpu-lower-global-ctor-dtor",
194                   cl::desc("Lower GPU ctor / dtors to globals on the device."),
195                   cl::init(true), cl::Hidden);
196 
197 // Option to disable vectorizer for tests.
198 static cl::opt<bool> EnableLoadStoreVectorizer(
199   "amdgpu-load-store-vectorizer",
200   cl::desc("Enable load store vectorizer"),
201   cl::init(true),
202   cl::Hidden);
203 
204 // Option to control global loads scalarization
205 static cl::opt<bool> ScalarizeGlobal(
206   "amdgpu-scalarize-global-loads",
207   cl::desc("Enable global load scalarization"),
208   cl::init(true),
209   cl::Hidden);
210 
211 // Option to run internalize pass.
212 static cl::opt<bool> InternalizeSymbols(
213   "amdgpu-internalize-symbols",
214   cl::desc("Enable elimination of non-kernel functions and unused globals"),
215   cl::init(false),
216   cl::Hidden);
217 
218 // Option to inline all early.
219 static cl::opt<bool> EarlyInlineAll(
220   "amdgpu-early-inline-all",
221   cl::desc("Inline all functions early"),
222   cl::init(false),
223   cl::Hidden);
224 
225 static cl::opt<bool> RemoveIncompatibleFunctions(
226     "amdgpu-enable-remove-incompatible-functions", cl::Hidden,
227     cl::desc("Enable removal of functions when they"
228              "use features not supported by the target GPU"),
229     cl::init(true));
230 
231 static cl::opt<bool> EnableSDWAPeephole(
232   "amdgpu-sdwa-peephole",
233   cl::desc("Enable SDWA peepholer"),
234   cl::init(true));
235 
236 static cl::opt<bool> EnableDPPCombine(
237   "amdgpu-dpp-combine",
238   cl::desc("Enable DPP combiner"),
239   cl::init(true));
240 
241 // Enable address space based alias analysis
242 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
243   cl::desc("Enable AMDGPU Alias Analysis"),
244   cl::init(true));
245 
246 // Option to run late CFG structurizer
247 static cl::opt<bool, true> LateCFGStructurize(
248   "amdgpu-late-structurize",
249   cl::desc("Enable late CFG structurization"),
250   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
251   cl::Hidden);
252 
253 // Enable lib calls simplifications
254 static cl::opt<bool> EnableLibCallSimplify(
255   "amdgpu-simplify-libcall",
256   cl::desc("Enable amdgpu library simplifications"),
257   cl::init(true),
258   cl::Hidden);
259 
260 static cl::opt<bool> EnableLowerKernelArguments(
261   "amdgpu-ir-lower-kernel-arguments",
262   cl::desc("Lower kernel argument loads in IR pass"),
263   cl::init(true),
264   cl::Hidden);
265 
266 static cl::opt<bool> EnableRegReassign(
267   "amdgpu-reassign-regs",
268   cl::desc("Enable register reassign optimizations on gfx10+"),
269   cl::init(true),
270   cl::Hidden);
271 
272 static cl::opt<bool> OptVGPRLiveRange(
273     "amdgpu-opt-vgpr-liverange",
274     cl::desc("Enable VGPR liverange optimizations for if-else structure"),
275     cl::init(true), cl::Hidden);
276 
277 static cl::opt<ScanOptions> AMDGPUAtomicOptimizerStrategy(
278     "amdgpu-atomic-optimizer-strategy",
279     cl::desc("Select DPP or Iterative strategy for scan"),
280     cl::init(ScanOptions::Iterative),
281     cl::values(
282         clEnumValN(ScanOptions::DPP, "DPP", "Use DPP operations for scan"),
283         clEnumValN(ScanOptions::Iterative, "Iterative",
284                    "Use Iterative approach for scan"),
285         clEnumValN(ScanOptions::None, "None", "Disable atomic optimizer")));
286 
287 // Enable Mode register optimization
288 static cl::opt<bool> EnableSIModeRegisterPass(
289   "amdgpu-mode-register",
290   cl::desc("Enable mode register pass"),
291   cl::init(true),
292   cl::Hidden);
293 
294 // Enable GFX11+ s_delay_alu insertion
295 static cl::opt<bool>
296     EnableInsertDelayAlu("amdgpu-enable-delay-alu",
297                          cl::desc("Enable s_delay_alu insertion"),
298                          cl::init(true), cl::Hidden);
299 
300 // Enable GFX11+ VOPD
301 static cl::opt<bool>
302     EnableVOPD("amdgpu-enable-vopd",
303                cl::desc("Enable VOPD, dual issue of VALU in wave32"),
304                cl::init(true), cl::Hidden);
305 
306 // Option is used in lit tests to prevent deadcoding of patterns inspected.
307 static cl::opt<bool>
308 EnableDCEInRA("amdgpu-dce-in-ra",
309     cl::init(true), cl::Hidden,
310     cl::desc("Enable machine DCE inside regalloc"));
311 
312 static cl::opt<bool> EnableSetWavePriority("amdgpu-set-wave-priority",
313                                            cl::desc("Adjust wave priority"),
314                                            cl::init(false), cl::Hidden);
315 
316 static cl::opt<bool> EnableScalarIRPasses(
317   "amdgpu-scalar-ir-passes",
318   cl::desc("Enable scalar IR passes"),
319   cl::init(true),
320   cl::Hidden);
321 
322 static cl::opt<bool> EnableStructurizerWorkarounds(
323     "amdgpu-enable-structurizer-workarounds",
324     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
325     cl::Hidden);
326 
327 static cl::opt<bool, true> EnableLowerModuleLDS(
328     "amdgpu-enable-lower-module-lds", cl::desc("Enable lower module lds pass"),
329     cl::location(AMDGPUTargetMachine::EnableLowerModuleLDS), cl::init(true),
330     cl::Hidden);
331 
332 static cl::opt<bool> EnablePreRAOptimizations(
333     "amdgpu-enable-pre-ra-optimizations",
334     cl::desc("Enable Pre-RA optimizations pass"), cl::init(true),
335     cl::Hidden);
336 
337 static cl::opt<bool> EnablePromoteKernelArguments(
338     "amdgpu-enable-promote-kernel-arguments",
339     cl::desc("Enable promotion of flat kernel pointer arguments to global"),
340     cl::Hidden, cl::init(true));
341 
342 static cl::opt<bool> EnableMaxIlpSchedStrategy(
343     "amdgpu-enable-max-ilp-scheduling-strategy",
344     cl::desc("Enable scheduling strategy to maximize ILP for a single wave."),
345     cl::Hidden, cl::init(false));
346 
347 static cl::opt<bool> EnableRewritePartialRegUses(
348     "amdgpu-enable-rewrite-partial-reg-uses",
349     cl::desc("Enable rewrite partial reg uses pass"), cl::init(false),
350     cl::Hidden);
351 
352 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
353   // Register the target
354   RegisterTargetMachine<R600TargetMachine> X(getTheR600Target());
355   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
356 
357   PassRegistry *PR = PassRegistry::getPassRegistry();
358   initializeR600ClauseMergePassPass(*PR);
359   initializeR600ControlFlowFinalizerPass(*PR);
360   initializeR600PacketizerPass(*PR);
361   initializeR600ExpandSpecialInstrsPassPass(*PR);
362   initializeR600VectorRegMergerPass(*PR);
363   initializeGlobalISel(*PR);
364   initializeAMDGPUDAGToDAGISelPass(*PR);
365   initializeGCNDPPCombinePass(*PR);
366   initializeSILowerI1CopiesPass(*PR);
367   initializeSILowerWWMCopiesPass(*PR);
368   initializeSILowerSGPRSpillsPass(*PR);
369   initializeSIFixSGPRCopiesPass(*PR);
370   initializeSIFixVGPRCopiesPass(*PR);
371   initializeSIFoldOperandsPass(*PR);
372   initializeSIPeepholeSDWAPass(*PR);
373   initializeSIShrinkInstructionsPass(*PR);
374   initializeSIOptimizeExecMaskingPreRAPass(*PR);
375   initializeSIOptimizeVGPRLiveRangePass(*PR);
376   initializeSILoadStoreOptimizerPass(*PR);
377   initializeAMDGPUCtorDtorLoweringLegacyPass(*PR);
378   initializeAMDGPUAlwaysInlinePass(*PR);
379   initializeAMDGPUAttributorPass(*PR);
380   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
381   initializeAMDGPUAnnotateUniformValuesPass(*PR);
382   initializeAMDGPUArgumentUsageInfoPass(*PR);
383   initializeAMDGPUAtomicOptimizerPass(*PR);
384   initializeAMDGPULowerKernelArgumentsPass(*PR);
385   initializeAMDGPUPromoteKernelArgumentsPass(*PR);
386   initializeAMDGPULowerKernelAttributesPass(*PR);
387   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
388   initializeAMDGPUPostLegalizerCombinerPass(*PR);
389   initializeAMDGPUPreLegalizerCombinerPass(*PR);
390   initializeAMDGPURegBankCombinerPass(*PR);
391   initializeAMDGPURegBankSelectPass(*PR);
392   initializeAMDGPUPromoteAllocaPass(*PR);
393   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
394   initializeAMDGPUCodeGenPreparePass(*PR);
395   initializeAMDGPULateCodeGenPreparePass(*PR);
396   initializeAMDGPURemoveIncompatibleFunctionsPass(*PR);
397   initializeAMDGPULowerModuleLDSPass(*PR);
398   initializeAMDGPURewriteOutArgumentsPass(*PR);
399   initializeAMDGPURewriteUndefForPHIPass(*PR);
400   initializeAMDGPUUnifyMetadataPass(*PR);
401   initializeSIAnnotateControlFlowPass(*PR);
402   initializeAMDGPUInsertDelayAluPass(*PR);
403   initializeSIInsertHardClausesPass(*PR);
404   initializeSIInsertWaitcntsPass(*PR);
405   initializeSIModeRegisterPass(*PR);
406   initializeSIWholeQuadModePass(*PR);
407   initializeSILowerControlFlowPass(*PR);
408   initializeSIPreEmitPeepholePass(*PR);
409   initializeSILateBranchLoweringPass(*PR);
410   initializeSIMemoryLegalizerPass(*PR);
411   initializeSIOptimizeExecMaskingPass(*PR);
412   initializeSIPreAllocateWWMRegsPass(*PR);
413   initializeSIFormMemoryClausesPass(*PR);
414   initializeSIPostRABundlerPass(*PR);
415   initializeGCNCreateVOPDPass(*PR);
416   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
417   initializeAMDGPUAAWrapperPassPass(*PR);
418   initializeAMDGPUExternalAAWrapperPass(*PR);
419   initializeAMDGPUUseNativeCallsPass(*PR);
420   initializeAMDGPUSimplifyLibCallsPass(*PR);
421   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
422   initializeAMDGPUResourceUsageAnalysisPass(*PR);
423   initializeGCNNSAReassignPass(*PR);
424   initializeGCNPreRAOptimizationsPass(*PR);
425   initializeGCNPreRALongBranchRegPass(*PR);
426   initializeGCNRewritePartialRegUsesPass(*PR);
427 }
428 
429 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
430   return std::make_unique<AMDGPUTargetObjectFile>();
431 }
432 
433 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
434   return new SIScheduleDAGMI(C);
435 }
436 
437 static ScheduleDAGInstrs *
438 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
439   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
440   ScheduleDAGMILive *DAG =
441     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
442   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
443   if (ST.shouldClusterStores())
444     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
445   DAG->addMutation(createIGroupLPDAGMutation());
446   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
447   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
448   return DAG;
449 }
450 
451 static ScheduleDAGInstrs *
452 createGCNMaxILPMachineScheduler(MachineSchedContext *C) {
453   ScheduleDAGMILive *DAG =
454       new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxILPSchedStrategy>(C));
455   DAG->addMutation(createIGroupLPDAGMutation());
456   return DAG;
457 }
458 
459 static ScheduleDAGInstrs *
460 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
461   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
462   auto DAG = new GCNIterativeScheduler(C,
463     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
464   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
465   if (ST.shouldClusterStores())
466     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
467   return DAG;
468 }
469 
470 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
471   return new GCNIterativeScheduler(C,
472     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
473 }
474 
475 static ScheduleDAGInstrs *
476 createIterativeILPMachineScheduler(MachineSchedContext *C) {
477   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
478   auto DAG = new GCNIterativeScheduler(C,
479     GCNIterativeScheduler::SCHEDULE_ILP);
480   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
481   if (ST.shouldClusterStores())
482     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
483   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
484   return DAG;
485 }
486 
487 static MachineSchedRegistry
488 SISchedRegistry("si", "Run SI's custom scheduler",
489                 createSIMachineScheduler);
490 
491 static MachineSchedRegistry
492 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
493                              "Run GCN scheduler to maximize occupancy",
494                              createGCNMaxOccupancyMachineScheduler);
495 
496 static MachineSchedRegistry
497     GCNMaxILPSchedRegistry("gcn-max-ilp", "Run GCN scheduler to maximize ilp",
498                            createGCNMaxILPMachineScheduler);
499 
500 static MachineSchedRegistry IterativeGCNMaxOccupancySchedRegistry(
501     "gcn-iterative-max-occupancy-experimental",
502     "Run GCN scheduler to maximize occupancy (experimental)",
503     createIterativeGCNMaxOccupancyMachineScheduler);
504 
505 static MachineSchedRegistry GCNMinRegSchedRegistry(
506     "gcn-iterative-minreg",
507     "Run GCN iterative scheduler for minimal register usage (experimental)",
508     createMinRegScheduler);
509 
510 static MachineSchedRegistry GCNILPSchedRegistry(
511     "gcn-iterative-ilp",
512     "Run GCN iterative scheduler for ILP scheduling (experimental)",
513     createIterativeILPMachineScheduler);
514 
515 static StringRef computeDataLayout(const Triple &TT) {
516   if (TT.getArch() == Triple::r600) {
517     // 32-bit pointers.
518     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
519            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
520   }
521 
522   // 32-bit private, local, and region pointers. 64-bit global, constant and
523   // flat. 160-bit non-integral fat buffer pointers that include a 128-bit
524   // buffer descriptor and a 32-bit offset, which are indexed by 32-bit values
525   // (address space 7), and 128-bit non-integral buffer resourcees (address
526   // space 8) which cannot be non-trivilally accessed by LLVM memory operations
527   // like getelementptr.
528   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
529          "-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:"
530          "128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-"
531          "G1-ni:7:8";
532 }
533 
534 LLVM_READNONE
535 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
536   if (!GPU.empty())
537     return GPU;
538 
539   // Need to default to a target with flat support for HSA.
540   if (TT.getArch() == Triple::amdgcn)
541     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
542 
543   return "r600";
544 }
545 
546 static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
547   // The AMDGPU toolchain only supports generating shared objects, so we
548   // must always use PIC.
549   return Reloc::PIC_;
550 }
551 
552 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
553                                          StringRef CPU, StringRef FS,
554                                          TargetOptions Options,
555                                          std::optional<Reloc::Model> RM,
556                                          std::optional<CodeModel::Model> CM,
557                                          CodeGenOpt::Level OptLevel)
558     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
559                         FS, Options, getEffectiveRelocModel(RM),
560                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
561       TLOF(createTLOF(getTargetTriple())) {
562   initAsmInfo();
563   if (TT.getArch() == Triple::amdgcn) {
564     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
565       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
566     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
567       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
568   }
569 }
570 
571 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
572 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
573 bool AMDGPUTargetMachine::EnableLowerModuleLDS = true;
574 
575 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
576 
577 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
578   Attribute GPUAttr = F.getFnAttribute("target-cpu");
579   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
580 }
581 
582 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
583   Attribute FSAttr = F.getFnAttribute("target-features");
584 
585   return FSAttr.isValid() ? FSAttr.getValueAsString()
586                           : getTargetFeatureString();
587 }
588 
589 /// Predicate for Internalize pass.
590 static bool mustPreserveGV(const GlobalValue &GV) {
591   if (const Function *F = dyn_cast<Function>(&GV))
592     return F->isDeclaration() || F->getName().startswith("__asan_") ||
593            F->getName().startswith("__sanitizer_") ||
594            AMDGPU::isEntryFunctionCC(F->getCallingConv());
595 
596   GV.removeDeadConstantUsers();
597   return !GV.use_empty();
598 }
599 
600 void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
601   AAM.registerFunctionAnalysis<AMDGPUAA>();
602 }
603 
604 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
605   PB.registerPipelineParsingCallback(
606       [](StringRef PassName, ModulePassManager &PM,
607          ArrayRef<PassBuilder::PipelineElement>) {
608         if (PassName == "amdgpu-unify-metadata") {
609           PM.addPass(AMDGPUUnifyMetadataPass());
610           return true;
611         }
612         if (PassName == "amdgpu-printf-runtime-binding") {
613           PM.addPass(AMDGPUPrintfRuntimeBindingPass());
614           return true;
615         }
616         if (PassName == "amdgpu-always-inline") {
617           PM.addPass(AMDGPUAlwaysInlinePass());
618           return true;
619         }
620         if (PassName == "amdgpu-lower-module-lds") {
621           PM.addPass(AMDGPULowerModuleLDSPass());
622           return true;
623         }
624         if (PassName == "amdgpu-lower-ctor-dtor") {
625           PM.addPass(AMDGPUCtorDtorLoweringPass());
626           return true;
627         }
628         return false;
629       });
630   PB.registerPipelineParsingCallback(
631       [this](StringRef PassName, FunctionPassManager &PM,
632              ArrayRef<PassBuilder::PipelineElement>) {
633         if (PassName == "amdgpu-simplifylib") {
634           PM.addPass(AMDGPUSimplifyLibCallsPass(*this));
635           return true;
636         }
637         if (PassName == "amdgpu-usenative") {
638           PM.addPass(AMDGPUUseNativeCallsPass());
639           return true;
640         }
641         if (PassName == "amdgpu-promote-alloca") {
642           PM.addPass(AMDGPUPromoteAllocaPass(*this));
643           return true;
644         }
645         if (PassName == "amdgpu-promote-alloca-to-vector") {
646           PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
647           return true;
648         }
649         if (PassName == "amdgpu-lower-kernel-attributes") {
650           PM.addPass(AMDGPULowerKernelAttributesPass());
651           return true;
652         }
653         if (PassName == "amdgpu-promote-kernel-arguments") {
654           PM.addPass(AMDGPUPromoteKernelArgumentsPass());
655           return true;
656         }
657         if (PassName == "amdgpu-unify-divergent-exit-nodes") {
658           PM.addPass(AMDGPUUnifyDivergentExitNodesPass());
659           return true;
660         }
661         if (PassName == "amdgpu-atomic-optimizer") {
662           PM.addPass(
663               AMDGPUAtomicOptimizerPass(*this, AMDGPUAtomicOptimizerStrategy));
664           return true;
665         }
666         if (PassName == "amdgpu-codegenprepare") {
667           PM.addPass(AMDGPUCodeGenPreparePass(*this));
668           return true;
669         }
670         return false;
671       });
672 
673   PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
674     FAM.registerPass([&] { return AMDGPUAA(); });
675   });
676 
677   PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
678     if (AAName == "amdgpu-aa") {
679       AAM.registerFunctionAnalysis<AMDGPUAA>();
680       return true;
681     }
682     return false;
683   });
684 
685   PB.registerPipelineStartEPCallback(
686       [this](ModulePassManager &PM, OptimizationLevel Level) {
687         FunctionPassManager FPM;
688         FPM.addPass(AMDGPUUseNativeCallsPass());
689         if (EnableLibCallSimplify && Level != OptimizationLevel::O0)
690           FPM.addPass(AMDGPUSimplifyLibCallsPass(*this));
691         PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
692       });
693 
694   PB.registerPipelineEarlySimplificationEPCallback(
695       [](ModulePassManager &PM, OptimizationLevel Level) {
696         PM.addPass(AMDGPUPrintfRuntimeBindingPass());
697 
698         if (Level == OptimizationLevel::O0)
699           return;
700 
701         PM.addPass(AMDGPUUnifyMetadataPass());
702 
703         if (InternalizeSymbols) {
704           PM.addPass(InternalizePass(mustPreserveGV));
705           PM.addPass(GlobalDCEPass());
706         }
707 
708         if (EarlyInlineAll && !EnableFunctionCalls)
709           PM.addPass(AMDGPUAlwaysInlinePass());
710       });
711 
712   PB.registerCGSCCOptimizerLateEPCallback(
713       [this](CGSCCPassManager &PM, OptimizationLevel Level) {
714         if (Level == OptimizationLevel::O0)
715           return;
716 
717         FunctionPassManager FPM;
718 
719         // Add promote kernel arguments pass to the opt pipeline right before
720         // infer address spaces which is needed to do actual address space
721         // rewriting.
722         if (Level.getSpeedupLevel() > OptimizationLevel::O1.getSpeedupLevel() &&
723             EnablePromoteKernelArguments)
724           FPM.addPass(AMDGPUPromoteKernelArgumentsPass());
725 
726         // Add infer address spaces pass to the opt pipeline after inlining
727         // but before SROA to increase SROA opportunities.
728         FPM.addPass(InferAddressSpacesPass());
729 
730         // This should run after inlining to have any chance of doing
731         // anything, and before other cleanup optimizations.
732         FPM.addPass(AMDGPULowerKernelAttributesPass());
733 
734         if (Level != OptimizationLevel::O0) {
735           // Promote alloca to vector before SROA and loop unroll. If we
736           // manage to eliminate allocas before unroll we may choose to unroll
737           // less.
738           FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
739         }
740 
741         PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));
742       });
743 }
744 
745 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
746   return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
747           AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
748           AddrSpace == AMDGPUAS::REGION_ADDRESS)
749              ? -1
750              : 0;
751 }
752 
753 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
754                                               unsigned DestAS) const {
755   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
756          AMDGPU::isFlatGlobalAddrSpace(DestAS);
757 }
758 
759 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
760   const auto *LD = dyn_cast<LoadInst>(V);
761   if (!LD)
762     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
763 
764   // It must be a generic pointer loaded.
765   assert(V->getType()->isPointerTy() &&
766          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
767 
768   const auto *Ptr = LD->getPointerOperand();
769   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
770     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
771   // For a generic pointer loaded from the constant memory, it could be assumed
772   // as a global pointer since the constant memory is only populated on the
773   // host side. As implied by the offload programming model, only global
774   // pointers could be referenced on the host side.
775   return AMDGPUAS::GLOBAL_ADDRESS;
776 }
777 
778 std::pair<const Value *, unsigned>
779 AMDGPUTargetMachine::getPredicatedAddrSpace(const Value *V) const {
780   if (auto *II = dyn_cast<IntrinsicInst>(V)) {
781     switch (II->getIntrinsicID()) {
782     case Intrinsic::amdgcn_is_shared:
783       return std::pair(II->getArgOperand(0), AMDGPUAS::LOCAL_ADDRESS);
784     case Intrinsic::amdgcn_is_private:
785       return std::pair(II->getArgOperand(0), AMDGPUAS::PRIVATE_ADDRESS);
786     default:
787       break;
788     }
789     return std::pair(nullptr, -1);
790   }
791   // Check the global pointer predication based on
792   // (!is_share(p) && !is_private(p)). Note that logic 'and' is commutative and
793   // the order of 'is_shared' and 'is_private' is not significant.
794   Value *Ptr;
795   if (match(
796           const_cast<Value *>(V),
797           m_c_And(m_Not(m_Intrinsic<Intrinsic::amdgcn_is_shared>(m_Value(Ptr))),
798                   m_Not(m_Intrinsic<Intrinsic::amdgcn_is_private>(
799                       m_Deferred(Ptr))))))
800     return std::pair(Ptr, AMDGPUAS::GLOBAL_ADDRESS);
801 
802   return std::pair(nullptr, -1);
803 }
804 
805 unsigned
806 AMDGPUTargetMachine::getAddressSpaceForPseudoSourceKind(unsigned Kind) const {
807   switch (Kind) {
808   case PseudoSourceValue::Stack:
809   case PseudoSourceValue::FixedStack:
810     return AMDGPUAS::PRIVATE_ADDRESS;
811   case PseudoSourceValue::ConstantPool:
812   case PseudoSourceValue::GOT:
813   case PseudoSourceValue::JumpTable:
814   case PseudoSourceValue::GlobalValueCallEntry:
815   case PseudoSourceValue::ExternalSymbolCallEntry:
816     return AMDGPUAS::CONSTANT_ADDRESS;
817   }
818   return AMDGPUAS::FLAT_ADDRESS;
819 }
820 
821 //===----------------------------------------------------------------------===//
822 // GCN Target Machine (SI+)
823 //===----------------------------------------------------------------------===//
824 
825 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
826                                    StringRef CPU, StringRef FS,
827                                    TargetOptions Options,
828                                    std::optional<Reloc::Model> RM,
829                                    std::optional<CodeModel::Model> CM,
830                                    CodeGenOpt::Level OL, bool JIT)
831     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
832 
833 const TargetSubtargetInfo *
834 GCNTargetMachine::getSubtargetImpl(const Function &F) const {
835   StringRef GPU = getGPUName(F);
836   StringRef FS = getFeatureString(F);
837 
838   SmallString<128> SubtargetKey(GPU);
839   SubtargetKey.append(FS);
840 
841   auto &I = SubtargetMap[SubtargetKey];
842   if (!I) {
843     // This needs to be done before we create a new subtarget since any
844     // creation will depend on the TM and the code generation flags on the
845     // function that reside in TargetOptions.
846     resetTargetOptions(F);
847     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
848   }
849 
850   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
851 
852   return I.get();
853 }
854 
855 TargetTransformInfo
856 GCNTargetMachine::getTargetTransformInfo(const Function &F) const {
857   return TargetTransformInfo(GCNTTIImpl(this, F));
858 }
859 
860 //===----------------------------------------------------------------------===//
861 // AMDGPU Pass Setup
862 //===----------------------------------------------------------------------===//
863 
864 std::unique_ptr<CSEConfigBase> llvm::AMDGPUPassConfig::getCSEConfig() const {
865   return getStandardCSEConfigForOpt(TM->getOptLevel());
866 }
867 
868 namespace {
869 
870 class GCNPassConfig final : public AMDGPUPassConfig {
871 public:
872   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
873     : AMDGPUPassConfig(TM, PM) {
874     // It is necessary to know the register usage of the entire call graph.  We
875     // allow calls without EnableAMDGPUFunctionCalls if they are marked
876     // noinline, so this is always required.
877     setRequiresCodeGenSCCOrder(true);
878     substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
879   }
880 
881   GCNTargetMachine &getGCNTargetMachine() const {
882     return getTM<GCNTargetMachine>();
883   }
884 
885   ScheduleDAGInstrs *
886   createMachineScheduler(MachineSchedContext *C) const override;
887 
888   ScheduleDAGInstrs *
889   createPostMachineScheduler(MachineSchedContext *C) const override {
890     ScheduleDAGMI *DAG = new GCNPostScheduleDAGMILive(
891         C, std::make_unique<PostGenericScheduler>(C),
892         /*RemoveKillFlags=*/true);
893     const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
894     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
895     if (ST.shouldClusterStores())
896       DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
897     DAG->addMutation(ST.createFillMFMAShadowMutation(DAG->TII));
898     DAG->addMutation(createIGroupLPDAGMutation());
899     if (isPassEnabled(EnableVOPD, CodeGenOpt::Less))
900       DAG->addMutation(createVOPDPairingMutation());
901     return DAG;
902   }
903 
904   bool addPreISel() override;
905   void addMachineSSAOptimization() override;
906   bool addILPOpts() override;
907   bool addInstSelector() override;
908   bool addIRTranslator() override;
909   void addPreLegalizeMachineIR() override;
910   bool addLegalizeMachineIR() override;
911   void addPreRegBankSelect() override;
912   bool addRegBankSelect() override;
913   void addPreGlobalInstructionSelect() override;
914   bool addGlobalInstructionSelect() override;
915   void addFastRegAlloc() override;
916   void addOptimizedRegAlloc() override;
917 
918   FunctionPass *createSGPRAllocPass(bool Optimized);
919   FunctionPass *createVGPRAllocPass(bool Optimized);
920   FunctionPass *createRegAllocPass(bool Optimized) override;
921 
922   bool addRegAssignAndRewriteFast() override;
923   bool addRegAssignAndRewriteOptimized() override;
924 
925   void addPreRegAlloc() override;
926   bool addPreRewrite() override;
927   void addPostRegAlloc() override;
928   void addPreSched2() override;
929   void addPreEmitPass() override;
930 };
931 
932 } // end anonymous namespace
933 
934 AMDGPUPassConfig::AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
935     : TargetPassConfig(TM, PM) {
936   // Exceptions and StackMaps are not supported, so these passes will never do
937   // anything.
938   disablePass(&StackMapLivenessID);
939   disablePass(&FuncletLayoutID);
940   // Garbage collection is not supported.
941   disablePass(&GCLoweringID);
942   disablePass(&ShadowStackGCLoweringID);
943 }
944 
945 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
946   if (getOptLevel() == CodeGenOpt::Aggressive)
947     addPass(createGVNPass());
948   else
949     addPass(createEarlyCSEPass());
950 }
951 
952 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
953   addPass(createSeparateConstOffsetFromGEPPass());
954   // ReassociateGEPs exposes more opportunities for SLSR. See
955   // the example in reassociate-geps-and-slsr.ll.
956   addPass(createStraightLineStrengthReducePass());
957   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
958   // EarlyCSE can reuse.
959   addEarlyCSEOrGVNPass();
960   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
961   addPass(createNaryReassociatePass());
962   // NaryReassociate on GEPs creates redundant common expressions, so run
963   // EarlyCSE after it.
964   addPass(createEarlyCSEPass());
965 }
966 
967 void AMDGPUPassConfig::addIRPasses() {
968   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
969 
970   // There is no reason to run these.
971   disablePass(&StackMapLivenessID);
972   disablePass(&FuncletLayoutID);
973   disablePass(&PatchableFunctionID);
974 
975   addPass(createAMDGPUPrintfRuntimeBinding());
976   if (LowerCtorDtor)
977     addPass(createAMDGPUCtorDtorLoweringLegacyPass());
978 
979   // Function calls are not supported, so make sure we inline everything.
980   addPass(createAMDGPUAlwaysInlinePass());
981   addPass(createAlwaysInlinerLegacyPass());
982 
983   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
984   if (TM.getTargetTriple().getArch() == Triple::r600)
985     addPass(createR600OpenCLImageTypeLoweringPass());
986 
987   // Replace OpenCL enqueued block function pointers with global variables.
988   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
989 
990   // Runs before PromoteAlloca so the latter can account for function uses
991   if (EnableLowerModuleLDS) {
992     addPass(createAMDGPULowerModuleLDSPass());
993   }
994 
995   // AMDGPUAttributor infers lack of llvm.amdgcn.lds.kernel.id calls, so run
996   // after their introduction
997   if (TM.getOptLevel() > CodeGenOpt::None)
998     addPass(createAMDGPUAttributorPass());
999 
1000   if (TM.getOptLevel() > CodeGenOpt::None)
1001     addPass(createInferAddressSpacesPass());
1002 
1003   addPass(createAtomicExpandPass());
1004 
1005   if (TM.getOptLevel() > CodeGenOpt::None) {
1006     addPass(createAMDGPUPromoteAlloca());
1007 
1008     if (EnableSROA)
1009       addPass(createSROAPass());
1010     if (isPassEnabled(EnableScalarIRPasses))
1011       addStraightLineScalarOptimizationPasses();
1012 
1013     if (EnableAMDGPUAliasAnalysis) {
1014       addPass(createAMDGPUAAWrapperPass());
1015       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
1016                                              AAResults &AAR) {
1017         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
1018           AAR.addAAResult(WrapperPass->getResult());
1019         }));
1020     }
1021 
1022     if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
1023       // TODO: May want to move later or split into an early and late one.
1024       addPass(createAMDGPUCodeGenPreparePass());
1025     }
1026 
1027     // Try to hoist loop invariant parts of divisions AMDGPUCodeGenPrepare may
1028     // have expanded.
1029     if (TM.getOptLevel() > CodeGenOpt::Less)
1030       addPass(createLICMPass());
1031   }
1032 
1033   TargetPassConfig::addIRPasses();
1034 
1035   // EarlyCSE is not always strong enough to clean up what LSR produces. For
1036   // example, GVN can combine
1037   //
1038   //   %0 = add %a, %b
1039   //   %1 = add %b, %a
1040   //
1041   // and
1042   //
1043   //   %0 = shl nsw %a, 2
1044   //   %1 = shl %a, 2
1045   //
1046   // but EarlyCSE can do neither of them.
1047   if (isPassEnabled(EnableScalarIRPasses))
1048     addEarlyCSEOrGVNPass();
1049 }
1050 
1051 void AMDGPUPassConfig::addCodeGenPrepare() {
1052   if (TM->getTargetTriple().getArch() == Triple::amdgcn) {
1053     if (RemoveIncompatibleFunctions)
1054       addPass(createAMDGPURemoveIncompatibleFunctionsPass(TM));
1055 
1056     // FIXME: This pass adds 2 hacky attributes that can be replaced with an
1057     // analysis, and should be removed.
1058     addPass(createAMDGPUAnnotateKernelFeaturesPass());
1059   }
1060 
1061   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
1062       EnableLowerKernelArguments)
1063     addPass(createAMDGPULowerKernelArgumentsPass());
1064 
1065   TargetPassConfig::addCodeGenPrepare();
1066 
1067   if (isPassEnabled(EnableLoadStoreVectorizer))
1068     addPass(createLoadStoreVectorizerPass());
1069 
1070   // LowerSwitch pass may introduce unreachable blocks that can
1071   // cause unexpected behavior for subsequent passes. Placing it
1072   // here seems better that these blocks would get cleaned up by
1073   // UnreachableBlockElim inserted next in the pass flow.
1074   addPass(createLowerSwitchPass());
1075 }
1076 
1077 bool AMDGPUPassConfig::addPreISel() {
1078   if (TM->getOptLevel() > CodeGenOpt::None)
1079     addPass(createFlattenCFGPass());
1080   return false;
1081 }
1082 
1083 bool AMDGPUPassConfig::addInstSelector() {
1084   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine(), getOptLevel()));
1085   return false;
1086 }
1087 
1088 bool AMDGPUPassConfig::addGCPasses() {
1089   // Do nothing. GC is not supported.
1090   return false;
1091 }
1092 
1093 llvm::ScheduleDAGInstrs *
1094 AMDGPUPassConfig::createMachineScheduler(MachineSchedContext *C) const {
1095   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1096   ScheduleDAGMILive *DAG = createGenericSchedLive(C);
1097   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1098   if (ST.shouldClusterStores())
1099     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1100   return DAG;
1101 }
1102 
1103 MachineFunctionInfo *R600TargetMachine::createMachineFunctionInfo(
1104     BumpPtrAllocator &Allocator, const Function &F,
1105     const TargetSubtargetInfo *STI) const {
1106   return R600MachineFunctionInfo::create<R600MachineFunctionInfo>(
1107       Allocator, F, static_cast<const R600Subtarget *>(STI));
1108 }
1109 
1110 //===----------------------------------------------------------------------===//
1111 // GCN Pass Setup
1112 //===----------------------------------------------------------------------===//
1113 
1114 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1115   MachineSchedContext *C) const {
1116   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1117   if (ST.enableSIScheduler())
1118     return createSIMachineScheduler(C);
1119 
1120   if (EnableMaxIlpSchedStrategy)
1121     return createGCNMaxILPMachineScheduler(C);
1122 
1123   return createGCNMaxOccupancyMachineScheduler(C);
1124 }
1125 
1126 bool GCNPassConfig::addPreISel() {
1127   AMDGPUPassConfig::addPreISel();
1128 
1129   if (TM->getOptLevel() > CodeGenOpt::None)
1130     addPass(createAMDGPULateCodeGenPreparePass());
1131 
1132   if ((TM->getOptLevel() >= CodeGenOpt::Less) &&
1133       (AMDGPUAtomicOptimizerStrategy != ScanOptions::None)) {
1134     addPass(createAMDGPUAtomicOptimizerPass(AMDGPUAtomicOptimizerStrategy));
1135   }
1136 
1137   if (TM->getOptLevel() > CodeGenOpt::None)
1138     addPass(createSinkingPass());
1139 
1140   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1141   // regions formed by them.
1142   addPass(&AMDGPUUnifyDivergentExitNodesID);
1143   if (!LateCFGStructurize) {
1144     if (EnableStructurizerWorkarounds) {
1145       addPass(createFixIrreduciblePass());
1146       addPass(createUnifyLoopExitsPass());
1147     }
1148     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1149   }
1150   addPass(createAMDGPUAnnotateUniformValues());
1151   if (!LateCFGStructurize) {
1152     addPass(createSIAnnotateControlFlowPass());
1153     // TODO: Move this right after structurizeCFG to avoid extra divergence
1154     // analysis. This depends on stopping SIAnnotateControlFlow from making
1155     // control flow modifications.
1156     addPass(createAMDGPURewriteUndefForPHIPass());
1157   }
1158   addPass(createLCSSAPass());
1159 
1160   if (TM->getOptLevel() > CodeGenOpt::Less)
1161     addPass(&AMDGPUPerfHintAnalysisID);
1162 
1163   return false;
1164 }
1165 
1166 void GCNPassConfig::addMachineSSAOptimization() {
1167   TargetPassConfig::addMachineSSAOptimization();
1168 
1169   // We want to fold operands after PeepholeOptimizer has run (or as part of
1170   // it), because it will eliminate extra copies making it easier to fold the
1171   // real source operand. We want to eliminate dead instructions after, so that
1172   // we see fewer uses of the copies. We then need to clean up the dead
1173   // instructions leftover after the operands are folded as well.
1174   //
1175   // XXX - Can we get away without running DeadMachineInstructionElim again?
1176   addPass(&SIFoldOperandsID);
1177   if (EnableDPPCombine)
1178     addPass(&GCNDPPCombineID);
1179   addPass(&SILoadStoreOptimizerID);
1180   if (isPassEnabled(EnableSDWAPeephole)) {
1181     addPass(&SIPeepholeSDWAID);
1182     addPass(&EarlyMachineLICMID);
1183     addPass(&MachineCSEID);
1184     addPass(&SIFoldOperandsID);
1185   }
1186   addPass(&DeadMachineInstructionElimID);
1187   addPass(createSIShrinkInstructionsPass());
1188 }
1189 
1190 bool GCNPassConfig::addILPOpts() {
1191   if (EnableEarlyIfConversion)
1192     addPass(&EarlyIfConverterID);
1193 
1194   TargetPassConfig::addILPOpts();
1195   return false;
1196 }
1197 
1198 bool GCNPassConfig::addInstSelector() {
1199   AMDGPUPassConfig::addInstSelector();
1200   addPass(&SIFixSGPRCopiesID);
1201   addPass(createSILowerI1CopiesPass());
1202   return false;
1203 }
1204 
1205 bool GCNPassConfig::addIRTranslator() {
1206   addPass(new IRTranslator(getOptLevel()));
1207   return false;
1208 }
1209 
1210 void GCNPassConfig::addPreLegalizeMachineIR() {
1211   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1212   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1213   addPass(new Localizer());
1214 }
1215 
1216 bool GCNPassConfig::addLegalizeMachineIR() {
1217   addPass(new Legalizer());
1218   return false;
1219 }
1220 
1221 void GCNPassConfig::addPreRegBankSelect() {
1222   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1223   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1224 }
1225 
1226 bool GCNPassConfig::addRegBankSelect() {
1227   addPass(new AMDGPURegBankSelect());
1228   return false;
1229 }
1230 
1231 void GCNPassConfig::addPreGlobalInstructionSelect() {
1232   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1233   addPass(createAMDGPURegBankCombiner(IsOptNone));
1234 }
1235 
1236 bool GCNPassConfig::addGlobalInstructionSelect() {
1237   addPass(new InstructionSelect(getOptLevel()));
1238   return false;
1239 }
1240 
1241 void GCNPassConfig::addPreRegAlloc() {
1242   if (LateCFGStructurize) {
1243     addPass(createAMDGPUMachineCFGStructurizerPass());
1244   }
1245 }
1246 
1247 void GCNPassConfig::addFastRegAlloc() {
1248   // FIXME: We have to disable the verifier here because of PHIElimination +
1249   // TwoAddressInstructions disabling it.
1250 
1251   // This must be run immediately after phi elimination and before
1252   // TwoAddressInstructions, otherwise the processing of the tied operand of
1253   // SI_ELSE will introduce a copy of the tied operand source after the else.
1254   insertPass(&PHIEliminationID, &SILowerControlFlowID);
1255 
1256   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1257   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1258 
1259   TargetPassConfig::addFastRegAlloc();
1260 }
1261 
1262 void GCNPassConfig::addOptimizedRegAlloc() {
1263   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1264   // instructions that cause scheduling barriers.
1265   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1266   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1267 
1268   if (OptExecMaskPreRA)
1269     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1270 
1271   if (EnableRewritePartialRegUses)
1272     insertPass(&RenameIndependentSubregsID, &GCNRewritePartialRegUsesID);
1273 
1274   if (isPassEnabled(EnablePreRAOptimizations))
1275     insertPass(&RenameIndependentSubregsID, &GCNPreRAOptimizationsID);
1276 
1277   // This is not an essential optimization and it has a noticeable impact on
1278   // compilation time, so we only enable it from O2.
1279   if (TM->getOptLevel() > CodeGenOpt::Less)
1280     insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1281 
1282   // FIXME: when an instruction has a Killed operand, and the instruction is
1283   // inside a bundle, seems only the BUNDLE instruction appears as the Kills of
1284   // the register in LiveVariables, this would trigger a failure in verifier,
1285   // we should fix it and enable the verifier.
1286   if (OptVGPRLiveRange)
1287     insertPass(&LiveVariablesID, &SIOptimizeVGPRLiveRangeID);
1288   // This must be run immediately after phi elimination and before
1289   // TwoAddressInstructions, otherwise the processing of the tied operand of
1290   // SI_ELSE will introduce a copy of the tied operand source after the else.
1291   insertPass(&PHIEliminationID, &SILowerControlFlowID);
1292 
1293   if (EnableDCEInRA)
1294     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1295 
1296   TargetPassConfig::addOptimizedRegAlloc();
1297 }
1298 
1299 bool GCNPassConfig::addPreRewrite() {
1300   addPass(&SILowerWWMCopiesID);
1301   if (EnableRegReassign)
1302     addPass(&GCNNSAReassignID);
1303   return true;
1304 }
1305 
1306 FunctionPass *GCNPassConfig::createSGPRAllocPass(bool Optimized) {
1307   // Initialize the global default.
1308   llvm::call_once(InitializeDefaultSGPRRegisterAllocatorFlag,
1309                   initializeDefaultSGPRRegisterAllocatorOnce);
1310 
1311   RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
1312   if (Ctor != useDefaultRegisterAllocator)
1313     return Ctor();
1314 
1315   if (Optimized)
1316     return createGreedyRegisterAllocator(onlyAllocateSGPRs);
1317 
1318   return createFastRegisterAllocator(onlyAllocateSGPRs, false);
1319 }
1320 
1321 FunctionPass *GCNPassConfig::createVGPRAllocPass(bool Optimized) {
1322   // Initialize the global default.
1323   llvm::call_once(InitializeDefaultVGPRRegisterAllocatorFlag,
1324                   initializeDefaultVGPRRegisterAllocatorOnce);
1325 
1326   RegisterRegAlloc::FunctionPassCtor Ctor = VGPRRegisterRegAlloc::getDefault();
1327   if (Ctor != useDefaultRegisterAllocator)
1328     return Ctor();
1329 
1330   if (Optimized)
1331     return createGreedyVGPRRegisterAllocator();
1332 
1333   return createFastVGPRRegisterAllocator();
1334 }
1335 
1336 FunctionPass *GCNPassConfig::createRegAllocPass(bool Optimized) {
1337   llvm_unreachable("should not be used");
1338 }
1339 
1340 static const char RegAllocOptNotSupportedMessage[] =
1341   "-regalloc not supported with amdgcn. Use -sgpr-regalloc and -vgpr-regalloc";
1342 
1343 bool GCNPassConfig::addRegAssignAndRewriteFast() {
1344   if (!usingDefaultRegAlloc())
1345     report_fatal_error(RegAllocOptNotSupportedMessage);
1346 
1347   addPass(&GCNPreRALongBranchRegID);
1348 
1349   addPass(createSGPRAllocPass(false));
1350 
1351   // Equivalent of PEI for SGPRs.
1352   addPass(&SILowerSGPRSpillsID);
1353 
1354   addPass(createVGPRAllocPass(false));
1355 
1356   addPass(&SILowerWWMCopiesID);
1357   return true;
1358 }
1359 
1360 bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
1361   if (!usingDefaultRegAlloc())
1362     report_fatal_error(RegAllocOptNotSupportedMessage);
1363 
1364   addPass(&GCNPreRALongBranchRegID);
1365 
1366   addPass(createSGPRAllocPass(true));
1367 
1368   // Commit allocated register changes. This is mostly necessary because too
1369   // many things rely on the use lists of the physical registers, such as the
1370   // verifier. This is only necessary with allocators which use LiveIntervals,
1371   // since FastRegAlloc does the replacements itself.
1372   addPass(createVirtRegRewriter(false));
1373 
1374   // Equivalent of PEI for SGPRs.
1375   addPass(&SILowerSGPRSpillsID);
1376 
1377   addPass(createVGPRAllocPass(true));
1378 
1379   addPreRewrite();
1380   addPass(&VirtRegRewriterID);
1381 
1382   return true;
1383 }
1384 
1385 void GCNPassConfig::addPostRegAlloc() {
1386   addPass(&SIFixVGPRCopiesID);
1387   if (getOptLevel() > CodeGenOpt::None)
1388     addPass(&SIOptimizeExecMaskingID);
1389   TargetPassConfig::addPostRegAlloc();
1390 }
1391 
1392 void GCNPassConfig::addPreSched2() {
1393   if (TM->getOptLevel() > CodeGenOpt::None)
1394     addPass(createSIShrinkInstructionsPass());
1395   addPass(&SIPostRABundlerID);
1396 }
1397 
1398 void GCNPassConfig::addPreEmitPass() {
1399   if (isPassEnabled(EnableVOPD, CodeGenOpt::Less))
1400     addPass(&GCNCreateVOPDID);
1401   addPass(createSIMemoryLegalizerPass());
1402   addPass(createSIInsertWaitcntsPass());
1403 
1404   addPass(createSIModeRegisterPass());
1405 
1406   if (getOptLevel() > CodeGenOpt::None)
1407     addPass(&SIInsertHardClausesID);
1408 
1409   addPass(&SILateBranchLoweringPassID);
1410   if (isPassEnabled(EnableSetWavePriority, CodeGenOpt::Less))
1411     addPass(createAMDGPUSetWavePriorityPass());
1412   if (getOptLevel() > CodeGenOpt::None)
1413     addPass(&SIPreEmitPeepholeID);
1414   // The hazard recognizer that runs as part of the post-ra scheduler does not
1415   // guarantee to be able handle all hazards correctly. This is because if there
1416   // are multiple scheduling regions in a basic block, the regions are scheduled
1417   // bottom up, so when we begin to schedule a region we don't know what
1418   // instructions were emitted directly before it.
1419   //
1420   // Here we add a stand-alone hazard recognizer pass which can handle all
1421   // cases.
1422   addPass(&PostRAHazardRecognizerID);
1423 
1424   if (isPassEnabled(EnableInsertDelayAlu, CodeGenOpt::Less))
1425     addPass(&AMDGPUInsertDelayAluID);
1426 
1427   addPass(&BranchRelaxationPassID);
1428 }
1429 
1430 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1431   return new GCNPassConfig(*this, PM);
1432 }
1433 
1434 void GCNTargetMachine::registerMachineRegisterInfoCallback(
1435     MachineFunction &MF) const {
1436   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1437   MF.getRegInfo().addDelegate(MFI);
1438 }
1439 
1440 MachineFunctionInfo *GCNTargetMachine::createMachineFunctionInfo(
1441     BumpPtrAllocator &Allocator, const Function &F,
1442     const TargetSubtargetInfo *STI) const {
1443   return SIMachineFunctionInfo::create<SIMachineFunctionInfo>(
1444       Allocator, F, static_cast<const GCNSubtarget *>(STI));
1445 }
1446 
1447 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1448   return new yaml::SIMachineFunctionInfo();
1449 }
1450 
1451 yaml::MachineFunctionInfo *
1452 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1453   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1454   return new yaml::SIMachineFunctionInfo(
1455       *MFI, *MF.getSubtarget<GCNSubtarget>().getRegisterInfo(), MF);
1456 }
1457 
1458 bool GCNTargetMachine::parseMachineFunctionInfo(
1459     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1460     SMDiagnostic &Error, SMRange &SourceRange) const {
1461   const yaml::SIMachineFunctionInfo &YamlMFI =
1462       static_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1463   MachineFunction &MF = PFS.MF;
1464   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1465 
1466   if (MFI->initializeBaseYamlFields(YamlMFI, MF, PFS, Error, SourceRange))
1467     return true;
1468 
1469   if (MFI->Occupancy == 0) {
1470     // Fixup the subtarget dependent default value.
1471     const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1472     MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1473   }
1474 
1475   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1476     Register TempReg;
1477     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1478       SourceRange = RegName.SourceRange;
1479       return true;
1480     }
1481     RegVal = TempReg;
1482 
1483     return false;
1484   };
1485 
1486   auto parseOptionalRegister = [&](const yaml::StringValue &RegName,
1487                                    Register &RegVal) {
1488     return !RegName.Value.empty() && parseRegister(RegName, RegVal);
1489   };
1490 
1491   if (parseOptionalRegister(YamlMFI.VGPRForAGPRCopy, MFI->VGPRForAGPRCopy))
1492     return true;
1493 
1494   if (parseOptionalRegister(YamlMFI.SGPRForEXECCopy, MFI->SGPRForEXECCopy))
1495     return true;
1496 
1497   if (parseOptionalRegister(YamlMFI.LongBranchReservedReg,
1498                             MFI->LongBranchReservedReg))
1499     return true;
1500 
1501   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1502     // Create a diagnostic for a the register string literal.
1503     const MemoryBuffer &Buffer =
1504         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1505     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1506                          RegName.Value.size(), SourceMgr::DK_Error,
1507                          "incorrect register class for field", RegName.Value,
1508                          std::nullopt, std::nullopt);
1509     SourceRange = RegName.SourceRange;
1510     return true;
1511   };
1512 
1513   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1514       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1515       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1516     return true;
1517 
1518   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1519       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1520     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1521   }
1522 
1523   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1524       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1525     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1526   }
1527 
1528   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1529       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1530     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1531   }
1532 
1533   for (const auto &YamlReg : YamlMFI.WWMReservedRegs) {
1534     Register ParsedReg;
1535     if (parseRegister(YamlReg, ParsedReg))
1536       return true;
1537 
1538     MFI->reserveWWMRegister(ParsedReg);
1539   }
1540 
1541   auto parseAndCheckArgument = [&](const std::optional<yaml::SIArgument> &A,
1542                                    const TargetRegisterClass &RC,
1543                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1544                                    unsigned SystemSGPRs) {
1545     // Skip parsing if it's not present.
1546     if (!A)
1547       return false;
1548 
1549     if (A->IsRegister) {
1550       Register Reg;
1551       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1552         SourceRange = A->RegisterName.SourceRange;
1553         return true;
1554       }
1555       if (!RC.contains(Reg))
1556         return diagnoseRegisterClass(A->RegisterName);
1557       Arg = ArgDescriptor::createRegister(Reg);
1558     } else
1559       Arg = ArgDescriptor::createStack(A->StackOffset);
1560     // Check and apply the optional mask.
1561     if (A->Mask)
1562       Arg = ArgDescriptor::createArg(Arg, *A->Mask);
1563 
1564     MFI->NumUserSGPRs += UserSGPRs;
1565     MFI->NumSystemSGPRs += SystemSGPRs;
1566     return false;
1567   };
1568 
1569   if (YamlMFI.ArgInfo &&
1570       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1571                              AMDGPU::SGPR_128RegClass,
1572                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1573        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1574                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1575                              2, 0) ||
1576        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1577                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1578        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1579                              AMDGPU::SReg_64RegClass,
1580                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1581        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1582                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1583                              2, 0) ||
1584        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1585                              AMDGPU::SReg_64RegClass,
1586                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1587        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1588                              AMDGPU::SGPR_32RegClass,
1589                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1590        parseAndCheckArgument(YamlMFI.ArgInfo->LDSKernelId,
1591                              AMDGPU::SGPR_32RegClass,
1592                              MFI->ArgInfo.LDSKernelId, 0, 1) ||
1593        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1594                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1595                              0, 1) ||
1596        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1597                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1598                              0, 1) ||
1599        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1600                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1601                              0, 1) ||
1602        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1603                              AMDGPU::SGPR_32RegClass,
1604                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1605        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1606                              AMDGPU::SGPR_32RegClass,
1607                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1608        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1609                              AMDGPU::SReg_64RegClass,
1610                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1611        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1612                              AMDGPU::SReg_64RegClass,
1613                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1614        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1615                              AMDGPU::VGPR_32RegClass,
1616                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1617        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1618                              AMDGPU::VGPR_32RegClass,
1619                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1620        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1621                              AMDGPU::VGPR_32RegClass,
1622                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1623     return true;
1624 
1625   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1626   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1627 
1628   // FIXME: Move proper support for denormal-fp-math into base MachineFunction
1629   MFI->Mode.FP32Denormals.Input = YamlMFI.Mode.FP32InputDenormals
1630                                       ? DenormalMode::IEEE
1631                                       : DenormalMode::PreserveSign;
1632   MFI->Mode.FP32Denormals.Output = YamlMFI.Mode.FP32OutputDenormals
1633                                        ? DenormalMode::IEEE
1634                                        : DenormalMode::PreserveSign;
1635 
1636   MFI->Mode.FP64FP16Denormals.Input = YamlMFI.Mode.FP64FP16InputDenormals
1637                                           ? DenormalMode::IEEE
1638                                           : DenormalMode::PreserveSign;
1639   MFI->Mode.FP64FP16Denormals.Output = YamlMFI.Mode.FP64FP16OutputDenormals
1640                                            ? DenormalMode::IEEE
1641                                            : DenormalMode::PreserveSign;
1642 
1643   return false;
1644 }
1645